Abstract: A semiconductor device includes a bidirectional GaN FET formed on a non-insulating substrate. The semiconductor device further includes a first electrical clamp connected between the substrate and a first source/drain node of the bidirectional GaN FET, and a second electrical clamp connected between the substrate and a second source/drain node of the bidirectional GaN FET. The first clamp and the second clamp are configured to bias the substrate at a lower voltage level of an applied bias to the first source/drain node and an applied bias to the second source/drain node, within an offset voltage of the relevant clamp.

Abstract: Aspects of the present disclosure describe high voltage fast recovery trench diodes and methods for make the same. The device may have trenches that extend at least through a top P-layer and an N-barrier layer. A conductive material may be disposed in the trenches with a dielectric material lining the trenches between the conductive material and sidewalls of the trenches. A highly doped P-pocket may be formed in an upper portion of the top P-layer between the trenches. A floating N-pocket may be formed directly underneath the P-pocket. The floating N-pocket may be as wide as or wider than the P-pocket. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A semiconductor device including buried bit lines formed of a metal silicide and silicidation preventing regions formed in a substrate under trenches that separate the buried bit lines.

Abstract: Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body; forming a source; forming an active region contact trench that extends through the source and the body into a drain; forming a Schottky barrier controlling layer in the epitaxial layer in bottom region of the active region contact trench; and disposing a contact electrode within the active region contact trench. The Schottky barrier controlling layer controls Schottky barrier height of a Schottky diode formed by the contact electrode and the drain.

Abstract: A semiconductor device with an embedded schottky diode and a manufacturing method thereof are provided. A semiconductor device having a schottky diode include: an epilayer of a first conductivity type, a body layer of a second conductivity type, and a source layer of the first conductivity type arranged in that order; a gate trench that extends from the source layer to a part of the epilayer; a body trench formed a predetermined distance from the gate trench and extends from the source layer to a part of the epilayer; and a guard ring of the second conductivity type that contacts an outer wall of the body trench and formed in the epilayer.

Abstract: An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.

Abstract: Aspects of the disclosure provide a dual electrostatic discharge (ESD) protection device in fin field effect transistor (FinFET) process technology and methods of forming the same. In one embodiment, the dual ESD protection device includes: a bulk silicon substrate; a shallow trench isolation (STI) region formed over the bulk silicon substrate; a first ESD device positioned above the STI region; and a second ESD device positioned below the STI region, wherein the first ESD device conducts current above the STI region and the second ESD device conducts current below the STI region.

Abstract: A trench Schottky rectifier device includes a substrate having a first conductivity type, a plurality of trenches formed in the substrate, and an insulating layer formed on sidewalls of the trenches. The trenches are filled with conductive structure. There is an electrode overlying the conductive structure and the substrate, and thus a Schottky contact forms between the electrode and the substrate. A plurality of embedded doped regions having a second conductivity type are formed in the substrate and located under the trenches. Each doped region and the substrate form a PN junction to pinch off current flowing toward the Schottky contact so as to suppress current leakage.

Abstract: A semiconductor device comprises a first substrate portion and a second substrate portion disposed a distance away from the first substrate portion. The first substrate portion includes a first active semiconductor layer defining at least one semiconductor fin and a first polycrystalline layer formed directly on the fin. The first polycrystalline layer is patterned to define at least one semiconductor gate. The second substrate portion includes a doped region interposed between a second active semiconductor region and an oxide layer. The oxide layer protects the second active semiconductor region and the doped region. The doped region includes a first doped area and a second doped area separated by the first doped region to define a depletion region.

Abstract: A method of forming a memory cell is provided, the method including forming a diode including a first region having a first conductivity type, counter-doping the diode to change the first region to a second conductivity type, and forming a memory element coupled in series with the diode. Other aspects are also provided.

Abstract: A phase change memory apparatus is provided that includes a first electrode that is longer than it is wide, the first electrode having a trench formed on an active region of a semiconductor substrate, a second electrode formed in a bottom portion of the trench, and a bottom electrode contact formed on the second electrode.

Abstract: A method for forming a Schottky diode including forming first and second trenches in a semiconductor layer, forming a thin dielectric layer lining sidewalls of the first and second trenches; forming a trench conductor layer in the first and second trenches where the trench conductor layer fills a portion of each of the first and second trenches and being the only one trench conductor layer in the first and second trenches; forming a first dielectric layer in the first and second trenches to fill the remaining portions of the first and second trenches; and forming a Schottky metal layer on a top surface of the lightly doped semiconductor layer between the first trench and the second trench to form a Schottky junction. The Schottky diode is formed with the Schottky metal layer as the anode and the lightly doped semiconductor layer between the first and second trenches as the cathode.

Abstract: An integrated circuit contains a voltage protection structure having a diode isolated DENMOS transistor with a guard element proximate to the diode and the DENMOS transistor. The guard element includes an active area coupled to ground. The diode anode is connected to an I/O pad. The diode cathode is connected to the DENMOS drain. The DENMOS source is grounded. A process of forming the integrated circuit is also disclosed.

Abstract: A three-dimensional (3D) gate driver integrated circuit includes a high-side integrated circuit stacked on a low-side integrated circuit where the high-side integrated circuit and the low-side integrated circuit are interconnected using through-silicon vias (TSV). As thus formed, the high-side integrated circuit and the low-side integrated circuit can be formed without termination regions and without buried layers. The 3D gate driver integrated circuit improves ease of high voltage integration and improves the ruggedness and reliability of the gate driver integrated circuit.

Abstract: A laterally diffused metal oxide semiconductor (LDMOS) device, and a method of manufacturing the same are provided. The LDMOS device can include a drain region of a bootstrap field effect transistor (FET), a source region of the bootstrap FET, a drift region formed between the drain region and the source region, and a gate formed at one side of the source region and on the drift region.

Abstract: A semiconductor device includes a first conduction type semiconductor substrate, a first conduction type semiconductor deposition layer, a trench, second conduction type wells, a JFET region, a first conduction type first source region, a first source region, a trench-type source electrode, a gate insulator film, a gate electrode, and a drain electrode. The trench is formed substantially perpendicularly to the semiconductor deposition layer so that the semiconductor deposition layer exposes to a bottom of the trench. The second conduction type second source region are formed in the first conduction type first source region. The trench-type source electrode is in contact with the first source region, the second source region, and the first conduction type semiconductor deposition layer to configure a Schottky junction.

Abstract: A zener diode in a SiGe BiCMOS process is disclosed. An N-type region of the zener diode is formed in an active region and surrounded by an N-deep well. A pseudo buried layer is formed under each of the shallow trench field oxide regions on a corresponding side of the active region, and the N-type region is connected to the pseudo buried layers via the N-deep well. The N-type region has its electrode picked up by deep hole contacts. A P-type region of the zener diode is formed of a P-type ion implanted region in the active region. The P-type region is situated above and in contact with the N-type region, and has a doping concentration greater than that of the N-type region. The P-type region has its electrode picked up by metal contact. A method of fabricating zener diode in a SiGe BiCMOS process is also disclosed.

Abstract: A semiconductor device and method of making such device is presented herein. The semiconductor device includes a plurality of memory cells, a plurality of p-n junctions, and a metal trace of a first metal layer. Each of the plurality of memory cells includes a first gate disposed over a first dielectric, a second gate disposed over a second dielectric and adjacent to a sidewall of the first gate, a first doped region in the substrate adjacent to the first gate, and a second doped region in the substrate adjacent to the second gate. The plurality of p-n junctions are electrically isolated from the doped regions of each memory cell. The metal trace extends along a single plane between a via to the second gate of at least one memory cell in the plurality of memory cells, and a via to a p-n junction within the plurality of p-n junctions.

Abstract: Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)<TBCD is created into side walls of TCT and beneath SCD. An embedded Shannon implant region (ESIR) is created into sub-contact trench zone (SCTZ) beneath TCT floor. A metal layer is formed in contact with ESIR, body and source region. The metal layer also fills TCT and covers dielectric region thus completing the MOSFET/SKY with only one-time etching of its TCT.

Abstract: Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided.

Abstract: Contact with a floating body of an FET in SOI may be formed in a portion of one of the two diffusions of the FET, wherein the portion of the diffusion (such as N?, for an NFET) which is “sacrificed” for making the contact is a portion of the diffusion which is not immediately adjacent (or under) the gate. This works well with linked body FETs, wherein the diffusion does not extend all the way to BOX, hence the linked body (such as P?) extends under the diffusion where the contact is being made. An example showing making contact for ground to two NFETs (PG and PD) of a 6T SRAM cell is shown.

Abstract: Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body; forming a source; forming an active region contact trench that extends through the source and the body into the drain; forming a Schottky barrier controlling layer in the epitaxial layer in bottom region of the active region contact trench; and disposing a contact electrode within the active region contact trench.

Abstract: Methods and systems for lateral switched-emitter thyristors in a single-layer implementation. Lateral operation is advantageously achieved by using an embedded gate. Embedded gate plugs are used to controllably invert a portion of the P-base region, so that the electron population at the portion of the inversion layer which is closest to the anode will provide a virtual emitter, and will provide sufficient gain so that the combination of bipolar devices will go into latchup.

Abstract: A semiconductor device includes an n-type drift layer formed on a main surface of a semiconductor substrate, a plurality of p-type well regions formed selectively in an upper layer portion of the drift layer, an n-type source region formed in a surface of the p-type well region, and a p-type contact region which is shallower than the source region formed in the surface of the p-type well region adjacent to the source region. Moreover, the semiconductor device includes an n-type additional region formed in contact with a bottom surface of the p-type well region in a position corresponding to below the contact region and deeper than the p-type well region.

Abstract: A method of manufacturing a diode is provided. An N-type well region is formed in a first upper portion of an N-type epitaxial layer. A P-type drift region is formed in a second upper portion of the N-type epitaxial layer. An N-type doping region is formed in the N-type well region. A P-type doping region is formed in the P-type drift region. An isolation structure is formed in the P-type drift region. The isolation structure is disposed between the P-type doping region and the N-type well region. A first electrode is formed on a portion of the N-type epitaxial layer. The portion of the N-type epitaxial layer is disposed between the N-type well region and the P-type drift region. The first electrode overlaps a portion of the isolation structure. A connection structure is formed to electrically couple the N-type doping region and the first electrode.

Abstract: A high density variable resistive random access memory device and a method of fabricating the same are provided. The device includes first word lines, each separated from each other by a width of first word line; bit lines, each separated from each other by a width of bit line; and second word lines, each located between two adjacent first word lines, wherein the widths of first word line and the bit line are substantially same, and the bit lines are located over the first and second word lines.

Abstract: A low-loss GaN-based semiconductor device is provided. The semiconductor device has the InzGa1-zN layer (where 0?z<1), the AlxGa1-xN layer (where 0<x<1), the InyGa1-yN layer (where 0?y<1) and the p-type InwGa1-wN layer (where 0?w<1) which are sequentially stacked on a base substrate of a C-plane sapphire substrate, etc. At a non-operating time, the two-dimensional hole gas is formed in the InyGa1-yN layer in the vicinity part of a hetero-interface between the AlxGa1-xN layer and the InyGa1-yN layer, and the two-dimensional electron gas is formed in the InzGa1-zN layer in the vicinity part of a hetero-interface between the InzGa1-zN layer and the AlxGa1-xN layer.

Abstract: A semiconductor device includes a plurality of trenches including active gate trenches in an active area and gate runner/termination trenches and shield electrode pickup trenches in a termination area outside the active area. The gate runner/termination trenches include one or more trenches that define a mesa located outside an active area. A first conductive region is formed in the plurality of trenches. An intermediate dielectric region and termination protection region are formed in the trenches that define the mesa. A second conductive region is formed in the portion of the trenches that define the mesa. The second conductive region is electrically isolated from the first conductive region by the intermediate dielectric region. A first electrical contact is made to the second conductive regions and a second electrical contact to the first conductive region in the shield electrode pickup trenches. One or more Schottky diodes are formed within the mesa.

Abstract: Memory devices are described along with methods for manufacturing and methods for operating. A memory device as described herein includes a plurality of memory cells located between word lines and bit lines. Memory cells in the plurality of memory cells comprise a diode and a metal-oxide memory element programmable to a plurality of resistance states including a first and a second resistance state, the diode of the memory element arranged in electrical series along a current path between a corresponding word line and a corresponding bit line. The device further includes bias circuitry to apply bias arrangements across the series arrangement of the diode and the memory element of a selected memory cell in the plurality of memory cells.

Abstract: A power cell including an isolation region having a first dopant type formed in a substrate. The power cell further includes a bottom gate having a second dopant type different from the first dopant type formed on the isolation region and a channel layer having the first dopant type formed on the bottom gate. The power cell further includes source/drain regions having the first dopant type formed in the channel layer and a first well region having the second dopant type formed around the channel layer and the source/drain regions, and the first well region electrically connected to the bottom gate. The power cell further includes a second well region having the first dopant type formed around the channel layer and contacting the isolation region and a gate structure formed on the channel layer.

Abstract: A semiconductor device containing a vertical power MOSFET with a planar gate and an integrated Schottky diode is formed by forming a source electrode on an extended drain of the vertical power MOSFET to form the Schottky diode and forming the source electrode on a source region of the vertical power MOSFET. The Schottky diode is connected through the source electrode to the source region. A drain electrode is formed at a bottom of a substrate of the semiconductor device. The Schottky diode is connected through the extended drain of the vertical power MOSFET to the drain electrode.

Abstract: Methods in accordance with the invention involve patterning and etching very small dimension pillars, such as in formation of a memory array in accordance with the invention. When dimensions of pillars become very small, the photoresist pillars used to pattern them may not have sufficient mechanical strength to survive the photoresist exposure and development process. Using methods according to the present invention, these photoresist pillars are printed and developed larger than their intended final dimension, such that they have increased mechanical strength, then are shrunk to the desired dimension during a preliminary etch performed before the etch of underlying material begins.

Abstract: An integrated structure combines field effect transistors and a Schottky diode. Trenches formed into a substrate composition extend along a depth of the substrate composition forming mesas therebetween. Each trench is filled with conductive material separated from the trench walls by dielectric material forming a gate region. Two first conductivity type body regions inside each mesa form wells partly into the depth of the substrate composition. An exposed portion of the substrate composition separates the body regions. Second conductivity type source regions inside each body region are adjacent to and on opposite sides of each well. Schottky barrier metal inside each well forms Schottky junctions at interfaces with exposed vertical sidewalls of the exposed portion of the substrate composition separating the body regions.

Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.

Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.

Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.

Abstract: Provided is an electrostatic discharge (ESD) protection diode that is formed on an input/output pad of an integrated circuit (IC), the ESD protection diode including: an N-type semiconductor that constitutes a first diode and is connected to a pad for a power supply voltage; a P-type semiconductor that constitutes the first diode and is connected to a signal line; an N-type semiconductor that constitutes a second diode and is connected to the signal line; a P-type semiconductor that constitutes the second diode and is connected to a pad for grounding; and a third diode that is formed by contacting the N-type semiconductor of the first diode and the P-type semiconductor of the second diode.

Abstract: Aspects of the present disclosure describe high voltage fast recovery trench diodes and methods for make the same. The device may have trenches that extend at least through a top P-layer and an N-barrier layer. A conductive material may be disposed in the trenches with a dielectric material lining the trenches between the conductive material and sidewalls of the trenches. A highly doped P-pocket may be formed in an upper portion of the top P-layer between the trenches. A floating N-pocket may be formed directly underneath the P-pocket. The floating N-pocket may be as wide as or wider than the P-pocket. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: An integrated circuit contains a voltage protection structure having a diode isolated DENMOS transistor with a guard element proximate to the diode and the DENMOS transistor. The guard element includes an active area coupled to ground. The diode anode is connected to an I/O pad. The diode cathode is connected to the DENMOS drain. The DENMOS source is grounded. A process of forming the integrated circuit is also disclosed.

Abstract: An object is to reduce the number of manufacturing steps of a semiconductor device, to improve yield of a semiconductor device, or to reduce manufacturing cost of a semiconductor device. One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes, over a substrate, a first transistor having a single crystal semiconductor layer in a channel formation region, a second transistor that is isolated from the first transistor with an insulating layer positioned therebetween and has an oxide semiconductor layer in a channel formation region, and a diode having a single crystal semiconductor layer and a oxide semiconductor layer.

Abstract: A semiconductor device is formed having compatibility with FINFET process flow, while having a large enough junction area of to reduce the discharge ESD current density. Embodiments include forming a removable gate over an N? doped fin on a substrate, forming P+ doped SiGe or Si on an anode side of the fin, and forming N+ doped Si on a cathode side of the fin. The area efficiency of the semiconductor device layout is greatly improved, and, thereby, discharge of ESD current density is mitigated.

Abstract: The PCRAM device includes a semiconductor substrate including a switching device; an interlayer insulating layer having a heating electrode contact hole exposing the switching device, a heating electrode formed to be extended along a side of the interlayer insulating layer in the heating electrode contact hole, wherein the heating electrode has a width gradually increased toward a bottom of the heating electrode and is in contact with the switching device, first and second phase-change layers formed within the heating electrode contact hole that includes the heating electrode, and a phase-change separation layer formed in the heating electrode contact hole between the first and second phase-change layers.

Abstract: A logic switch intentionally utilizes GIDL current as its primary mechanism of operation. Voltages may be applied to a doped gate overlying and insulated from a pn junction. A first voltage initiates GIDL current, and the logic switch is bidirectionally conductive. A second voltage terminates GIDL current, but the logic switch is unidirectionally conductive. A third voltage renders the logic switch bidirectionally non-conductive. Circuits containing the logic switch are also described. These circuits include inverters, SRAM cells, voltage reference sources, and neuron logic switches. The logic switch is primarily implemented according to SOI protocols, but embodiments according to bulk protocols are described.

Abstract: A VTMOS transistor in semiconductor material of a first type of conductivity includes a body region of a second type of conductivity and a source region of the first type of conductivity. A gate region extends into the main surface through the body region and is insulated from the semiconductor material. A region of the gate region extends onto the main surface is insulated from the rest of the gate region. An anode region of the first type of conductivity is formed into said insulated region, and a cathode region of the second type of conductivity is formed into said insulated region in contact with the anode region; the anode region and the cathode region define a thermal diode electrically insulated from the chip.

Abstract: There is provided a light emitting diode package and a method of manufacturing the same. A light emitting diode package according to an aspect of the invention may include: an LED chip; a body part having the LED chip mounted thereon; a pair of reflective parts extending from the body part to face each other while interposing the LED chip therebetween, and reflecting light emitted from the LED chip; and a molding part provided between the pair of reflective parts to encapsulate the LED chip and having a top surface whose central region is curved inwards.

Abstract: A method of forming one or more diodes in a fin field-effect transistor (FinFET) device includes forming a hardmask layer having a fin pattern, said fin pattern including an isolated fin area, a fin array area, and a FinFET area. The method further includes etching a plurality of fins into a semiconductor substrate using the fin pattern, and depositing a dielectric material over the semiconductor substrate to fill spaces between the plurality of fins. The method further includes planarizing the semiconductor substrate to expose the hardmask layer. The method further includes implanting a p-type dopant into the fin array area and portions of the FinFET area, and implanting an n-type dopant into the isolated fin area, a portion of the of fin array area surrounding the p-well and portions of the FinFET area. The method further includes annealing the semiconductor substrate.

Abstract: A method for forming a Schottky diode including forming first and second trenches in a semiconductor layer, forming a thin dielectric layer lining sidewalls of the first and second trenches; forming a trench conductor layer in the first and second trenches where the trench conductor layer fills a portion of each of the first and second trenches and being the only one trench conductor layer in the first and second trenches; forming a first dielectric layer in the first and second trenches to fill the remaining portions of the first and second trenches; and forming a Schottky metal layer on a top surface of the lightly doped semiconductor layer between the first trench and the second trench to form a Schottky junction. The Schottky diode is formed with the Schottky metal layer as the anode and the lightly doped semiconductor layer between the first and second trenches as the cathode.

Abstract: A first MOSFET is formed in a first region of a chip, and a second MOSFET is formed in a second region thereof. A first source terminal and a first gate terminal are formed in the first region. In the second region, a second source terminal and a second gate terminal are arranged so as to be aligned substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned. A temperature detection diode is arranged between the first source terminal and the second source terminal. A first terminal and a second terminal of the temperature detection diode are aligned in a first direction substantially parallel to a direction in which the first source terminal and the first gate terminal are aligned or in a second direction substantially perpendicular thereto.

Abstract: A method for producing a semiconductor device includes the steps of forming first and second pillar-shaped semiconductors on a substrate at the same time so as to have the same height; forming a first semiconductor layer by doping a bottom region of the first pillar-shaped semiconductor with a donor or acceptor impurity to connect the first semiconductor layer to the second pillar-shaped semiconductor; forming a circuit element including an upper semiconductor region formed by doping an upper region of the first pillar-shaped semiconductor with a donor or acceptor impurity; forming a first conductor layer in the second pillar-shaped semiconductor; forming first and second contact holes that are respectively connected to the first and second pillar-shaped semiconductors; and forming a wiring metal layer that is connected to the upper semiconductor region and the first conductor layer through the first and second contact holes, respectively.

Abstract: Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.