Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A power Schottky rectifier device and method of making the same are disclosed. The Schottky rectifier device includes a LOCOS structure grown on the bottom of the trenches by using nitride spacer on the sidewall of the trenches as a thermal oxidation mask. A polycrystalline silicon layer is then filled the first trenches. Under LOCOS structure, a p doped region is optionally formed to minimize the current leakage when the device undergoes a reverse biased. A Schottky barrier silicide layer formed by sputtering and annealing steps is formed on the upper surfaces of the epi-layer and the polycrystalline silicon layer. A top metal layer served as anode is then formed on the Schottky barrier silicide layer and extended to cover a portion of field oxide region of the termination trench. A metal layer served as a cathode electrode is then formed on the backside surface of the substrate opposite to the top metal layer.

Abstract: Electrostatic discharge (ESD) protection device in high voltage and the relevant manufacturing method is disclosed. The mentioned ESD protection device is disposed to bridge a ground and an input connected with an inner circuit to be protected. In which, the ESD protection device for high voltage comprises at least one PNP transistor and at least one diode connected in parallel, and an ESD discharging path is formed thereby. The PNP transistor is formed with an adjacent heavily doped P-type semiconductor zone (P+), lightly doped N-type semiconductor zone (N?), and a P-type semiconductor substrate. The diode is formed with an adjacent lightly doped N-type semiconductor zone and a light doped P-type semiconductor zone.

Abstract: A method of forming a monolithically integrated trench FET and Schottky diode includes the following steps. Two trenches are formed extending through an upper silicon layer and terminating within a lower silicon layer. The upper and lower silicon layers have a first conductivity type. First and second silicon regions of a second conductivity type are formed in the upper silicon layer between the pair of trenches. A third silicon region of the first conductivity type is formed extending into the first and second silicon regions between the pair of trenches such that remaining lower portions of the first and second silicon regions form two body regions separated by a portion of the upper silicon layer. A silicon etch is performed to form a contact opening extending through the first silicon region such that outer portions of the first silicon region remain, the outer portions forming source regions.

Abstract: A device of forming a film from an organic compound material at low cost is provided, using an organic compound material having high light emission efficiency. An organic compound film is formed on a substrate under an inert gas atmosphere by spraying of a colloid solution in which organic compound aggregates are dispersed (this solution is also referred to as a “sol”). Note that the organic compound may be one in which particles are composed of aggregates of several organic compounds within a liquid, and may be one in which a portion of the organic compound is dissolved within a liquid.

Abstract: A semiconductor device includes a substrate. The substrate includes a semiconductor material. An electrically isolated region is formed over the substrate. A metal-oxide-semiconductor field-effect transistor (MOSFET) is formed over the substrate within the electrically isolated region. The electrically isolated region includes a trench formed around the electrically isolated region. An insulative material such as silicon dioxide (SiO2) may be deposited into the trench. A diode is formed over the substrate within the electrically isolated region. In one embodiment, the diode is a Schottky diode. A metal layer may be formed over a surface of the substrate to form an anode of the diode. A first electrical connection is formed between a source of the MOSFET and an anode of the diode. A second electrical connection is formed between a drain of the MOSFET and a cathode of the diode.

Abstract: In fabricating an electronic structure, a substrate is provided, and a first barrier layer is provided on the substrate. A germanium thin film diode is provided on the first barrier layer, and a second barrier layer is provided on the germanium thin film diode. A memory device is provided over and connected to the second barrier layer.

Abstract: A lateral DMOS device and a fabrication method therefor that may include forming a second conductive type well in a first conductive type semiconductor substrate and forming a Schottky contact in contact with the second conductive type well in a Schottky diode region, thereby preventing breakdown of the device due to high voltage.

Abstract: A semiconductor device provided with a temperature detection function having a high temperature detection accuracy for improving the ESD resistance of a temperature detection diode. The semiconductor device has a semiconductor element. A temperature detection diode is used to detect the temperature of the semiconductor element and an ambient temperature of the semiconductor element. A protection diode is connected between a cathode of the temperature detection diode and a ground side of the semiconductor element when the semiconductor element is activated.

Abstract: A lateral DMOS device having a structure that prevents breakdown of a semiconductor device while enhancing the breakdown voltage property.

Abstract: This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.

Abstract: A semiconductor device which has a semiconductor body and a method for producing it. At the semiconductor body, a first electrode which is electrically connected to a first near-surface zone of the semiconductor body and a second electrode which is electrically connected to a second zone of the semiconductor body are arranged. A drift section is arranged between the first and the second electrode. In the drift section, a coupling structure is provided for at least one field plate arranged in the drift section. The coupling structure has a floating first area doped complementarily to the drift section and a second area arranged in the first area. The second area forms a locally limited punch-through effect or an ohmic contact to the drift section, and the field plate is electrically connected at least to the second area.

Abstract: Integrated circuit devices are provided having a vertical diode therein. The devices include an integrated circuit substrate and an insulating layer on the integrated circuit substrate. A contact hole penetrates the insulating layer. A vertical diode is in a lower region of the contact hole and a bottom electrode in the contact hole has a bottom surface on a top surface of the vertical diode. The bottom electrode is self-aligned with the vertical diode. A top surface area of the bottom electrode is less than a horizontal section area of the contact hole. Methods of forming the integrated circuit devices and phase change memory cells are also provided.

Abstract: A MOSFET device that includes a first Zener diode connected between a gate metal and a drain metal of said semiconductor power device for functioning as a gate-drain (GD) clamp diode. The GD clamp diode includes multiple back-to-back doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on an insulation layer above the MOSFET device, having an avalanche voltage lower than a source/drain avalanche voltage of the MOSFET device wherein the Zener diode is insulated from a doped region of the MOSFET device for preventing a channeling effect.

Abstract: In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. A method of manufacture of a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for SRAM, DRAM, and NVM devices.

Abstract: On a surface of a Si substrate, a nonvolatile memory cell, an nMOS transistor, and a pMOS transistor are formed, and thereafter an interlayer insulation film covering the nonvolatile memory cell, the nMOS transistor, and the pMOS transistor is formed. Next, in the interlayer insulation film, there are formed plural contact plugs connected respectively to a control gate of the nonvolatile memory cell, a source or a drain of the nMOS transistor, and a source or a drain of the pMOS transistor. Thereafter, there is formed a single-layer wiring connecting the control gate to the sources or drains of the nMOS transistor and the pMOS transistor via the plural contact plugs.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Various embodiments may include or exclude a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A method uses simplified processes to complete the forming of the trench DMOS transistors and Schottky contacts. In the processes, only four masks, i.e. a trench pattern mask, a contact-hole pattern mask, a P+ contact pattern mask and a conductive-wire pattern mask, are applied to create desired trench DMOS transistors. In addition to the trench DMOS transistors, a Schottky contact is simultaneously formed at a junction between a conductive layer and a doped body region in the trench DMOS transistors without additional photolithography process.

Abstract: A protection circuit protects a semiconductor device provided on a semiconductor substrate and including an interconnect from charge entering the interconnect during fabrication of the semiconductor device. The protection circuit includes a first metal interconnect connected to the interconnect; a forward diode and a backward diode connected in parallel to the interconnect; an NMIS whose drain is connected to the output port of the forward diode, whose source is connected to the semiconductor substrate and whose gate is grounded through an upper metal interconnect; a PMIS whose drain is connected to the input port of the backward diode and whose source is connected to the semiconductor substrate; a first antenna connected to the gate of the NMIS; and a second antenna connected to the gate of the PMIS.

Abstract: A method of forming an active device is provided. The method includes performing a first patterning operation on a first plurality of layers. This first patterning operation defines a first feature of the active device. Then, a second patterning operation can be performed on at least one layer of the first plurality of layers. This second patterning operation defines a second feature of the active device. Of importance, the first and second patterning operations are performed substantially back-to-back, thereby ensuring that the active device can accurately function.

Abstract: Apparatus and Methods for the self-alignment of separated regions in a lateral MOSFET of an integrate circuit. In one embodiment, a method comprising, forming a relatively thin dielectric layer on a surface of a substrate. Forming a first region of relatively thick material having a predetermined lateral length on the surface of the substrate adjacent the relatively thin dielectric layer. Implanting dopants to form a top gate using a first edge of the first region as a mask to define a first edge of the top gate. Implanting dopants to form a drain contact using a second edge of the first region as a mask to define a first edge of the drain contact, wherein the distance between the top gate and drain contact is defined by the lateral length of the first region.

Abstract: A semiconductor device formed in a semiconductor substrate for dissipating electrostatic discharge and/or accumulated charge in an integrated circuit is provided. In one embodiment, the device comprises a semiconductor substrate; a plurality of layers of metal lines formed overlying the substrate; a plurality of via plugs through intermetal dielectric layers between the layers of metal lines and wherein the via plugs interconnect the metal lines; and a dummy pad formed over the plurality of layers of metal lines, the dummy pad having a diode connected thereto and to ground for providing a discharge path for the electrostatic discharge and/or accumulated charge.

Abstract: A semiconductor device formed in a semiconductor substrate for dissipating electrostatic discharge and/or accumulated charge in an integrated circuit is provided. In one embodiment, the device comprises a semiconductor substrate; a plurality of layers of metal lines formed overlying the substrate; a plurality of via plugs through intermetal dielectric layers between the layers of metal lines and wherein the via plugs interconnect the metal lines; and a dummy pad formed over the plurality of layers of metal lines, the dummy pad having a diode connected thereto and to ground for providing a discharge path for the electrostatic discharge and/or accumulated charge.

Abstract: Disclosed herewith is a semiconductor device comprising a trench gate electrode and a zener diode, as well as a method for manufacturing the same. The trench gate electrode is formed in a semiconductor body and includes a first polycrystalline silicon layer doped with impurities of a first conductivity type at a first concentration. An extended gate electrode is elongated over the semiconductor body in contact with the trench gate electrode, and includes a second polycrystalline silicon layer doped with impurities of the first conductivity type at a second concentration that is lower than the first concentration. The zener diode is formed over the semiconductor body and includes a third polycrystalline silicon layer of a first conductivity type and a fourth polycrystalline silicon layer of a second conductivity type.

Abstract: An insulated gate semiconductor device, specifically, a trench lateral MOSFET having improved hot carrier resistance can be provided without increasing the number of processes and device pitch and without degrading device breakdown voltages and on-resistance characteristics RonA. A junction depth Xj of a p base region of a TLPM (trench lateral power MOSFET) is made smaller than the depth of a trench, and the trench is formed with a depth Dt of about 1.2 ?m such that the junction does not contact a curved corner part at the bottom of the trench.

Abstract: A technique for making a bulk isolated PN diode. Specifically, a technique is provided for making a voltage clamp with a pair of bulk isolated PN diode. Another embodiment provides for a voltage clamp with a pair of bulk isolated PN diodes in parallel with a pair of MOSFET diode-connected transistors. In addition, a method for manufacturing the bulk isolated PN diodes is recited.

Abstract: A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Various embodiments may include or exclude a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract: A semiconductor device has a semiconductor body (22) comprising an active area (7) and a termination structure (16) surrounding the active area. The termination structure comprises a plurality of lateral transistor devices (2a to 2d) connected in series and extending from the active area towards a peripheral edge (42) of the semiconductor body, with a zener diode (8) connected to the gate electrode (4) of one of the lateral devices for controlling its gate voltage, such that a voltage difference between the active area and the peripheral edge is distributed across the lateral devices and the zener diode. The termination structure (16) is capable of withstanding higher voltages in a compact manner and features thereof are susceptible to fabrication in the same process steps as features of the active area (7).

Abstract: In deep submicron memory arrays there is noted a relatively steady on current value and, therefore, threshold values of the transistors comprising the memory cell are reduced. This, in turn, results in an increase in the leakage current of the memory cell. With the use of an ever increasing number of memory cells leakage current must be controlled. A method and apparatus using a dynamic threshold voltage control scheme implemented with no more than minor changes to the existing MOS process technology is disclosed. The disclosed invention controls the threshold voltage of MOS transistors. Methods for enhancing the impact of the dynamic threshold control technology using this apparatus are also included. The invention is particularly useful for SRAM, DRAM, and NVM devices.

Abstract: There is provided a high-voltage-withstanding semiconductor device a fabrication method thereof capable of suppressing Vt fluctuation induced by plasma damage in a via hole forming step. In the high-voltage-withstanding semiconductor device, a gate electrode of a transistor having a gate insulating film formed on a semiconductor substrate and having a thickness of 350 ? or more and a diode composed of a first conductive well region formed in a surface layer region of the semiconductor substrate and a second conductive diffusion layer formed in the surface layer region of the semiconductor substrate and on the well region are electrically connected by a wire directly connected to contacts formed respectively on the gate electrode and the diode, via the contacts.

Abstract: An image sensor includes a semiconductor substrate, a photo receiving area in the semiconductor substrate, a gate electrode installed in a lateral side of the photo receiving area on the semiconductor substrate, and a patterned dielectric layer covering the gate electrode, the photo receiving area, and exposing a partial gate electrode. A spacer surrounds the gate electrode on the dielectric layer.

Abstract: A p-type collector region of an IGBT and an n-type cathode region of a free wheel diode are alternately formed in a second main surface of a semiconductor substrate. A back electrode is formed on the second main surface so as to be in contact with both of the p-type collector region and the n-type cathode region, and has a titanium layer, a nickel layer and a gold layer that are successively stacked from the side of the second main surface. A semiconductor device capable of obtaining a satisfactory ON voltage in any of conduction of an insulated gate field effect transistor and conduction of the free wheel diode as well as a manufacturing method thereof can thus be obtained.

Abstract: A method is provided for fabricating a semiconductor on insulator (SOI) device. The method includes, in one embodiment, providing a monocrystalline silicon substrate having a monocrystalline silicon layer overlying the substrate and separated therefrom by a dielectric layer. A gate electrode material is deposited and patterned to form a gate electrode and a spacer. Impurity determining dopant ions are implanted into the monocrystalline silicon layer using the gate electrode as an ion implant mask to form spaced apart source and drain regions in the monocrystalline silicon layer and into the monocrystalline silicon substrate using the spacer as an ion implant mask to form spaced apart device regions in the monocrystalline substrate. Electrical contacts are then formed that contact the spaced apart device regions.

Abstract: Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.

Abstract: An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

Abstract: A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.

Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.

Abstract: A fabrication process for a trench Schottky diode with differential oxide thickness within the trenches includes forming a first nitride layer on a substrate surface and subsequently forming a plurality of trenches in the substrate including, possibly, a termination trench. Following a sacrificial oxide layer formation and removal, sidewall and bottom surfaces of the trenches are oxidized. A second nitride layer is then applied to the substrate and etched such that the second nitride layer covers the oxide layer on the trench sidewalls but exposes the oxide layer on the trench bottom surfaces. The trench bottom surfaces are then re-oxidized and the remaining second nitride layer then removed from the sidewalls, resulting in an oxide layer of varying thickness being formed on the sidewall and bottom surfaces of each trench. The trenches are then filled with a P type polysilicon, the first nitride layer removed, and a Schottky barrier metal applied to the substrate surface.

Abstract: A silicon on insulator (SOI) device and methods for fabricating such a device are provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor.

Abstract: A semiconductor substrate is provided on which a plurality of shallow trench isolations (STI) defining a plurality of active areas are formed. The active areas comprise a photo sensing region, and a plurality of photodiodes are formed in each photo sensing region. Then a local oxidation of silicon isolation (LOCOS) layer is formed by performing a LOCOS process. Thereafter a plurality of gates are respectively formed in each active area, where the gates partially overlap the LOCOS layer. Finally doped regions are formed in the semiconductor substrate where the gate does not cover the LOCOS layer.

Abstract: A method is provided for forming patterned features using a conductive hard mask, where the conductive hard mask protects those features during a subsequent trench etch to form Damascene conductors providing electrical connection to those features from above. The thickness of the hard mask provides a margin to avoid overetch during the trench etch which may be harmful to device performance. The method is advantageously used in formation of a monolithic three dimensional memory array.

Abstract: A method for producing an integrated PIN photodiode. The PIN photodiode contains a doped region of a first conduction type near the substrate and a doped region that is remote from the substrate. The doped region that is remote from the substrate has a different construction type than the region near the substrate. In addition, an intermediate region provided that is a range between the doped region remote from the substrate and the doped region near the substrate. The intermediate region is undoped or provided with weak doping.

Abstract: An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor/capacitor biasing circuit and a second diode triggering biasing circuit.

Abstract: A method for forming a protective structure of active matrix triode field emission device is provided. The method comprises the steps of forming a silicon active region; depositing a gate oxide layer over the silicon active region; depositing and patterning a first metal layer over the gate oxide layer; doping impurities into portions of the said silicon active region to form a source/drain in a first conductive type and simultaneously to form a diode having a terminal in the first conductive type; forming ILD layer over the first metal layer and forming a plurality of contact holes thereon; depositing and patterning a second metal layer; forming a passivation layer over the second metal layer and forming a plurality of via holes thereon, depositing and patterning a third metal layer to form a gate and a tip structure.

Abstract: A CMOS imager with two adjacent pixel active area regions without the presence of an intervening trench isolation region that typically separates two adjacent pixels and their associated photodiodes is provided. The shared active area region isolates the two adjacent photodiodes and provides good substrate to surface pinned layer contact without the presence of n? type dopant ions and due to the presence of p-type dopant ions. As a result, the size of the imager can be reduced and the photodiodes of the two adjacent pixels have increased capacitance.

Abstract: Disclosed is a semiconductor device in which the capacitive element of MIMC structure has a low parasitic capacity. A process for fabrication of said semiconductor device. The semiconductor device has a capacitive element of MIMC structure, a PN photodiode, and a vertical NPN bipolar transistor which are mounted together on the same semiconductor substrate. The lower wiring layer connected to the TiN lower electrode layer of the capacitive element of MIMC structure is formed on the insulating film and the first interlayer insulating film. Between this insulating film and the p-type semiconductor substrate is the p?-type low-concentration semiconductor layer whose impurity concentration is lower than that of the p-type semiconductor substrate. This construction suppresses the parasitic capacity of the capacitive element of the MIMC structure.

Abstract: In one embodiment, a diode is formed with anodes on two surfaces of a semiconductor substrate.

Abstract: A high-density Germanium (Ge)-on-Insulator (GOI) photodiode array and corresponding fabrication method are provided. The method includes: forming an array of pixel driver nMOST devices, each device having a gate connected to a row line in a first orientation, a first source/drain (S/D) region, and a second S/D region connected to Vdd; forming a P-I-N Ge diode for each pixel as follows: forming a n+ region; forming an intrinsic Ge region overlying the n+ region; forming a p+ junction in the intrinsic Ge; and, isolating the P-I-N Ge diodes; and, forming an Indium Tin oxide (ITO) column in a second orientation, about orthogonal to the first orientation, overlying the P-I-N Ge diodes.

Abstract: A device of forming a film from an organic compound material at low cost is provided, using an organic compound material having high light emission efficiency. An organic compound film is formed on a substrate under an inert gas atmosphere by spraying of a colloid solution in which organic compound aggregates are dispersed (this solution is also referred to as a “sol”). Note that the organic compound may be one in which particles are composed of aggregates of several organic compounds within a liquid, and may be one in which a portion of the organic compound is dissolved within a liquid.