Abstract: A flash memory array having improved core field isolation in select gate regions via shallow trench isolation and field isolation implant after liner oxidation is disclosed. The flash memory array includes a core area and a periphery area, wherein the core area further includes a select gate region. The method of fabricating the flash memory array begins by patterning a layer of nitride over a substrate in active device locations. After the nitride is patterned, a silicon trench etch is performed to form trenches. After forming the trenches, a layer of liner oxide is grown in the trenches. Then, a field implant is performed in both the core area and periphery area to provide field isolation regions for the flash memory array with. Thereafter, poly1 is patterned in the core area to form floating gate and select word-lines.

Abstract: In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.

Abstract: In a semiconductor device and a method of manufacturing the same according to the present invention, a trade-off relationship between threshold values and a diffusion layer leakage is eliminated and it is not necessary to form gate oxide films at more than one stages. Since doses of nitrogen are different from each other between gate electrodes (4A to 4C) of N-channel type MOS transistors (T41 to T43), concentrations of nitrogen in the nitrogen-introduced regions (N1 to N3) are accordingly different from each other. Concentrations of nitrogen in the gate electrodes are progressively lower in the order of expected higher threshold values.

Abstract: The manufacturing method of the invention is applied to production of a semiconductor device including a memory area and a logic circuit area. The method first provides a semiconductor substrate, which has a conductive layer to make a word gate of the non-volatile memory device, a stopper layer formed above the conductive layer, and control gates formed as side walls on both side faces of the conductive layer via an ONO membrane, which are all located above a semiconductor layer in the memory area, as well as a gate electrode of an insulated gate field effect transistor formed above a semiconductor layer in the logic circuit area. The method subsequently forms an insulating layer over whole surface of the memory area and the logic circuit area on the semiconductor substrate, and carries out anisotropic etching of an upper portion in a part of the insulating layer.

Abstract: Semiconductor devices with a multiple isolation structure and methods for fabricating the same are provided. In one aspect, a semiconductor device comprises a heavily doped buried layer having a first conductivity type, which is formed in a predetermined region of a semiconductor substrate, and an epitaxial layer having the first conductivity type, which covers an entire surface of the semiconductor substrate. A device isolation structure is disposed such that the device isolation structure penetrates the epitaxial layer and a portion of the semiconductor substrate to define a device region. The device isolation structure includes an upper isolation structure penetrating an epitaxial layer as well as a lower isolation structure formed in the semiconductor substrate under the upper isolation structure.

Abstract: A method of manufacturing a semiconductor device includes the steps of: forming first and second active areas at a main surface of a silicon substrate; forming a first thermal oxide film on the main surface of the silicon substrate; selectively removing a prescribed portion of the first thermal oxide film to expose the second active area; forming a second thermal oxide film on the first and second active areas; performing an annealing process on the first and second thermal oxide films at or above a temperature for forming the second thermal oxide film; and forming first and second gate electrodes on the first and second active areas such that the first and second thermal oxide films undergoing the annealing process lie between them. Consequently, a method of manufacturing a semiconductor device wherein residual stress inside a semiconductor substrate is reduced is provided.

Abstract: A fabrication method for a non-volatile memory includes providing a first metal oxide semiconductor (MOS) transistor having a control gate and a second MOS transistor having a source, a drain, and a floating gate. The first MOS transistor and the second MOS transistor are formed on a well. The method further includes biasing the first MOS with a first biasing voltage to actuate the first MOS transistor, biasing the second MOS transistor with a second biasing voltage to enable the second MOS transistor to generate a gate current, and adjusting capacitances between the floating gate of the second MOS transistor and the drain, the source, the control gate, and the well according to voltage difference between the floating gate of the second MOS transistor and the source of the second MOS transistor.

Abstract: Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo implants are conducted into the first type MOS transistors in less than all of the peripheral MOS transistors of the first type. In another embodiment, a plurality of n-type transistor devices are formed over a substrate and comprise memory array circuitry and peripheral circuitry. At least some of the individual peripheral circuitry n-type transistor devices are partially masked, and a halo implant is conducted for unmasked portions of the partially masked peripheral circuitry n-type transistor devices. In yet another embodiment, at least a portion of only one of the source and drain regions is masked, and at least a portion of the other of the source and drains regions is exposed for at least some of the peripheral circuitry n-type transistor devices.

Abstract: Disclosed is a semiconductor device comprising a first transistor and a second transistor formed on a semiconductor substrate, wherein a gate side wall of the second transistor has a thickness equal to that of a gate side wall of the first transistor, wherein each of the first and second transistors has an inner low impurity diffusion region and an outer high impurity diffusion region, and wherein the size of the inner low impurity diffusion region of the second transistor along the surface of the semiconductor substrate is larger than that of the inner low impurity diffusion region of the first transistor.

Abstract: The present invention includes a 6F2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first access transistor is coupled to the first data storage capacitor via a first storage node formed on the substrate. The memory array also includes a second memory cell. The second memory cell includes a second access transistor and a second data storage capacitor. A first load electrode of the second access transistor is coupled to the second data storage capacitor via a second storage node formed on the substrate. The first and second access transistors have a gate dielectric having a first thickness. The memory array further includes an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween.

Abstract: A manufacturing method of an integrated chip. The integrated chip includes at least two devices with different functions. The method uses a first production line to form a first device on a semiconductor wafer and then uses a second production line to form a second device on the semiconductor wafer so as to complete the integrated chip.

Abstract: The object of the present invention is directed to shorten a manufacturing TAT when changing a stored data of a mask ROM incorporated into a semiconductor integrated circuit device with multi-layered structure, and to improve a manufacturing yield. For example, when the semiconductor integrated circuit device comprising an interconnection layer with five layers are manufactured, when fabricating samples or prototypes where data to be written to the mask ROM is frequently changed, the manufacturing TAT is shortened by means of configuring a bit line as a fifth layer of metal interconnection layer of an uppermost layer, and an interlayer dielectric (ILD) layer just below it as a forming layer of a via hole for use in data writing.

Abstract: An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.

Abstract: Methods are disclosed for fabricating dual bit SONOS flash memory cells, comprising forming polysilicon gate structures over an ONO layer, and doping source/drain regions of the substrate using the gate structures as an implant mask. Methods are also disclosed in which dielectric material is formed over and between the gate structures, and the wafer is planarized using an STI CMP process to remove dielectric material over the polysilicon gate structures.

Abstract: A semiconductor device according to the present invention includes a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of a plurality of rows and columns. Each of the nonvolatile memory devices includes a word gate formed over a semiconductor layer with a gate insulating layer interposed in between, impurity layers formed in the semiconductor layer, and sidewall-shaped control gates formed along both side surfaces of the word gate. The control gate includes a first control gate and a second control gate which are adjacent to each other. The first control gate is formed on a first insulating layer formed of a first silicon oxide film, a silicon nitride film, and a second silicon oxide film. The second control gate is formed on a second insulating layer formed of a silicon oxide film.

Abstract: High voltage (HV), single polysilicon gate NMOS and PMOS transistors in double polysilicon stacked gate flash technology and methods for making the same are described. Specifically, the methods provide for the formation of (and devices comprise) high voltage polysilicon 1 and polysilicon 2 transistors (NMOS and PMOS) in double polysilicon stacked gate flash technology. Different types of transistors (e.g., HV P1 NMOS, HV P1 PMOS, HV P2 NMOS, HV P2 PMOS, LV P1 NMOS, LV P1 PMOS, LV P2 NMOS, LV P2 PMOS) are formed along with a stacked-gate double-poly transistor, thereby providing versatility in flash technology device design. The polysilicon 1 transistors may be salicided without adding to the complexity of the double poly stacked gate fabrication process. In addition, the stacked gate device may include polysilicon 2 only transistors.

Abstract: NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

Abstract: In a nonvolatile memory, substrate isolation regions (220) are formed in a semiconductor substrate (120). The substrate isolation regions are dielectric regions protruding above the substrate. Then select gate lines (140) are formed. Then a floating gate layer (160) is deposited. The floating gate layer is etched until the substrate isolation regions are exposed and the floating layer is removed from over at least a portion of the select gate lines. A dielectric (1510) is formed over the floating gate layer, and a control gate layer (170) is deposited. The control gate layer protrudes upward over each select gate line. These protrusions are exploited to define the control gates independently of photolithographic alignment. The floating gates are then defined independently of any photolithographic alignment other than the alignment involved in patterning the substrate isolation regions and the select gate lines. In another aspect, a nonvolatile memory cell has a conductive floating gate (160).

Abstract: To fabricate a nonvolatile memory, a select gate (140) is formed over a semiconductor substrate. A dielectric (810, 1010, 1030) is formed over the select gate. A floating gate layer (160), e.g. doped polysilicon, is formed over the select gate. The floating gate layer is removed from over at least a portion of the select gate. A dielectric (1510), e.g., ONO, is formed over the floating gate layer, and a control gate layer (170) is formed over this dielectric. The control gate layer has an upward protrusion over the select gate. Then another layer (1710), e.g. silicon nitride, is formed on the control gate layer, but the protrusions of the control gate layer are exposed. The exposed portion of the control gate layer is etched selectively until the control gate layer is removed from over at least a portion of the select gate. Then another layer (1910) is formed on the exposed portion of the control gate layer. This is thermally grown silicon dioxide in some embodiments. Then the silicon nitride is removed.

Abstract: A DRAM cell capacitor is described. Capacitor formation and cell isolation methods are integrated by using existing isolation trench sidewalls to form DRAM capacitors. A doped silicon substrate adjacent to the vertical sidewalls of the isolation trench provides one DRAM cell capacitor plate. The DRAM capacitor also contains a dielectric material that partially covers the interior vertical sidewalls of the isolation trench. A conductive layer covering the dielectric material on the vertical sidewalls of the isolation trench forms the second capacitor plate and completes the DRAM capacitor.

Abstract: An EEPROM device incorporates a partially encapsulated floating gate electrode in order to increase the capacitive coupling between the floating gate electrode and the control gate region of an EEPROM device. The floating gate electrode is partially encapsulated by a capacitor plate that is locally interconnected to the control gate region residing in a semiconductor substrate. The capacitor plate is electrically isolated from the floating gate electrode by a capacitor dielectric layer overlying the floating gate electrode. By partially encapsulating the floating gate electrode with a capacitor plate electrically connected to the control gate region, a high capacitance coupling is obtained between the floating gate electrode and the control gate region, while minimizing the substrate area necessary for fabrication of the capacitor portion of an EEPROM device.

Abstract: Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in a charge storage part. An oxide coating film is formed on the surface of the metal interconnection at the bonding pad part, and ultraviolet rays are irradiated onto the oxide coating film for erasing of charges from the floating gate.

Abstract: One aspect disclosed herein relates to a method for forming a programmable logic array. Various embodiments of the method include forming a first logic plane and a second logic plane, each including a plurality of logic cells interconnected to implement a logical function. Forming the logic cells includes forming a horizontal substrate with a source region, a drain region, and a depletion mode channel region separating the source and the drain regions, and further includes forming a number of vertical gates located above different portions of the depletion mode channel region. At least one vertical gate is separated from the depletion mode channel region by a first oxide thickness, and at least one of the vertical gates is separated from the depletion mode channel region by a second oxide thickness. Other aspects and embodiments are provided herein.

Abstract: A method for forming contacts on a semiconductor device is provided. The method includes steps of forming an opening on a gate contact area, depositing a dielectric layer on a bit-line contact area and the opening, coating a photoresist to etch the dielectric layer, removing the photoresist and finally forming a conductive layer on a bit-line contact opening and a gate contact opening.

Abstract: A method for manufacturing a flash memory comprises forming a first dielectric layer on a semiconductor substrate as a tunneling dielectric and forming a first conductive layer on the first dielectric layer. Next step is to pattern the first dielectric layer, the first conductive layer and the substrate to form a trench in the substrate. An isolation is refilled into the trench, a portion of isolation is removed to a surface of the first conductive layer. A portion of the first conductive layer is removed, thereby forming a cavity between adjacent isolation. A second conductive layer is formed along a surface of the cavity and the isolation, next, a portion of the second conductive layer is removed to a surface of the isolation. Subsequently, a second dielectric layer is formed on a surface of the floating gate, a third conductive layer is formed on the second dielectric layer as a control gate.

Abstract: Disclosed is a method of manufacturing a flash memory device. A sidewall oxidization process using a mixed gas of O2 and TCA is implemented to reinforce isolation of the floating gate, and prevent a phenomenon that the thickness of the sidewall of the oxide film included within the dielectric film is thickness and a phenomenon that the thickness of the sidewall of the tunnel oxide film is thickened.

Abstract: A method of fabricating a semiconductor device in accordance with the present invention relates to a method of fabricating a semiconductor device including a memory region and a logic circuit region having a peripheral circuit, the method including the steps of: patterning a predetermined region formed of a stopper layer and a first conductive layer within the memory region, without patterning the logic circuit region; forming control gates in the form of side walls over both side surfaces of the first conductive layer within at least the memory region, with an ONO film interposed in between; forming first side wall dielectric layers on upper portions of the control gates; forming a gate electrode for a MOS transistor by patterning the first conductive layer within the logic circuit region; and forming a second side wall dielectric layer over the gate electrode and the side surfaces of the control gates and the first side wall dielectric layers.

Abstract: The present invention includes devices and methods to form non-volatile memory cells and peripheral devices, with reduced damage to the electron trapping layer and, optionally, reduced thermal exposure during CMOS processing. Particular aspects of the present invention are described in the claims, specification and drawings.

Abstract: A semiconductor chip having a plurality of flash memory devices, shallow trench isolation in the periphery region, and LOCOS isolation in the core region. A hard mask is used first to create the shallow trench isolation. The LOCOS isolation is then created. Subsequent etching is used to remove stringers. The flash memory is able to use shallow trench isolation to limit encroachment. The flash memory may also have a nitridated tunnel oxide barrier layer. A hard mask is used to prevent nitride contamination of the gate oxide layer. Periphery stacks have hate oxide layers of different thicknesses.

Abstract: A first polysilicon film, an ONO film, and a second polysilicon film are deposited on a substrate. After ions of an impurity have been implanted in the second polysilicon film, a silicon oxide is deposited on the substrate, followed by a heat treatment for activating the impurity. Patterning is thereafter performed on the silicon oxide film, the second polysilicon film, the ONO film and the first polysilicon film to from stack cell electrodes and an on-gate protective film. The on-gate protective film formed of a silicon oxide film is densified to have improved resistance to etching. Therefore the desired shape of the on-gate protective film is maintained. The film thickness of sidewalls on side surfaces of the stack cell electrodes is set with stability, so that the reduction in insulation withstand voltage between a contact and a control gate electrode is limited.

Abstract: A semiconductor device of which the process is simplified so that the manufacturing cost can be reduced and, at the same time, which has a semiconductor element that can control a current of high voltage is provided. The semiconductor device includes first and second semiconductor elements and the first semiconductor element includes a lower electrode formed above a substrate, an intermediate insulating film formed on the lower electrode and an upper electrode formed on the insulating film. The second semiconductor element includes a gate insulating film, which is formed on the substrate and which includes the same layer as that of the intermediate insulating film, and a gate electrode formed on the gate insulating film.

Abstract: A method is disclosed for fabricating an MDL (Merged DRAM Logic) semiconductor device, in which silicide is formed on a logic region and a memory region selectively for enhancing device reliability. The method includes the steps of (a) providing a substrate having a first region and a second region adjoining the first region, (b) forming a first gate forming material layer in the first region, (c) forming a second gate forming material layer in the first region having the first gate forming material layer formed therein and the second region, (d) selectively patterning the second gate forming material layer to form second gates in the second region and a boundary dummy pattern layer at a boundary area of the first and second regions, and (e) selectively patterning the first gate forming material layer to form first gates in the first region.

Abstract: Disclosed is a nonvolatile semiconductor memory device in which a disturbance phenomenon can be prevented. A nonvolatile semiconductor memory device has a semiconductor substrate, and a floating gate electrode formed on the semiconductor substrate via a gate insulating film. The floating gate electrode includes a lower conductive layer formed on the gate insulating film and having a first width W1 in a channel width direction, and an upper conductive layer formed on the lower conductive layer and having a second width W2 wider than the first width W1 in the channel width direction.

Abstract: Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the se

Abstract: A method of forming a semiconductor device including a memory cell area having a plurality of memory cells and a peripheral circuit area for reading and writing data on the memory cells in the memory cell area of a semiconductor substrate is provided. Contact pads are formed on source/drain regions of transistors in the peripheral circuit area as well as in the memory cell area. The contact pads are concurrently formed on the source/drain regions of the transistors in the memory cell area and the peripheral circuit area. As a result, there is no step difference between the contact pads and, thus, it is easy to form metal contact plugs on the contact pads.

Abstract: A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A first sub-line and space pattern in the first region comprises a space of a dimension (A) less than achievable by lithographic processes alone. Further, a second sub-line and space pattern in the second region comprises at least one line including a second critical dimension (B) achievable by lithography. The method uses two critical masking steps to form a hard mask that includes in the core region a critical dimension (A) less than achievable at a resolution limit of lithography. Further, the method uses a single etch step to transfer the pattern of the hard mask to the layer.

Abstract: The invention includes a method of making a programmable memory device. At least one floating gate layer is formed over a semiconductor substrate. A dielectric material is formed over the at least one floating gate layer, and a mass consisting essentially of W is formed over the dielectric material. The mass has a pair of opposing sidewalls. A first layer is formed over the mass and along the sidewalls of the mass, and a second layer is formed over the first layer. The second layer extends over the mass and along the sidewalls of the mass, and has a different composition than the first layer. After the second layer is formed, the first and second layers are anisotropically etched to form sidewall spacers extending along the sidewalls of the mass.

Abstract: A method of fabricating a non-volatile memory cell on a semiconductor substrate is disclosed. An area of a first region of the semiconductor substrate designated for a layer of floating polysilicon is blocked while a second region of the semiconductor substrate designated for a layer of non-floating polysilicon is exposed. Exposed regions of the semiconductor substrate are doped with charges.

Abstract: A method for fabricating a nonvolatile semiconductor memory device according to the present invention includes patterning an insulating film for forming a tunnel insulating film and a conductor film for forming a floating gate electrode and forming a well region of a first conductivity type in the logic circuit portion of a semiconductor substrate. This prevents the well region in the logic circuit portion from experiencing a thermal budget resulting from the formation of the insulating film and the conductor film.

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

Abstract: A process for manufacturing a byte selection transistor for a matrix of non volatile memory cells organised in rows and columns integrated on a semiconductor substrate, each memory cell comprising a floating gate transistor and a selection transistor, the process providing the following steps: defining on a same semiconductor substrate respective active areas for the byte selection transistor, for the floating gate transistor and for the selection transistor split by portions of insulating layer; depositing a multilayer structure comprising at least a gate oxide layer, a first polysilicon layer, a dielectric layer on the whole substrate and a second polysilicon layer, characterised in that it comprises the following steps: removing through a traditional photolithographic technique the multilayer structure to form at least a couple of two bands developing substantially in a parallel way to the columns of the matrix of memory cells, the first band being effective to define the gate regions of the byte selection

Abstract: A method of forming triple poly silicon split gate flash memory cell comprising of select gate, floating gate, and control gate having the three poly-silicon gates fully aligned with each other is described. High-resolution select-gate poly-silicon-1 is patterned using I-line lithography and resist instead of deep UV (DUV) lithography resist, as is normally used in prior art, which reduces cost of fabrication. Further, the triple poly-silicon structure is etched in a self-aligned manner and also provided with dielectric spacers in the source and drain contact regions prior to forming silicided metal contacts. Self-aligned etching in conjunction with dielectric spacers provide electrical isolation on the drain side and prevent potential bridging between select-gate poly silicon-1 and the drain.

Abstract: After a channel layer (7) containing nitrogen is formed in a channel region (5) in the main surface of a semiconductor substrate (1), a gate insulating film (9) and insulating films (10) are formed as oxide film by a thermal oxidation on the main surface of the semiconductor substrate (1). The insulating films (10) are thicker than the gate insulating film (9) because the oxidation reaction is suppressed in the nitrogen-introduced region. Further, stresses caused by the oxidation are suppressed-around the connections between the gate insulating film (9) and the insulating films (10). Accordingly, reduction in leakage current and improvement of gate insulating film reliability are compatibly realized.

Abstract: Provided are a method of manufacturing a semiconductor, a nonvolatile semiconductor memory device and a method of manufacturing the same, wherein: the memory device has a plurality of memory cells; a buried diffusion layer serves as a signal line; and, a buried diffusion layer disposed adjacent to each of opposite end portions of a lower floating gate is free from variations in width resulted from misalignment occurring in an optical aligner. In the memory device, for example: the floating gate is formed in an active region of a P-type semiconductor substrate through a gate oxide film; an N-type drain region and an N-type source region are formed in opposite end portions of the floating gate; and, a pair of device isolation shielding electrode extends in parallel with the floating gate outside both the drain region and the source region to cover adjacent ones of the memory cells.

Abstract: Disclosed are devices and associated methods for manufacturing an EEPROM memory cell (10) for use on a negatively biased substrate (12). The invention may be practiced using standard semiconductor processing techniques. Devices and methods are disclosed for a floating gate transistor for use as an EEPROM cell (10) including a DNwell (14) formed on a P-type substrate (12) for isolating the EEPROM cell (10) from the underlying P-type substrate (12).

Abstract: A method of fabricating flash memory is provided. A substrate divided into a memory cell region and a peripheral circuit region is provided. After forming a first conductive layer over the substrate, the first conductive layer in the memory cell region is patterned to form a first gate conductive layer. Thereafter, a gate dielectric layer is formed over the substrate and then a second conductive layer and a passivation layer are sequentially formed over the gate dielectric layer. After removing the passivation layer, the second conductive layer and the first conductive layer in the peripheral circuit region, a third conductive layer is formed over the substrate. The third conductive layer and the passivation layer in the memory cell region are removed. The second conductive layer, the gate dielectric layer and the first gate conductive layer in the memory cell region are patterned to form a plurality of memory gates.

Abstract: The present invention relates to a method of manufacturing a flash memory device. In the method, a low-voltage transistor is formed to have a DDD structure same to a high-voltage transistor when a peripheral region is formed in the manufacture process of the flash memory device. As the process for forming the LDD structure for the low voltage is omitted, the cost is reduced in the entire process of manufacturing the flash memory device.

Abstract: A method of forming an array of FLASH field effect transistors and circuitry peripheral to such array includes forming a sacrificial oxide over an array area and a periphery area of a semiconductor substrate. After forming the sacrificial oxide, at least one conductivity modifying implant is conducted into semiconductive material of the substrate within the array without conducting the one conductivity modifying implant into semiconductive material of the substrate within the periphery. The sacrificial oxide is removed from the array while the sacrificial oxide is left over the periphery. After removing the sacrificial oxide from the array, at least some FLASH transistor gates are formed within the array and at least some non-FLASH transistor gates are formed within the periphery.

Abstract: In this invention, by offering specific array-end structures and their fabrication method, the three resistive layers of diffusion bit line, control gate and word gate polysilicons, where control gate polysilicon can run on top of the diffusion bit line, are most effectively stitched with only three layers of metal lines keeping minimum metal pitches. The stitching method can also incorporate a bit diffusion select transistor and/or a control gate line select transistor. The purpose of the select transistors may be to reduce the overall capacitance of the bit line or control gate line, or to limit the disturb conditions that a grouped sub-array of cells may be subjected to during program and/or erase.

Abstract: A semiconductor device includes a trench isolating elements, a memory cell transistor and a peripheral circuit Vcc transistor having a thermal oxide film of a first thickness, and a peripheral circuit Vpp transistor including a thermal oxide film and a thermal oxide film formed before trench formation, having a second thickness greater than the first thickness.