Including Forming Gate Electrode In Trench Or Recess In Substrate Patents (Class 438/259)
  • Patent number: 10450672
    Abstract: The object is to produce with good reproducibility an epitaxial silicon carbide wafer having a high quality silicon carbide single crystal thin film with little step bunching. To achieve this object, for etching the silicon carbide single crystal substrate in the epitaxial growth furnace, hydrogen carrier gas and silicon-based material gas are used. After the etching treatment is finished as well, the epitaxial growth conditions are changed in the state in the state supplying these gases. When the conditions stabilize, a carbon-based material gas is introduced for epitaxial growth.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: October 22, 2019
    Assignee: SHOWA DENKO K.K.
    Inventors: Takashi Aigo, Wataru Ito, Tatsuo Fujimoto
  • Patent number: 10186600
    Abstract: A method for fabricating an electronic device is provided to include: forming a hard mask pattern over a substrate to expose a gate formation region; forming a gate trench by etching the substrate using the hard mask pattern; forming a gate insulating layer over an inner wall of the gate trench; forming a gate electrode filling a lower portion of the gate trench in which the gate insulating layer is formed; forming an insulating material covering a resultant structure in which the gate electrode is formed; forming a gate protective layer having a top surface lower than a bottom surface of the hard mask pattern; removing the hard mask pattern; recessing the substrate so that a top surface of the substrate is lower than the top surface of the gate protective layer; and forming a conductive pattern filling a space formed by the recessing of the substrate.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: January 22, 2019
    Assignee: SK hynix Inc.
    Inventor: Sang-Soo Kim
  • Patent number: 9947791
    Abstract: A semiconductor device comprises an insulation layer, an active semiconductor layer formed on an upper surface of the insulation layer, and a plurality of fins formed on the insulation layer. The fins are formed in the gate and spacer regions between a first source/drain region and second source/drain region, without extending into the first and second source/drain regions.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: April 17, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hong He, Chiahsun Tseng, Junli Wang, Chun-chen Yeh, Yunpeg Yin
  • Patent number: 9887206
    Abstract: A non-volatile memory cell, and method of making, that includes a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: February 6, 2018
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Chien-Sheng Su, Jeng-Wei Yang, Man-Tang Wu, Chun-Ming Chen, Hieu Van Tran, Nhan Do
  • Patent number: 9876086
    Abstract: Embodiments of mechanisms for forming a memory device structure are provided. The memory device includes a first gate stack structure. The first gate stack structure includes a first dielectric layer over a semiconductor substrate. The first gate stack structure also includes a first floating gate over the first dielectric layer, and the first floating gate has a tip corner. The first gate stack structure further includes a second dielectric layer conformally covering an upper surface and sidewalls of the first floating gate. The second dielectric layer has a substantially uniform thickness. In addition, the first gate stack structure includes a first control gate over the second dielectric layer and partially over the first floating gate.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: January 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Hsing-Chih Lin
  • Patent number: 9722071
    Abstract: A trench power transistor is provided. The trench gate structure of the trench power transistor includes at least one insulting layer, a gate electrode, and a shielding electrode, which are disposed in a trench of an epitaxial layer. The insulating layer formed on an inner wall of the active trench to isolate an epitaxial layer from the gate and the shielding electrodes. The insulating layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer. The first and second dielectric layers extend from an upper portion of the inner wall to a lower portion of the inner wall of the active trench. The third dielectric layer is formed on the second dielectric layer and located at the lower portion of the active trench. A portion of the second dielectric layer is interposed between the first and third dielectric layers.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: August 1, 2017
    Assignee: SINOPOWER SEMICONDUCTOR, INC.
    Inventors: Po-Hsien Li, Guo-Liang Yang, Jia-Fu Lin, Wei-Chieh Lin
  • Patent number: 9673289
    Abstract: A power MOSFET device including a semiconductor layer, an active trench formed in the semiconductor layer and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the active trench by a liner oxide layer having a first thickness, and a termination trench formed in the semiconductor layer apart from the active trench and housing a dual oxide thickness trench gate structure where a bottom of the trench gate is isolated from a bottom of the termination trench by the liner oxide layer having a second thickness. In one embodiment, the second thickness is greater than the first thickness. In another embodiment, the trench gate in each of the active trench and the termination trench is formed as a single polysilicon layer.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: June 6, 2017
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Daniel Calafut, Madhur Bobde, Yeeheng Lee, Hong Chang
  • Patent number: 9673328
    Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
  • Patent number: 9633858
    Abstract: A method for forming a semiconductor device includes forming first and second hard mask layers overlying a semiconductor substrate and forming trenches through the second hard mask, the first hard mask, and into the substrate. A dielectric material is formed in the trenches to form shallow trench isolation regions, removing the second hard mask layer, and a floating gate material is formed overlying the first hard mask and the trenches. The method further includes repeating at least twice a process of forming a buffer layer over the floating gate material and using a polishing process to remove a portion of the buffer layer and a top portion of the floating gate material. Next, a dry etch process to remove a portion of the floating gate material above the shallow trench isolation regions and the remaining portions of the buffer layer to form floating gate structures.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: April 25, 2017
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Xinpeng Wang
  • Patent number: 9608071
    Abstract: An IGBT manufacturing method is provided. The IGBT has an n-type emitter region, a p-type top body region, an n-type intermediate region, a p-type bottom body region, an n-type drift region, a p-type collector region, trenches penetrating the emitter region, the top body region, the intermediate region and the bottom body region from an upper surface of a semiconductor substrate and reaching the drift region, and gate electrodes formed in the trenches. The method includes forming the trenches on the upper surface of the semiconductor substrate, forming the insulating film in the trenches, forming an electrode layer on the semiconductor substrate and in the trenches after forming the insulating film, planarizing an upper surface of the electrode layer, and implanting n-type impurities to a depth of the intermediate region from the upper surface side of the semiconductor substrate after planarizing the upper surface of the electrode layer.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: March 28, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Takehiro Kato, Toru Onishi
  • Patent number: 9559057
    Abstract: According to one embodiment, a semiconductor device comprises a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a gate interconnect, a second insulating layer, and a first electrode. The first semiconductor region includes a first region and a second region provided around the first region. The gate interconnect is provided on the second region. The gate interconnect includes a first portion and a second portion provided around the second portion. A thickness in the first direction of the second portion is thinner than a thickness in the first direction of the first portion. A length in the second direction of the gate interconnect is longer than a length in the third direction of the gate electrode. The first electrode contacts the gate interconnect.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: January 31, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuya Nishiwaki, Masatoshi Arai, Hiroaki Katou, Hiroaki Katsuda, Chikako Yoshioka, Rieko Matoba
  • Patent number: 9502582
    Abstract: A non-volatile memory unit includes a substrate, a first dielectric layer, an erase gate, a floating gate, a second dielectric layer, a coupled dielectric layer and a couple control gate. The substrate has a source region and a drain region, and the first dielectric layer is formed on the substrate. The erase gate, the floating gate, the second dielectric layer and the selective gate are formed on the first dielectric layer. The second dielectric layer and coupled dielectric layer are formed among and above the erase gate, the floating gate and the selective gate, and the couple control gate is formed on the coupled dielectric layer.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: November 22, 2016
    Assignee: XINNOVA TECHNOLOGY LIMITED
    Inventors: Der-Tsyr Fan, Chih-Ming Chen, Jung-Chang Lu
  • Patent number: 9412665
    Abstract: A semiconductor device and a method for manufacturing the same are capable of improving GIDL in a buried gate, and preventing degradation of device characteristics and reliability due to reduction in gate resistance. The semiconductor device may include: junction regions formed at both sidewalls of a trench formed in a semiconductor substrate; a first gate electrode formed in a lower portion of the trench; a second gate electrode formed on at least one inner sidewall of the trench which overlaps one of the junction regions on the first gate electrode; and a third gate electrode formed on one side of the second gate electrode on the first gate electrode.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: August 9, 2016
    Assignee: SK HYNIX INC.
    Inventor: Sung Soo Kim
  • Patent number: 9406795
    Abstract: A trench gate MOSFET is provided. An epitaxial layer is disposed on a substrate. A body layer is disposed in the epitaxial layer. The epitaxial layer has a first trench therein, the body layer has a second trench therein, and the first trench is disposed below the second trench. A first insulating layer is disposed on a surface of the first trench. A second insulating layer is disposed in the first trench. A first conductive layer is disposed between the first and second insulating layers. A second conductive layer is disposed in the second trench. A third insulating layer is disposed between the second conductive layer and the body layer and between the second conductive layer and the first conductive layer. A dielectric layer is disposed on the epitaxial layer and covers the second conductive layer. Two doped regions are disposed in the body layer respectively beside the second trench.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: August 2, 2016
    Assignee: UBIQ Semiconductor Corp.
    Inventors: Chien-Ling Chan, Chi-Hsiang Lee
  • Patent number: 9312351
    Abstract: Provided is a floating gate flash cell and method for forming the same. The flash includes two floating gate transistors and a common source area therebetween. Each floating gate transistor includes a floating gate having a central portion disposed over a substrate surface and opposed lateral edges that extend into trenches and below the substrate surface. A control gate is disposed over said floating gate with a control gate dielectric between the floating gate and the control gate. The floating gates have side edges that are orthogonal to the opposed lateral edges and a common source area which is a substrate diffusion area, is positioned between respective facing side edges of the floating gates.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: April 12, 2016
    Assignee: WAFERTECH, LLC
    Inventor: Yimin Wang
  • Patent number: 9287300
    Abstract: The present inventive concepts provide methods for fabricating semiconductor devices. The method may comprise providing a substrate, stacking a conductive layer and a lower mask layer on the substrate, forming a plurality of hardmask layers each having an island shape on the lower mask layer, forming a plurality of upper mask patterns having island shapes arranged to expose portions of the lower mask layer, etching the exposed portions of the lower mask layer to expose portions of the conductive layer, and etching the exposed portions of the conductive layer to form a plurality of contact holes each exposing a portion of the substrate.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: March 15, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eunjung Kim, Yong Kwan Kim, Jemin Park, Semyeong Jang, Sangyeon Han, Yoosang Hwang
  • Patent number: 9281202
    Abstract: A nonvolatile memory cell and a method for fabricating the same can secure stable operational reliability as well as reducing a cell size. The nonvolatile memory cell includes a drain region formed in a substrate, a source region formed in the substrate to be separated from the drain region, a floating gate formed over the substrate between the drain region and the source region, a halo region formed in the substrate in a direction that the drain region is formed, a dielectric layer formed on sidewalls of the floating gate, and a control gate formed over the dielectric layer to overlap with at least one sidewall of the floating gate.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: March 8, 2016
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Tae-Ho Choi, Jung-Hwan Lee, Heung-Gee Hong, Jeong-Ho Cho, Min-Wan Choo, Il-Seok Han
  • Patent number: 9269709
    Abstract: A MOS transistor structure comprises a substrate including a bulk semiconductor region, a first gate formed in a first trench, a first drain/source region, a second drain/source region, wherein the first drain/source region and the second drain/source region are formed on opposing sides of the first gate. The MOS transistor structure further comprises a second gate formed in a second trench, a third drain/source region, wherein the third drain/source region and the second drain/source region are formed on opposing sides of the second gate and a channel region formed in the bulk semiconductor region, wherein the channel region, the first drain/source region, the second drain/source region and the third drain source region share a same polarity.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: February 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Po-Yu Chen
  • Patent number: 9257363
    Abstract: A base plate has a mounting surface on which a semiconductor element is mounted and a heat-radiation surface for radiating heat to a cooler. The cover has a portion that seals the semiconductor element on the mounting surface of the base plate. The cover has a projecting portion arranged outside the heat-radiation surface and projecting from a level of the heat-radiation surface in a thickness direction. The intermediate layer is arranged on the heat-radiation surface of the base plate, projects from the level of the projecting portion of the cover in a thickness direction, and is made of a thermoplastic material in a solid-phase state.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: February 9, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenta Nakahara, Hiroshi Yoshida
  • Patent number: 9230802
    Abstract: Field-effect transistors (FETs) and methods of fabricating field-effect transistors are provided, with one or both of a source cavity or a drain cavity having different channel junction characteristics. The methods include, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of the transistor, the recessing defining a bottom channel interface surface and a sidewall channel interface surface within the cavity; providing a protective liner over the sidewall channel interface surface, with the bottom channel interface surface being exposed within the cavity; processing the bottom channel interface surface to facilitate forming a first channel junction of the transistor; and removing the protective liner from over the sidewall channel interface surface, and subsequently processing the sidewall channel interface surface to form a second channel junction of the transistor, where the first and second channel junctions have different channel junction characteristics.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: January 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Neeraj Tripathi, Christopher Michael Prindle
  • Patent number: 9190473
    Abstract: A method for forming semiconductor contacts comprises forming a germanium fin structure over a silicon substrate, depositing a doped amorphous silicon layer over the first drain/source region and the second drain/source region at a first temperature, wherein the first temperature is lower than a melting point of the germanium fin structure and performing a solid phase epitaxial regrowth process on the amorphous silicon layer at a second temperature, wherein the second temperature is lower than the melting point of the germanium fin structure.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: November 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jean-Pierre Colinge
  • Patent number: 9184060
    Abstract: The embodiments herein relate to methods, apparatus, and systems for forming recessed features at high aspect ratios. Often, such features are formed in the context of fabricating a vertical NAND (VNAND) memory device. Various disclosed embodiments relate to process flows that involve depositing and shaping sacrificial posts on a metal seed layer that covers an underlying stack of materials, electroplating or electroless plating metal hard mask material around the sacrificial posts, removing the sacrificial posts, and etching the underlying stack of materials to form a high aspect ratio recessed feature.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: November 10, 2015
    Assignee: Lam Research Corporation
    Inventor: William T. Lee
  • Patent number: 9171854
    Abstract: A semiconductor device includes a substrate including an active region defined by a device isolation pattern and a floating gate on the active region. The floating gate includes an upper portion, a lower portion having a width greater than a width of the upper portion, and a step-difference portion between the upper portion and the lower portion. A dielectric pattern is on the floating gate, and a control gate is on the dielectric pattern. The lower portion of the floating gate has a height of about 4 nm or more.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: October 27, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: HyoJoong Kim, ByeongHoon Kim, In-Young Kim, Sang Bong Shin, Songha Oh
  • Patent number: 9159426
    Abstract: A method includes forming a first group of memory cells coupled to a first conductive channel. The first conductive channel is substantially perpendicular relative to a surface of a substrate. The method further includes forming a second group of memory cells coupled to a second conductive channel. The second conductive channel is electrically coupled to the first conductive channel and is substantially perpendicular relative to the surface of the substrate.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: October 13, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventor: Manuel Antonio D'Abreu
  • Patent number: 9159845
    Abstract: A charge-retaining transistor includes a control gate and an inter-gate dielectric alongside the control gate. A charge-storage node of the transistor includes first semiconductor material alongside the inter-gate dielectric. Islands of charge-trapping material are alongside the first semiconductor material. An oxidation-protective material is alongside the islands. Second semiconductor material is alongside the oxidation-protective material, and is of some different composition from that of the oxidation-protective material. Tunnel dielectric is alongside the charge-storage node. Channel material is alongside the tunnel dielectric. Additional embodiments, including methods, are disclosed.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: October 13, 2015
    Assignee: Micron Technology, Inc.
    Inventor: D. V. Nirmal Ramaswamy
  • Patent number: 9153705
    Abstract: A memory device includes a plurality of channels, a plurality of first charge storage sites coupled to first sides of respective ones of the channels, and a plurality of second charge storage sites coupled to second sides of respective ones of the channels. The first charge storage sites correspond to first memory cells and the second charge storage sites coupled to second memory cells. At least one of the channels is a dummy channel not connected to a bit line, and a blocking layer is contiguously formed around the first and second charge storage sites and the channels.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: October 6, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gang Zhang, Kyoung-Sub Shin
  • Patent number: 9147729
    Abstract: Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: September 29, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Deepak Pandey, Haitao Liu, Fawad Ahmed, Kamal M. Karda
  • Patent number: 9136379
    Abstract: A bottom source power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a gate electrode and a source electrode formed on an initial insulation layer on a first surface of a semiconductor chip and a drain electrode formed on a second surface of the semiconductor chip. The source electrode includes a source metal, a source electrode bump formed on the source metal and a source electrode metal layer on top of the source electrode bump. A first insulation layer covers the gate electrode. A through via aligned to the gate electrode is formed from the second surface of the chip to expose a portion of the gate electrode from the second surface.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: September 15, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yueh-Se Ho, Yan Xun Xue, Ping Huang
  • Patent number: 9136321
    Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a junction butting region using low energy ion implantation to reduce parasitic leakage and body-to-body leakage between adjacent FETs that share a common contact in high density memory technologies, such as dynamic random access memory (DRAM) devices and embedded DRAM (eDRAM) devices. A method disclosed may include forming a junction butting region at the bottom of a trench formed in a semiconductor on insulator (SOI) layer using low energy ion implantation and protecting adjacent structures from damage from ion scattering using a protective layer.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: September 15, 2015
    Assignee: International Business Machines Corporation
    Inventors: Shreesh Narasimha, Katsunori Onishi, Paul C. Parries, Chengwen Pei, Geng Wang
  • Patent number: 9117836
    Abstract: A SiC MOSFET has a subject that resistance in the source region is increased when annealing for metal silicidation is performed to a source region before forming the gate insulating film, the metal silicide layer of the source region is oxidized by an oxidizing treatment (including oxynitriding treatment) when the gate insulating film is formed. When a metal silicide layer to be formed on the surface of a SiC epitaxial substrate is formed before forming a gate insulating film interface layer (oxide film), and an anti-oxidation film for the metal silicide is formed on the metal silicide layer, it is possible to suppress oxidation of the metal silicide layer by the oxidizing treatment upon forming the gate insulating film interface layer and the resistance of the source region can be decreased without lowering the channel mobility.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: August 25, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Tega, Yasuhiro Shimamoto, Yuki Mori, Hirotaka Hamamura, Hiroyuki Okino, Digh Hisamoto
  • Patent number: 9105632
    Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a plurality of first doped regions and second doped regions; and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a first gate dielectric layer and a second gate dielectric layer; and forming a first metal gate and a second metal gate on the first gate dielectric layer and the second gate dielectric layer, respectively. Further, the method includes forming a third dielectric layer on the second metal gate; and forming a second dielectric layer on the first dielectric layer. Further, the method also includes forming at least one opening exposing at least one first metal gate and one first doped region; and forming a contact layer contacting with the first metal gate and the first doped region to be used as a share contact structure.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: August 11, 2015
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORP
    Inventor: Zhongshan Hong
  • Patent number: 9082654
    Abstract: A semiconductor device of the present invention includes a semiconductor substrate, stripe-shaped trenches for separating the semiconductor substrate into a plurality of active regions, a buried film having a projecting portion that projects from the semiconductor substrate, buried into the trenches, a source region and drain region of a second conductivity type, which are a pair of regions formed in the active region, for providing a channel region of a first conductivity type for a region therebetween, and a floating gate consisting of a single layer striding across the source region and the drain region, projecting beyond the projecting portion in a manner not overlapping the projecting portion, in which an aspect ratio of the buried film is 2.3 to 3.67.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: July 14, 2015
    Assignee: ROHM CO., LTD.
    Inventors: Kunihiko Iwamoto, Bungo Tanaka, Michihiko Mifuji
  • Patent number: 9082848
    Abstract: A semiconductor device and a method for manufacturing the same are capable of improving GIDL in a buried gate, and preventing degradation of device characteristics and reliability due to reduction in gate resistance. The semiconductor device may include: junction regions formed at both sidewalls of a trench formed in a semiconductor substrate; a first gate electrode formed in a lower portion of the trench; a second gate electrode formed on at least one inner sidewall of the trench which overlaps one of the junction regions on the first gate electrode; and a third gate electrode formed on one side of the second gate electrode on the first gate electrode.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: July 14, 2015
    Assignee: SK HYNIX INC.
    Inventor: Sung Soo Kim
  • Patent number: 9076824
    Abstract: The disclosure is related to memory arrays and methods. One such memory array has a substantially vertical pillar. A memory cell adjacent to the pillar where the pillar has a first size has a greater channel length than a memory cell adjacent to the pillar where the pillar has a second size larger than the first size.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: July 7, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Koji Sakui, Peter Feeley
  • Patent number: 9041057
    Abstract: A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Shu-Jen Han, Chung-Hsun Lin
  • Patent number: 9034712
    Abstract: A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Renata Camillo-Castillo, Erik M. Dahlstrom, Robert J. Gauthier, Jr., Ephrem G. Gebreselasie, Richard A. Phelps, Jed H. Rankin, Yun Shi
  • Patent number: 9029215
    Abstract: In one embodiment, a method for forming a semiconductor device includes forming trench and a dielectric layer along surfaces of the trench. A shield electrode is formed in a lower portion of the trench and the dielectric layer is removed from upper sidewall surfaces of the trench. A gate dielectric layer is formed along the upper surfaces of the trench. Oxidation-resistant spacers are formed along the gate dielectric layer. Thereafter, an interpoly dielectric layer is formed above the shield electrode using localized oxidation. The oxidation step increases the thickness of lower portions of the gate dielectric layer. The oxidation-resistant spacers are removed before forming a gate electrode adjacent the gate dielectric layer.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: May 12, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Zia Hossain, Gordon M. Grivna, Duane B. Barber, Peter McGrath, Balaji Padmanabhan, Prasad Venkatraman
  • Patent number: 9029235
    Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.
    Type: Grant
    Filed: May 26, 2014
    Date of Patent: May 12, 2015
    Assignee: PFC Device Corp.
    Inventors: Mei-Ling Chen, Hung-Hsin Kuo, Kuo-Liang Chao
  • Patent number: 9029932
    Abstract: A programmable device and a method of manufacturing the same are provided. A programmable device comprises a substrate having a source region, a drain region and a diffusion region adjacent to the source region and the drain region; a channel coupling the source region and the drain region; a floating gate formed of a conductive material and positioned on the substrate and corresponding to the channel; and a trench formed in the diffusion region at the substrate, wherein the floating gate extends to the trench, and the conductive material covers a sidewall of the trench.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: May 12, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Ze-Wei Jhou, Ching-Chung Yang
  • Patent number: 9024377
    Abstract: A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate. The word line includes: a gate electrode, a gate dielectric layer disposed between the gate electrode and the substrate and at least one first charge trapping dielectric layer disposed adjacent to the gate electrode, wherein the first charge trapping dielectric layer comprises HfO2, TiO2, ZrO2, a germanium nanocrystal layer, an organic charge trapping material, HfSiOxNy, or MoSiOqNz.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: May 5, 2015
    Assignee: Nanya Technology Corp.
    Inventor: Shian-Jyh Lin
  • Patent number: 9006053
    Abstract: Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)<TBCD is created into side walls of TCT and beneath SCD. An embedded Shannon implant region (ESIR) is created into sub-contact trench zone (SCTZ) beneath TCT floor. A metal layer is formed in contact with ESIR, body and source region. The metal layer also fills TCT and covers dielectric region thus completing the MOSFET/SKY with only one-time etching of its TCT.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: April 14, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Ji Pan, Daniel Ng, Sung-Shan Tai, Anup Bhalla
  • Patent number: 8999769
    Abstract: A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having an upper and a lower portion is formed in a trench in the substrate in the device region. The upper portion forms a gate electrode and the lower portion forms a gate field plate. First and second surface doped regions are formed adjacent to the gate. The gate field plate introduces vertical reduced surface (RESURF) effect in a drift region of the device.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: April 7, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Purakh Raj Verma, Liang Yi, Yemin Dong
  • Patent number: 8999783
    Abstract: A method for producing a semiconductor device is disclosed. The method includes providing a semiconductor body having a first surface, and a second surface opposite the first surface, producing a first trench having a bottom and sidewalls and extending from the first surface into the semiconductor body, forming a dielectric layer along at least one sidewall of the trench, and filling the trench with a filling material. Forming the dielectric layer includes forming a protection layer on the least one sidewall such that the protection layer leaves a section of the at least one sidewall uncovered, oxidizing the semiconductor body in the region of the uncovered sidewall section to form a first section of the dielectric layer, removing the protection layer, and forming a second section of the dielectric layer on the at least one sidewall.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: April 7, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Franz Hirler, Andreas Meiser
  • Patent number: 8994101
    Abstract: A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: March 31, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hong Chang, Yi Su, Wenjun Li, Limin Weng, Jongoh Kim, John Chen
  • Patent number: 8993391
    Abstract: A method for fabricating a semiconductor device includes forming a conductive layer over first and second regions of a semiconductor substrate, forming a trench extended in the first region of the semiconductor substrate through the conductive layer, forming a recessed gate electrode in the trench, doping the conductive layer and the recessed first gate electrode, and forming a second gate electrode by etching the doped conductive layer.
    Type: Grant
    Filed: March 16, 2013
    Date of Patent: March 31, 2015
    Assignee: SK Hynix Inc.
    Inventor: Min-Chul Sung
  • Patent number: 8981384
    Abstract: There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes a substrate having a main surface, and a silicon carbide layer. The silicon carbide layer is formed on the main surface of the substrate. The silicon carbide layer includes a side surface as an end surface inclined relative to the main surface. The side surface substantially includes one of a {03-3-8} plane and a {01-1-4} plane in a case where the silicon carbide layer is of hexagonal crystal type, and substantially includes a {100} plane in a case where the silicon carbide layer is of cubic crystal type.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: March 17, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Takeyoshi Masuda
  • Patent number: 8980713
    Abstract: A method for fabricated a buried recessed access device comprising etching a plurality of gate trenches in a substrate, implanting and activating a source/drain region in the substrate, depositing a dummy gate in each of the plurality of gate trenches, filling the plurality of gate trenches with an oxide layer, removing each dummy gate and depositing a high-K dielectric in the plurality of gate trenches, depositing a metal gate on the high-K dielectric in each of the plurality of gate trenches, depositing a second oxide layer on the metal gate and forming a contact on the source/drain.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: March 17, 2015
    Assignee: Sony Corporation
    Inventors: Satoru Mayuzumi, Mark Fischer, Michael Violette
  • Publication number: 20150060980
    Abstract: A programmable device and a method of manufacturing the same are provided. A programmable device comprises a substrate having a source region, a drain region and a diffusion region adjacent to the source region and the drain region; a channel coupling the source region and the drain region; a floating gate formed of a conductive material and positioned on the substrate and corresponding to the channel; and a trench formed in the diffusion region at the substrate, wherein the floating gate extends to the trench, and the conductive material covers a sidewall of the trench.
    Type: Application
    Filed: August 27, 2013
    Publication date: March 5, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ze-Wei Jhou, Ching-Chung Yang
  • Patent number: 8969940
    Abstract: A process integration is disclosed for fabricating non-volatile memory (NVM) cells having patterned select gates (211, 213), charge storage layers (219), inlaid control gates (223, 224), and inlaid control gate contact regions (228).
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: March 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jane A Yater, Cheong Min Hong, Sung-Taeg Kang, Asanga H Perera
  • Patent number: 8969955
    Abstract: A device includes a trench extending into a semiconductor region and having a first conductivity type, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer and having an edge portion overlapping the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion contacting the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type. A MOS-containing device is at a surface of the semiconductor region.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu