Including Forming Gate Electrode In Trench Or Recess In Substrate Patents (Class 438/259)
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Patent number: 9029932Abstract: A programmable device and a method of manufacturing the same are provided. A programmable device comprises a substrate having a source region, a drain region and a diffusion region adjacent to the source region and the drain region; a channel coupling the source region and the drain region; a floating gate formed of a conductive material and positioned on the substrate and corresponding to the channel; and a trench formed in the diffusion region at the substrate, wherein the floating gate extends to the trench, and the conductive material covers a sidewall of the trench.Type: GrantFiled: August 27, 2013Date of Patent: May 12, 2015Assignee: United Microelectronics Corp.Inventors: Ze-Wei Jhou, Ching-Chung Yang
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Patent number: 9024377Abstract: A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate. The word line includes: a gate electrode, a gate dielectric layer disposed between the gate electrode and the substrate and at least one first charge trapping dielectric layer disposed adjacent to the gate electrode, wherein the first charge trapping dielectric layer comprises HfO2, TiO2, ZrO2, a germanium nanocrystal layer, an organic charge trapping material, HfSiOxNy, or MoSiOqNz.Type: GrantFiled: December 14, 2011Date of Patent: May 5, 2015Assignee: Nanya Technology Corp.Inventor: Shian-Jyh Lin
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Patent number: 9006053Abstract: Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)<TBCD is created into side walls of TCT and beneath SCD. An embedded Shannon implant region (ESIR) is created into sub-contact trench zone (SCTZ) beneath TCT floor. A metal layer is formed in contact with ESIR, body and source region. The metal layer also fills TCT and covers dielectric region thus completing the MOSFET/SKY with only one-time etching of its TCT.Type: GrantFiled: April 29, 2014Date of Patent: April 14, 2015Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Ji Pan, Daniel Ng, Sung-Shan Tai, Anup Bhalla
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Patent number: 8999783Abstract: A method for producing a semiconductor device is disclosed. The method includes providing a semiconductor body having a first surface, and a second surface opposite the first surface, producing a first trench having a bottom and sidewalls and extending from the first surface into the semiconductor body, forming a dielectric layer along at least one sidewall of the trench, and filling the trench with a filling material. Forming the dielectric layer includes forming a protection layer on the least one sidewall such that the protection layer leaves a section of the at least one sidewall uncovered, oxidizing the semiconductor body in the region of the uncovered sidewall section to form a first section of the dielectric layer, removing the protection layer, and forming a second section of the dielectric layer on the at least one sidewall.Type: GrantFiled: February 6, 2013Date of Patent: April 7, 2015Assignee: Infineon Technologies Austria AGInventors: Anton Mauder, Franz Hirler, Andreas Meiser
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Patent number: 8999769Abstract: A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having an upper and a lower portion is formed in a trench in the substrate in the device region. The upper portion forms a gate electrode and the lower portion forms a gate field plate. First and second surface doped regions are formed adjacent to the gate. The gate field plate introduces vertical reduced surface (RESURF) effect in a drift region of the device.Type: GrantFiled: July 18, 2012Date of Patent: April 7, 2015Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Purakh Raj Verma, Liang Yi, Yemin Dong
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Patent number: 8993391Abstract: A method for fabricating a semiconductor device includes forming a conductive layer over first and second regions of a semiconductor substrate, forming a trench extended in the first region of the semiconductor substrate through the conductive layer, forming a recessed gate electrode in the trench, doping the conductive layer and the recessed first gate electrode, and forming a second gate electrode by etching the doped conductive layer.Type: GrantFiled: March 16, 2013Date of Patent: March 31, 2015Assignee: SK Hynix Inc.Inventor: Min-Chul Sung
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Patent number: 8994101Abstract: A method for fabricating a semiconductor device includes forming a plurality of trenches using a first mask. The trenches include source pickup trenches located in outside a termination area and between two adjacent active areas. First and second conductive regions separated by an intermediate dielectric region are formed using a second mask. A first electrical contact to the first conductive region and a second electrical contact to the second conductive region are formed using a third mask and forming a source metal region. Contacts to a gate metal region are formed using a fourth mask. A semiconductor device includes a source pickup contact located outside a termination region and outside an active region of the device.Type: GrantFiled: April 18, 2013Date of Patent: March 31, 2015Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Hong Chang, Yi Su, Wenjun Li, Limin Weng, Jongoh Kim, John Chen
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Patent number: 8981384Abstract: There are provided a high-quality semiconductor device having stable characteristics and a method for manufacturing such a semiconductor device. The semiconductor device includes a substrate having a main surface, and a silicon carbide layer. The silicon carbide layer is formed on the main surface of the substrate. The silicon carbide layer includes a side surface as an end surface inclined relative to the main surface. The side surface substantially includes one of a {03-3-8} plane and a {01-1-4} plane in a case where the silicon carbide layer is of hexagonal crystal type, and substantially includes a {100} plane in a case where the silicon carbide layer is of cubic crystal type.Type: GrantFiled: July 14, 2011Date of Patent: March 17, 2015Assignee: Sumitomo Electric Industries, Ltd.Inventor: Takeyoshi Masuda
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Patent number: 8980713Abstract: A method for fabricated a buried recessed access device comprising etching a plurality of gate trenches in a substrate, implanting and activating a source/drain region in the substrate, depositing a dummy gate in each of the plurality of gate trenches, filling the plurality of gate trenches with an oxide layer, removing each dummy gate and depositing a high-K dielectric in the plurality of gate trenches, depositing a metal gate on the high-K dielectric in each of the plurality of gate trenches, depositing a second oxide layer on the metal gate and forming a contact on the source/drain.Type: GrantFiled: May 31, 2013Date of Patent: March 17, 2015Assignee: Sony CorporationInventors: Satoru Mayuzumi, Mark Fischer, Michael Violette
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Publication number: 20150060980Abstract: A programmable device and a method of manufacturing the same are provided. A programmable device comprises a substrate having a source region, a drain region and a diffusion region adjacent to the source region and the drain region; a channel coupling the source region and the drain region; a floating gate formed of a conductive material and positioned on the substrate and corresponding to the channel; and a trench formed in the diffusion region at the substrate, wherein the floating gate extends to the trench, and the conductive material covers a sidewall of the trench.Type: ApplicationFiled: August 27, 2013Publication date: March 5, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ze-Wei Jhou, Ching-Chung Yang
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Patent number: 8969940Abstract: A process integration is disclosed for fabricating non-volatile memory (NVM) cells having patterned select gates (211, 213), charge storage layers (219), inlaid control gates (223, 224), and inlaid control gate contact regions (228).Type: GrantFiled: October 8, 2013Date of Patent: March 3, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Jane A Yater, Cheong Min Hong, Sung-Taeg Kang, Asanga H Perera
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Patent number: 8969955Abstract: A device includes a trench extending into a semiconductor region and having a first conductivity type, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer and having an edge portion overlapping the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion contacting the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type. A MOS-containing device is at a surface of the semiconductor region.Type: GrantFiled: September 13, 2012Date of Patent: March 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Po-Chih Su, Ruey-Hsin Liu
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Patent number: 8962455Abstract: A method of fabricating a semiconductor device includes forming a first preliminary gate barrier layer and a first preliminary gate electrode recessed to have a first depth from the surface of the substrate within a gate trench, removing an upper portion of the first preliminary gate electrode by means of a first wet etching process using a first etchant to form a second preliminary gate electrode recessed to have a second depth greater than the first depth, and removing an upper portion of the first preliminary gate barrier layer and an upper portion of the second preliminary gate electrode by means of a second wet etching process using a second etchant to form a gate electrode and a gate barrier layer recessed to a third depth greater than the second depth.Type: GrantFiled: June 18, 2013Date of Patent: February 24, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Hyun Choi, Jin-Ho Noh, Yoon-Ho Son, Dae-Hyuk Chung, In-Seak Hwang, Tae-Joon Park, Tae-Ho Hwang
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Publication number: 20150048447Abstract: A lateral diffusion metal oxide semiconductor (LDMOS) comprises a semiconductor substrate having an STI structure in a top surface of the substrate, a drift region below the STI structure, and a source region and a drain region on opposite sides of the STI structure. A gate conductor is on the substrate over a gap between the STI structure and the source region, and partially overlaps the drift region. Floating gate pieces are over the STI structure. A conformal dielectric layer is on the top surface and on the gate conductor and floating gate pieces and forms a mesa above the gate conductor and floating gate pieces. A conformal etch-stop layer is embedded within the conformal dielectric layer. A drift electrode is formed on the conformal etch-stop layer over, relative to the top surface, the drift region. The drift electrode has a variable thickness relative to the top surface.Type: ApplicationFiled: August 14, 2013Publication date: February 19, 2015Applicant: International Business Machines CorporationInventors: Santosh Sharma, Yun Shi, Anthony K. Stamper
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Patent number: 8955579Abstract: There is provided a means for uniformly controlling the in-plane temperature of a semiconductor wafer at high speed in a high heat input etching process. A refrigerant channel structure in a circular shape is formed in a sample stage. Due to a fact that a heat transfer coefficient of a refrigerant is largely changed from a refrigerant supply port to a refrigerant outlet port, the cross sections of the channel structure is structured so as to be increased from a first channel areas towards a second channel areas in order to make the heat transfer coefficient of the refrigerant constant in the refrigerant channel structure. Thereby, the heat transfer coefficient of the refrigerant is prevented from increasing by reducing the flow rate of the refrigerant at a dry degree area where the heat transfer coefficient of the refrigerant is increased.Type: GrantFiled: April 21, 2011Date of Patent: February 17, 2015Assignee: Hitachi High-Technologies CorporationInventors: Takumi Tandou, Kenetsu Yokogawa, Masaru Izawa
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Patent number: 8946021Abstract: On a silicon substrate is formed a stacked body by alternately stacking a plurality of silicon oxide films and silicon films, a trench is formed in the stacked body, an alumina film, a silicon nitride film and a silicon oxide film are formed in this order on an inner surface of the trench, and a channel silicon crystalline film is formed on the silicon oxide film. Next, a silicon oxide layer is formed at an interface between the silicon oxide film and the channel silicon crystalline film by performing thermal treatment in an oxygen gas atmosphere.Type: GrantFiled: August 15, 2014Date of Patent: February 3, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Yoshio Ozawa
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Patent number: 8946908Abstract: Disclosed is a semiconductor structure which includes a semiconductor substrate and a wiring layer on the semiconductor substrate. The wiring layer includes a plurality of fin-like structures comprising a first metal; a first layer of a second metal on each of the plurality of fin-like structures wherein the first metal is different from the second metal, the first layer of the second metal having a height less than each of the plurality of fin-like structures; and an interlayer dielectric (ILD) covering the plurality of fin-like structures and the first layer of the second metal except for exposed edges of the plurality of fin-like structures at predetermined locations, and at locations other than the predetermined locations, the height of the plurality of fin-like structures has been reduced so as to be covered by the ILD.Type: GrantFiled: August 7, 2013Date of Patent: February 3, 2015Assignee: International Business Machines CorporationInventors: Steven J. Holmes, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
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Patent number: 8940607Abstract: The present invention provides a manufacturing method of a trench type power transistor device with a super junction. First, a substrate of a first conductivity type is provided, and then an epitaxial layer of a second conductive type is formed on the substrate. Next, a through hole is formed in the epitaxial layer, and the through hole penetrates through the epitaxial layer. Two doped drain regions of the first conductivity type are then formed in the epitaxial layer respectively at two sides of the through hole, and the doped drain regions extend from a top surface of the epitaxial layer to be in contact with the substrate.Type: GrantFiled: December 16, 2013Date of Patent: January 27, 2015Assignee: Anpec Electronics CorporationInventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Chia-Hao Chang
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Patent number: 8940604Abstract: The disclosure relates to an integrated circuit comprising a nonvolatile memory on a semiconductor substrate. The integrated circuit comprises a doped isolation layer implanted in the depth of the substrate, isolated conductive trenches reaching the isolation layer and forming gates of selection transistors of memory cells, isolation trenches perpendicular to the conductive trenches and reaching the isolation layer, and conductive lines parallel to the conductive trenches, extending on the substrate and forming control gates of charge accumulation transistors of memory cells. The isolation trenches and the isolated conductive trenches delimit a plurality of mini wells in the substrate, the mini wells electrically isolated from each other, each having a floating electrical potential and comprising two memory cells.Type: GrantFiled: March 5, 2013Date of Patent: January 27, 2015Assignee: STMicroelectronics (Rousset) SASInventor: Francesco La Rosa
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Patent number: 8941090Abstract: A resistive memory device capable of implementing a multi-level cell, a method of fabricating the same, and a memory apparatus and data processing system including the same are provided. The resistive memory device includes a lower electrode, a first phase-change material layer formed over the lower electrode, a second phase-change material layer formed to surround an outer sidewall of the first phase-change material layer, and an upper electrode formed over the first phase-change material layer and the second phase-change material layer.Type: GrantFiled: December 19, 2012Date of Patent: January 27, 2015Assignee: SK Hynix Inc.Inventor: Sung Min Lee
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Patent number: 8932924Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.Type: GrantFiled: October 21, 2013Date of Patent: January 13, 2015Assignee: Fairchild Semiconductor CorporationInventors: Joseph A. Yedinak, Dean E. Probst, Daniel Calafut
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Patent number: 8927368Abstract: A trench having a side wall and a bottom portion is formed in a silicon carbide substrate. A trench insulating film is formed to cover the bottom portion and the side wall. A silicon film is formed to fill the trench with the trench insulating film being interposed therebetween. The silicon film is etched so as to leave a portion of the silicon film that is disposed on the bottom portion with the trench insulating film being interposed therebetween. The trench insulating film is removed from the side wall. By oxidizing the silicon film, a bottom insulating film is formed. A side wall insulating film is formed on the side wall.Type: GrantFiled: August 2, 2013Date of Patent: January 6, 2015Assignee: Sumitomo Electric Industries, Ltd.Inventors: Yu Saitoh, Takeyoshi Masuda, Hideki Hayashi
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Patent number: 8928070Abstract: The present invention provides a manufacturing method of a trench type power transistor device with a super junction. First, a substrate of a first conductivity type is provided, and then an epitaxial layer of a second conductive type is formed on the substrate. Next, a through hole is formed in the epitaxial layer, and the through hole penetrates through the epitaxial layer. Two doped drain regions of the first conductivity type are then formed in the epitaxial layer respectively at two sides of the through hole, and the doped drain regions extend from a top surface of the epitaxial layer to be in contact with the substrate.Type: GrantFiled: July 23, 2012Date of Patent: January 6, 2015Assignee: Anpec Electronics CorporationInventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Chia-Hao Chang
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Patent number: 8928072Abstract: Provided is a semiconductor device that can be manufactured at low cost and that can reduce a reverse leak current, and a manufacturing method thereof. A semiconductor device has: a source region and a drain region having a body region therebetween; a source trench that reaches the body region, penetrating the source region; a body contact region formed at the bottom of the source trench; a source electrode embedded in the source trench; and a gate electrode that faces the body region. The semiconductor device also has: an n-type region for a diode; a diode trench formed reaching the n-type region for a diode; a p+ region for a diode that forms a pn junction with the n-type region for a diode at the bottom of the diode trench; and a schottky electrode that forms a schottky junction with the n-type region for a diode at side walls of the diode trench.Type: GrantFiled: May 3, 2013Date of Patent: January 6, 2015Assignee: Rohm Co., Ltd.Inventor: Kenichi Yoshimochi
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Patent number: 8921136Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.Type: GrantFiled: January 17, 2013Date of Patent: December 30, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Neng-Kuo Chen, Shao-Ming Yu, Gin-Chen Huang, Chia-Jung Hsu, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 8916470Abstract: The present invention relates to a method of manufacturing sidewall spacers on a memory device. The method comprises forming sidewall spacers on a memory device having a memory array region and at least one peripheral circuit region by forming a first sidewall spacer adjacent to a word line in the memory array region and a second sidewall spacer adjacent to a transistor in the peripheral circuit region. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness, wherein the second thickness is greater than the first thickness.Type: GrantFiled: October 15, 2014Date of Patent: December 23, 2014Assignee: Nanya Technology CorporationInventors: Durga Panda, Jaydip Guha, Robert Kerr
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Source/drain zones with a delectric plug over an isolation region between active regions and methods
Patent number: 8907396Abstract: Devices, memory arrays, and methods are disclosed. In an embodiment, one such device has a source/drain zone that has first and second active regions, and an isolation region and a dielectric plug between the first and second active regions. The dielectric plug may extend below upper surfaces of the first and second active regions and may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.Type: GrantFiled: January 4, 2012Date of Patent: December 9, 2014Assignee: Micron Technology, IncInventors: John Hopkins, James Mathew, Jie Sun, Gordon Haller -
Patent number: 8900947Abstract: Methods of manufacturing a semiconductor device are provided. The method includes forming an isolation region in a substrate to define active regions extending in a single direction and being spaced apart from each other by the isolation region, forming a conductive layer in the isolation region and the active regions, etching the conductive layer to form bit line trenches extending in a first direction that is non-perpendicular to the single direction, forming bit line patterns in respective ones of the bit line trenches, etching the conductive layer to form a plurality of plug trenches two dimensionally arrayed along the first direction and a second direction perpendicular to the first direction, and filling the plug trenches with an insulation material to define conductive plug patterns in portions of the active regions. Related semiconductor devices are also provided.Type: GrantFiled: September 13, 2012Date of Patent: December 2, 2014Assignee: SK Hynix Inc.Inventor: Jin Yul Lee
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Patent number: 8901632Abstract: A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM region and a first protection layer over a logic region. A control gate and a storage layer are formed over the substrate in the NVM region. The control gate has a top surface below a top surface of the select gate. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The first and second protection layers are removed from the logic region. A portion of the second protection layer is left over the control gate and the select gate. A gate structure, formed over the logic region, has a high k dielectric and a metal gate.Type: GrantFiled: September 30, 2013Date of Patent: December 2, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Asanga H. Perera, Cheong Min Hong, Sung-Taeg Kang, Byoung W. Min, Jane A. Yater
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Patent number: 8895389Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a plurality of first doped regions and second doped regions; and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a first gate dielectric layer and a second gate dielectric layer; and forming a first metal gate and a second metal gate on the first gate dielectric layer and the second gate dielectric layer, respectively. Further, the method includes forming a third dielectric layer on the second metal gate; and forming a second dielectric layer on the first dielectric layer. Further, the method also includes forming at least one opening exposing at least one first metal gate and one first doped region; and forming a contact layer contacting with the first metal gate and the first doped region to be used as a share contact structure.Type: GrantFiled: June 17, 2013Date of Patent: November 25, 2014Assignee: Semiconductor Manufacturing International CorpInventor: Zhongshan Hong
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Patent number: 8895388Abstract: An object is to provide a technique for manufacturing an insulating layer with favorable withstand voltage. Another object is to provide a technique for manufacturing a semiconductor device having an insulating layer with favorable withstand voltage. By subjecting a semiconductor layer or semiconductor substrate mainly containing silicon to a high density plasma treatment, an insulating layer is formed on a surface of the semiconductor layer or a top surface of the semiconductor substrate. At this time, the high density plasma treatment is performed by switching a supply gas in the middle of the treatment from a gas containing a rare gas, oxygen, and hydrogen, to a gas containing a rare gas and oxygen.Type: GrantFiled: July 13, 2007Date of Patent: November 25, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tetsuya Kakehata, Tomokazu Yokoi
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Patent number: 8896060Abstract: A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.Type: GrantFiled: June 1, 2012Date of Patent: November 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Wai Ng, Hsueh-Liang Chou, Ruey-Hsin Liu, Po-Chih Su
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Patent number: 8889532Abstract: In one embodiment, a vertical insulated-gate field effect transistor includes a shield electrode formed in trench structure within a semiconductor material. A gate electrode is isolated from the semiconductor material using gate insulating layers. Before the shield electrode is formed, spacer layers can be used form shield insulating layers along portions of the trench structure. The shield insulating layers are thicker than the gate insulating layers. In another embodiment, the shield insulating layers have variable thickness.Type: GrantFiled: June 27, 2011Date of Patent: November 18, 2014Assignee: Semiconductor Components Industries, LLCInventors: Peter A. Burke, Gordon M. Grivna, Balaji Padmanabhan, Prasad Venkatraman
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Patent number: 8889513Abstract: A power semiconductor power device having composite trench bottom oxide and multiple trench floating gates is disclosed. The gate charge is reduced by forming a pad oxide surrounding a HDP oxide on trench bottom. The multiple trenched floating gates are applied in termination for saving body mask.Type: GrantFiled: July 29, 2013Date of Patent: November 18, 2014Assignee: Force Mos Technology Co., Ltd.Inventor: Fu-Yuan Hsieh
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Patent number: 8889539Abstract: A method of forming a semiconductor device is provided, comprising forming a plurality of hard masks on a substrate by patterning an insulating layer; forming a plurality of trenches in the substrate, each trench having trench walls disposed between two adjacent masks and extending vertically from a bottom portion to an upper portion; forming an insulating layer on the hard masks and the trench walls; forming a conductive layer on the insulating layer; etching the conductive layer to form conductive layer patterns to fill the bottom portions of the trenches; depositing a buffer layer on the conductive layer patterns and the trench walls; and filling the upper portions of the trenches with a capping layer.Type: GrantFiled: December 11, 2008Date of Patent: November 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-In Ryu, Bong-Su Kim, Dae-Ik Kim, Ho-Jun Lee, Dae-Young Jang, Si-Hyung Lee
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Patent number: 8871583Abstract: A non-planar JFET device having a thin fin structure is provided. A fin is formed projecting upwardly from or through a top surface of a substrate, where the fin has a first semiconductor layer portion formed from a first semiconductor material of a first conductivity type. The first semiconductor layer portion has a source region and a drain region, a channel region extending between the source region and the drain region. Two or more channel control regions are formed adjoining the channel region for generating charge depletion zones at and extending into the channel region for thereby controlling current conduction through the channel region. A gate is provided so as to adjoin and short together the at least two channel control regions from the outer sides of the channel control regions.Type: GrantFiled: November 13, 2012Date of Patent: October 28, 2014Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Mieno Fumitake
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Patent number: 8865547Abstract: Methods of fabricating a semiconductor device are provided. The method includes forming active lines in a semiconductor substrate, forming contact lines generally crossing over the active lines, forming line-shaped etch mask patterns generally crossing over the active lines and the contact lines, etching the contact lines exposed by the line-shaped etch mask patterns to form contact separation grooves and to form contact patterns generally remaining at intersections between the line-shaped etch mask patterns and the active lines, etching the active lines exposed by the contact separation grooves to form active separation grooves that generally divide each of the active lines into a plurality of active patterns, forming gates that substantially intersect the active patterns, and forming bit lines electrically connected to the contact patterns.Type: GrantFiled: September 14, 2012Date of Patent: October 21, 2014Assignee: SK Hynix Inc.Inventor: Chun Soo Kang
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Patent number: 8859365Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes: forming a plurality of trenches; forming a gate insulating film; burying a gate electrode; burying an insulating member; projecting the insulating member; forming a base layer; forming a mask film; forming a first semiconductor layer; forming a carrier ejection layer; forming a first electrode; and forming a second electrode. The projecting includes projecting the insulating member from the upper surface of the semiconductor substrate by removing an upper layer portion of the semiconductor substrate. The mask film is formed so as to cover the projected insulating member. The forming the first semiconductor layer includes forming a first semiconductor layer of the first conductivity type in an upper layer portion of the base layer by doping the base layer with impurity, the upper layer portion having a lower surface below an upper end of the gate electrode.Type: GrantFiled: March 3, 2014Date of Patent: October 14, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hideki Okumura, Hiroto Misawa, Takahiro Kawano
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Patent number: 8859369Abstract: Provided is a semiconductor device having a vertical MOS transistor and a method of manufacturing the same. The vertical MOS transistor has a trench gate, a distance between a gate electrode and an N-type high concentration buried layer below the gate electrode is formed longer than that in the conventional structure, and a P-type trench bottom surface lower region (5) is formed therebetween. In this manner, when a high voltage is applied to a drain region and 0 V is applied to the gate electrode, the trench bottom surface lower region (5) is depleted, thereby increasing the breakdown voltage in the OFF state.Type: GrantFiled: February 7, 2013Date of Patent: October 14, 2014Assignee: Seiko Instruments Inc.Inventor: Yukimasa Minami
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Patent number: 8859367Abstract: A method of forming a gate construction of a recessed access device includes forming a pair of sidewall spacers laterally over opposing sidewalls of a gate dielectric and elevationally over first conductive gate material. The gate dielectric, the first conductive gate material, and the sidewall spacers are received within a trench formed in semiconductive material. Second conductive gate material is deposited within the semiconductive material trench between the pair of sidewall spacers in electrical connection with the first conductive gate material. Other implementations are disclosed, including recessed access device gate constructions independent of method of manufacture.Type: GrantFiled: July 9, 2010Date of Patent: October 14, 2014Assignee: Micron Technology, Inc.Inventors: Suraj Mathew, Jaydip Guha
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Publication number: 20140302650Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.Type: ApplicationFiled: June 20, 2014Publication date: October 9, 2014Inventors: Sanh D. Tang, John K. Zahurak
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Patent number: 8853764Abstract: A method for forming a low Rdson LDNMOS and a high sheet resistance poly resistor and the resulting device are provided. Embodiments include forming first, second, and third STI regions in a substrate; forming a P-well in the substrate around the first STI region with a first mask; forming an N-drift region in the substrate between the P-well and the third STI region with the first mask; forming a dielectric layer over the substrate; forming a poly-silicon layer over the dielectric layer; performing an N-drain implant between the second and third STI regions with a second mask; performing a resistance adjustment implant in, but not through, the poly-silicon layer with the second mask; and patterning the poly-silicon and dielectric layers subsequent to performing the resistance adjustment implant to form a gate stack and a poly resistor, the poly resistor being formed over the third STI region and laterally separated from the gate stack.Type: GrantFiled: March 15, 2013Date of Patent: October 7, 2014Assignee: GLOBALFOUNDRIES Singapore Pte. LtdInventors: Guowei Zhang, Deyan Chen
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Patent number: 8853033Abstract: A method for fabricating a semiconductor device includes: sequentially forming an n? type epitaxial layer, a p type epitaxial layer, and a first n+ region on a first surface of an n+ type silicon carbide substrate; forming a trench by penetrating the first n+ region and the p type epitaxial layer, and etching part of the n? type epitaxial layer; forming a buffer layer in the trench and on the first n+ region; etching the buffer layer to form a buffer layer pattern on both sidewalls defined by the trench; forming a first silicon film on the first n+ region, the buffer layer pattern, and a surface of the n? type epitaxial layer exposed by the trench; oxidizing the first silicon film to form a first silicon oxide film; removing the buffer layer pattern by an ashing process to form a first silicon oxide film pattern; forming a second silicon film on the first silicon oxide film pattern and in the trench; oxidizing the second silicon film to form a second silicon oxide film; and etching the second silicon oxide fiType: GrantFiled: September 12, 2013Date of Patent: October 7, 2014Assignee: Hyundai Motor CompanyInventors: Youngkyun Jung, Kyoung-Kook Hong, Jong Seok Lee, Dae Hwan Chun
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Patent number: 8853695Abstract: A substrate supporting thin film transistors thereon, each including a semiconductor layer and source-drain electrodes, wherein the source-drain electrodes are formed from a nitrogen-containing layer or oxygen/nitrogen-containing layer and a thin film of pure copper or copper alloy. The nitrogen-containing layer or oxygen/nitrogen-containing layer has respectively part or all of its nitrogen or part or all of its oxygen or nitrogen connected to silicon in the semiconductor layer of the thin film transistor, and the thin film of pure copper or copper alloy is connected to the semiconductor layer of said thin film transistor through the nitrogen-containing layer or oxygen/nitrogen-containing layer.Type: GrantFiled: October 12, 2007Date of Patent: October 7, 2014Assignee: Kobe Steel, Ltd.Inventors: Aya Hino, Hiroshi Gotou
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Patent number: 8846469Abstract: A fabrication method of a trenched power semiconductor device with source trench is provided. Firstly, at least two gate trenches are formed in a base. Then, a dielectric layer and a polysilicon structure are sequentially formed in the gate trench. Afterward, at least a source trench is formed between the neighboring gate trenches. Next, the dielectric layer and a second polysilicon structure are sequentially formed in the source trench. The second polysilicon structure is located in a lower portion of the source trench. Then, the exposed portion of the dielectric layer in the source trench is removed to expose a source region and a body region. Finally, a conductive structure is filled into the source trench to electrically connect the second polysilicon structure, the body region, and the source region.Type: GrantFiled: May 12, 2012Date of Patent: September 30, 2014Assignee: Great Power Semiconductor Corp.Inventors: Chun Ying Yeh, Hsiu Wen Hsu
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Patent number: 8841183Abstract: On a silicon substrate is formed a stacked body by alternately stacking a plurality of silicon oxide films and silicon films, a trench is formed in the stacked body, an alumina film, a silicon nitride film and a silicon oxide film are formed in this order on an inner surface of the trench, and a channel silicon crystalline film is formed on the silicon oxide film. Next, a silicon oxide layer is formed at an interface between the silicon oxide film and the channel silicon crystalline film by performing thermal treatment in an oxygen gas atmosphere.Type: GrantFiled: March 10, 2011Date of Patent: September 23, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Yoshio Ozawa
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Publication number: 20140264530Abstract: A memory cell formed by forming a trench in the surface of a substrate. First and second spaced apart regions are formed in the substrate with a channel region therebetween. The first region is formed under the trench. The channel region includes a first portion that extends along a sidewall of the trench and a second portion that extends along the surface of the substrate. A charge trapping layer in the trench is adjacent to and insulated from the first portion of the channel region for controlling the conduction of the channel region first portion. An electrically conductive gate in the trench is adjacent to and insulated from the charge trapping layer and from the first region and is capacitively coupled to the charge trapping layer. An electrically conductive control gate is disposed over and insulated from the second portion of the channel region for controlling its conduction.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: Silicon Storage Technology, Inc.Inventor: Nhan Do
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Patent number: 8835254Abstract: A method of forming a device in each of vertical trench gate MOSFET region and control lateral planar gate MOSFET region of a semiconductor substrate is disclosed. A trench is formed in the substrate in the vertical trench gate MOSFET region, a first gate oxide film is formed along the internal wall of the trench, and the trench is filled with a polysilicon film. A LOCOS oxide film is formed in a region isolating the devices. A second gate oxide film is formed on the substrate in the lateral planar gate MOSFET region. Advantages are that number of steps is suppressed, the gate threshold voltage of an output stage MOSFET is higher than the gate threshold voltage of a control MOSFET, the thickness of the LOCOS oxide film does not decrease, and no foreign object residue remains inside the trench.Type: GrantFiled: November 13, 2013Date of Patent: September 16, 2014Assignee: Fuji Electric Co., Ltd.Inventors: Yoshiaki Toyoda, Takatoshi Ooe
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Patent number: 8835294Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure on the substrate, the gate structure including a dummy gate, removing the dummy gate from the gate structure thereby forming a trench, forming a work function metal layer partially filling the trench, forming a fill metal layer filling a remainder of the trench, performing a chemical mechanical polishing (CMP) to remove portions of the metal layers outside the trench, and implanting Si, C, or Ge into a remaining portion of the fill metal layer.Type: GrantFiled: March 16, 2010Date of Patent: September 16, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Guan Chew, Ming Zhu, Lee-Wee Teo, Harry Hak-Lay Chuang, Yi-Ren Chen
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Patent number: 8829597Abstract: A nonvolatile memory device includes a plurality of channel connection layers formed over a substrate; a first gate electrode layer filling a space between the plurality channel connection layers; a gate dielectric layer interposed between each of the channel connection layers and the first gate electrode layer; a stacked structure formed over the plurality channel connection layers and the first gate electrode layer, the stacked structure including a plurality of interlayer dielectric layers and a plurality second gate electrode layers, which are alternately stacked; a pair of channel layers, formed through the stacked structure and connected to each channel connection layer of the plurality of channel connection layers; and a memory layer interposed between each of the channel layers and each of the second gate electrode layers.Type: GrantFiled: December 18, 2012Date of Patent: September 9, 2014Assignee: SK Hynix Inc.Inventor: Su-Chang Kwak