Abstract: A memory device, such as a flash EEPROM, has zero birds' beaks and vertically overlapping gates to facilitate high cell density in the EEPROM's core. During fabrication, a layer of field oxide is formed over the core. The active regions are exposed by etching through the layer of field oxide to form vertically walled cavities around the active regions. The tunnel oxide, floating gate, interpoly dielectric, and the control gate are formed within each cavity so that the floating gate overlaps the control gate along the vertical walls. As a result, capacitive coupling between the gates is maintained, yet the horizontal dimensions of the cell decrease. Similarly, the absence of birds' beaks facilitates higher cell density in the core.

Abstract: A memory device, such as a flash EEPROM, employs a high energy implantation to form common source line, avoiding the necessity of self-aligned source etch processes. The use of the high energy implantation, and avoiding the etching process, provides for greater cell uniformity, and better V.sub.T distribution.