Totally Embedded In Semiconductive Layers Patents (Class 438/272)
  • Patent number: 10431678
    Abstract: A plurality of trench stripes are disposed in parallel in an epitaxial layer on a drain and extends from a top region to a bottom region of a first surface of the semiconductor. A first polysilicon layer is in each of the trench stripes. The first polysilicon layer extends between the drain and the first surface proximal to the top region and the bottom region, and between the drain and a level below the first surface in a middle region between the top region and the bottom region. A second polysilicon layer is over the first polysilicon layer in the middle region, wherein the first poly silicon layer forms a shield, and the second polysilicon layer forms a gate. A source is in a silicon mesa stripe surrounding the first trench stripe.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: October 1, 2019
    Assignee: NXP USA, Inc.
    Inventors: Ganming Qin, Vishnu Khemka, Ljubo Radic, Bernhard Grote, Tanuj Saxena, Moaniss Zitouni
  • Patent number: 9997608
    Abstract: Disclosed is a transistor device. The transistor device includes a plurality of device cells each having an active device region integrated in a semiconductor body and electrically connected to a contact layer. The contact layer includes a plurality of layer sections separated from each other by a separation layer. A resistivity of the separation layer is at least 100 times the resistivity of the layer sections.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: June 12, 2018
    Assignee: Infineon Technologies AG
    Inventors: Karoline Koepp, Herbert Gietler
  • Patent number: 9991353
    Abstract: Machining accuracy of an IGBT region is worsened due to a height difference caused by polysilicon. Therefore, there is a problem that characteristic variation of the IGBT increases. Provided is a semiconductor device including a semiconductor substrate; a gate wiring layer provided on a front surface side of the semiconductor substrate; and a gate structure that includes a gate electrode and is provided on the front surface of the semiconductor substrate. The gate wiring layer includes an outer periphery portion that is a metal wiring layer and is provided along an outer periphery of the semiconductor substrate; and an extending portion that is a metal wiring layer, is provided extending from the outer periphery portion toward a central portion of the semiconductor substrate, and is electrically connected to the gate electrode.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: June 5, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 9899267
    Abstract: A semiconductor device includes a semiconductor substrate, a shallow trench isolation structure, a plurality of gate electrodes, and a gate isolation structure. The semiconductor substrate includes a plurality of fin structures, and each of the fin structures is elongated in a first direction. The shallow trench isolation structure is disposed on the semiconductor substrate and disposed between the fin structures. The gate electrodes are disposed on the semiconductor substrate and the shallow trench isolation structure. Each of the gate electrodes is elongated in a second direction and disposed straddling at least one of the fin structures. The gate isolation structure is disposed between two adjacent gate electrodes in the second direction, and a bottom surface of the gate isolation structure is lower than a top surface of the shallow trench isolation structure.
    Type: Grant
    Filed: December 25, 2016
    Date of Patent: February 20, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung
  • Patent number: 9812548
    Abstract: In one embodiment, a power MOSFET vertically conducts current. A bottom electrode may be connected to a positive voltage, and a top electrode may be connected to a low voltage, such as a load connected to ground. A gate and/or a field plate, such as polysilicon, is within a trench. The trench has a tapered oxide layer insulating the polysilicon from the silicon walls. The oxide is much thicker near the bottom of the trench than near the top to increase the breakdown voltage. The tapered oxide is formed by implanting nitrogen into the trench walls to form a tapered nitrogen dopant concentration. This forms a tapered silicon nitride layer after an anneal. The tapered silicon nitride variably inhibits oxide growth in a subsequent oxidation step.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: November 7, 2017
    Assignee: MAXPOWER SEMICONDUCTOR, INC.
    Inventors: Richard A. Blanchard, Mohamed N. Darwish, Jun Zeng
  • Patent number: 9653462
    Abstract: A semiconductor device includes a fin type active pattern extended in a first direction and disposed on a substrate. A first gate electrode and a second gate electrode are disposed on the fin type active pattern. The first gate electrode and the second gate electrode are extended in a second direction crossing the first direction. A trench region is disposed in the fin type active pattern and between the first gate electrode and the second gate electrode. A source/drain region is disposed on a surface of the trench region. A source/drain contact is disposed on the source/drain region. The source/drain contact includes a first insulating layer disposed on the source/drain region and a metal oxide layer disposed on the first insulating layer.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: May 16, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Dae Suk, Kang-Ill Seo
  • Patent number: 9275908
    Abstract: A semiconductor device includes at least one first semiconductor fin formed on an nFET region of a semiconductor device and at least one second semiconductor fin formed on a pFET region. The at least one first semiconductor fin has an nFET channel region interposed between a pair of nFET source/drain regions. The at least one second semiconductor fin has a pFET channel region interposed between a pair of pFET source/drain regions. The an epitaxial liner is formed on only the pFET channel region of the at least one second semiconductor fin such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: March 1, 2016
    Assignee: International Business Machines Corporation
    Inventors: Pranita Kerber, Qiqing C. Ouyang, Alexander Reznicek
  • Patent number: 9196654
    Abstract: The disclosure relates to a method of fabricating a vertical MOS transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer in at least one dielectric layer; etching a hole through at least the conductive layer, the hole exposing an inner lateral edge of the conductive layer and a portion of the semiconductor surface; forming a gate oxide on the inner lateral edge of the conductive layer and a bottom oxide on the portion of the semiconductor surface; forming an etch-protection sidewall on the lateral edge of the hole, the sidewall covering the gate oxide and an outer region of the bottom oxide, leaving an inner region of the bottom oxide exposed; etching the exposed inner region of the bottom oxide until the semiconductor surface is reached; and depositing a semiconductor material in the hole.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: November 24, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Philippe Boivin
  • Patent number: 9048218
    Abstract: A semiconductor device includes a supplementary layer and a silicon layer stacked over a substrate, a trench penetrating the supplementary layer and the silicon layer and formed over the substrate, a gate insulation layer formed along a surface of the trench, and a buried gate formed over the gate insulation layer and filling a portion of the trench.
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: June 2, 2015
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seung-Ryong Lee, Tae-Hang Ahn
  • Patent number: 9029220
    Abstract: Semiconductor oxide pillars are selectively grown on semiconductor mesas between precursor structures that extend from a main surface into a semiconductor substrate. Spaces between the semiconductor oxide pillars are filled with one or more auxiliary materials to form alignment plugs in a vertical projection of the precursor structures. The semiconductor oxide pillars are removed selectively against the alignment plugs. Contact spacers are provided along sidewalls of the alignment plugs. Between opposing ones of the contact spacers contact plugs are provided directly adjoining the semiconductor mesas. The contact plugs are self-aligned to the semiconductor mesas and allow a further reduction of the lateral dimensions of the semiconductor mesas without recessing the semiconductor mesas.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Poelzl
  • Patent number: 9018062
    Abstract: In one embodiment, a method of making a super-junction MOS transistor in a wafer can include: (i) forming a first doping layer having a high doping concentration; (ii) forming a second doping layer on the first doping layer, wherein a doping concentration of the second doping layer is less than a doping concentration of the first doping layer; (iii) forming a third doping layer on the second doping layer, wherein the third doping layer comprises an intrinsic layer; (iv) etching through the third doping layer and partially through the second doping layer to form trenches; and (v) filling the trenches to form pillar structures.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: April 28, 2015
    Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd.
    Inventor: Zhongping Liao
  • Patent number: 8999790
    Abstract: A method of forming a trench gate MOSFET is provided. An epitaxial layer is formed on a substrate. A trench is formed in the epitaxial layer. A first insulating layer is conformally formed on surfaces of the epitaxial layer and the trench. A first conductive layer is formed at the bottom of the trench. A portion of the first insulating layer is removed to form a second insulating layer exposing an upper portion of the first conductive layer. An oxidation process is performed to oxidize the first conductive layer to a third insulating layer, wherein a fourth insulating layer is simultaneously formed on the surface of the epitaxial layer and on the sidewall of the trench. A second conductive layer is formed in the trench. Two body layers are formed in the epitaxial layer beside the trench. Two doped regions are formed in the body layers respectively beside the trench.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: April 7, 2015
    Assignee: UBIQ Semiconductor Corp.
    Inventors: Chien-Ling Chan, Chi-Hsiang Lee
  • Patent number: 8999783
    Abstract: A method for producing a semiconductor device is disclosed. The method includes providing a semiconductor body having a first surface, and a second surface opposite the first surface, producing a first trench having a bottom and sidewalls and extending from the first surface into the semiconductor body, forming a dielectric layer along at least one sidewall of the trench, and filling the trench with a filling material. Forming the dielectric layer includes forming a protection layer on the least one sidewall such that the protection layer leaves a section of the at least one sidewall uncovered, oxidizing the semiconductor body in the region of the uncovered sidewall section to form a first section of the dielectric layer, removing the protection layer, and forming a second section of the dielectric layer on the at least one sidewall.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: April 7, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Franz Hirler, Andreas Meiser
  • Patent number: 8980713
    Abstract: A method for fabricated a buried recessed access device comprising etching a plurality of gate trenches in a substrate, implanting and activating a source/drain region in the substrate, depositing a dummy gate in each of the plurality of gate trenches, filling the plurality of gate trenches with an oxide layer, removing each dummy gate and depositing a high-K dielectric in the plurality of gate trenches, depositing a metal gate on the high-K dielectric in each of the plurality of gate trenches, depositing a second oxide layer on the metal gate and forming a contact on the source/drain.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: March 17, 2015
    Assignee: Sony Corporation
    Inventors: Satoru Mayuzumi, Mark Fischer, Michael Violette
  • Patent number: 8969959
    Abstract: There are provided a semiconductor device and a method of manufacturing the same. The semiconductor device includes a body layer of a first conductivity type; an active layer of a second conductivity type, contacting an upper portion of the body layer; and a field limiting ring of a first conductivity type, formed in an upper portion of the active layer.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: March 3, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Chang Su Jang
  • Patent number: 8969157
    Abstract: According to one embodiment, in a method of a semiconductor device, a trench is formed in the direction of a lower surface from an upper surface of a semiconductor layer. A first insulating film is formed to cover an inner surface of the trench. An electrode material is formed to fill the trench and cover the upper surface of the semiconductor layer. The electrode material is selectively removed except a portion of the electrode material to fill the trench and a portion of the electrode material to cover an opening of the trench. The first insulating film to cover an upper portion of the trench is removed. The portions of the electrode material to fill the trench and cover the opening of the trench are etched back to form a first electrode at a lower portion of the trench.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: March 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuhiro Takahashi, Yukie Nishikawa, Yasuhiko Akaike
  • Patent number: 8962455
    Abstract: A method of fabricating a semiconductor device includes forming a first preliminary gate barrier layer and a first preliminary gate electrode recessed to have a first depth from the surface of the substrate within a gate trench, removing an upper portion of the first preliminary gate electrode by means of a first wet etching process using a first etchant to form a second preliminary gate electrode recessed to have a second depth greater than the first depth, and removing an upper portion of the first preliminary gate barrier layer and an upper portion of the second preliminary gate electrode by means of a second wet etching process using a second etchant to form a gate electrode and a gate barrier layer recessed to a third depth greater than the second depth.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Hyun Choi, Jin-Ho Noh, Yoon-Ho Son, Dae-Hyuk Chung, In-Seak Hwang, Tae-Joon Park, Tae-Ho Hwang
  • Patent number: 8946816
    Abstract: Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: February 3, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Hamza Yilmaz, Sik Lui, Daniel Ng
  • Patent number: 8927369
    Abstract: A method of forming a trench gate MOSFET is provided. An epitaxial layer is formed on a substrate. A trench is formed in the epitaxial layer. A first insulating layer is conformally formed on surfaces of the epitaxial layer and the trench. A first conductive layer is formed at the bottom of the trench. A portion of the first insulating layer is removed to form a second insulating layer exposing an upper portion of the first conductive layer. An oxidation process is performed to oxidize the first conductive layer to a third insulating layer, wherein a fourth insulating layer is simultaneously formed on the surface of the epitaxial layer and on the sidewall of the trench. A second conductive layer is formed in the trench. Two body layers are formed in the epitaxial layer beside the trench. Two doped regions are formed in the body layers respectively beside the trench.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: January 6, 2015
    Assignee: UBIQ Semiconductor Corp.
    Inventors: Chien-Ling Chan, Chi-Hsiang Lee
  • Patent number: 8912070
    Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stack structure on a substrate; forming a drain region in the substrate on one side of the gate stack structure; and forming a source region made of GeSn in the substrate on the other side of the gate stack structure; wherein the forming the source region made of GeSn comprises: implanting precursors in the substrate on the other side of the gate stack structure; and performing a laser rapid annealing such that the precursors react to produce GeSn alloy, thereby to constitute a source region; and wherein the step of implanting precursors further comprises: performing a pre-amorphization ion implantation, so as to form an amorphized region in the substrate; and implanting Sn in the amorphized region.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: December 16, 2014
    Assignee: The Institute of Microelectronics Chinese Academy of Science
    Inventors: Xiaolong Ma, Huaxiang Yin, Zuozhen Fu
  • Patent number: 8895394
    Abstract: A high voltage vertical field effect transistor device (101) is fabricated in a substrate (102, 104) using angled implantations (116, 120) into trench sidewalls formed above recessed gate poly layers (114) to form self-aligned N+ regions (123) adjacent to the trenches and along an upper region of an elevated substrate. With a trench fill insulator layer (124) formed over the recessed gate poly layers (114), self-aligned P+ body contact regions (128) are implanted into the elevated substrate without counter-doping the self-aligned N+ regions (123), and a subsequent recess etch removes the elevated substrate, leaving self-aligned N+ source regions (135-142) and P+ body contact regions (130-134).
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: November 25, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Ganming Qin, Edouard D. de Frésart, Peilin Wang, Pon S. Ku
  • Patent number: 8890252
    Abstract: A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: November 18, 2014
    Assignee: DENSO CORPORATION
    Inventors: Hirotaka Saikaku, Tsuyoshi Yamamoto, Shoji Mizuno, Masakiyo Sumitomo, Tetsuo Fujii, Jun Sakakibara, Hitoshi Yamaguchi, Yoshiyuki Hattori, Rie Taguchi, Makoto Kuwahara
  • Patent number: 8883596
    Abstract: A semiconductor device with vertical channel transistors and a method of fabricating the same are provided. A method of fabricating the semiconductor device includes patterning a substrate to form a trench that defines an active region, forming a sacrificial pattern in a lower region of the trench, forming a spacer on an upper sidewall of the trench, recessing a top surface of the sacrificial pattern to form a window exposing a sidewall of the active region between the spacer and the sacrificial pattern, doping a sidewall of the trench through the window to form a doped region in the active region, and forming a wiring in the trench to be connected to the doped region.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seonghwee Cheong, Mansug Kang, Joon Kim, Kihong Nam, Gyuwan Choi
  • Patent number: 8878271
    Abstract: Methods, apparatuses, and systems for providing a body connection to a vertical access device. The vertical access device may include a digit line extending along a substrate to a digit line contact pillar, a body connection line extending along the substrate to a body connection line contact pillar, a body region disposed on the body connection line, an electrode disposed on the body region, and a word line extending to form a gate to the body region. A method for operation includes applying a first voltage to the body connection line, and applying a second voltage to the word line to cause a conductive channel to form through the body region. A memory cell array may include a plurality of vertical access devices.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: November 4, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Rajesh N. Gupta, Srinivas Pulugurtha, Chandra V. Mouli, Wolfgang Mueller
  • Patent number: 8872172
    Abstract: Semiconductor structures having embedded source/drains with oxide underlayers and methods for forming the same. Embodiments include semiconductor structures having a channel in a substrate, and a source/drain region adjacent to the channel including an embedded oxide region and an embedded semiconductor region located above the embedded oxide region. Embodiments further include methods of forming a transistor structure including forming a gate on a substrate, etching a source/drain recess in the substrate, filling a bottom portion of the source/drain recess with an oxide layer, and filling a portion of the source/drain recess not filled by the oxide layer with a semiconductor layer.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Raghavasimhan Sreenivasan, Thomas N. Adam
  • Patent number: 8871593
    Abstract: A semiconductor device includes a gate electrode buried in a semiconductor portion. The gate electrode includes a first gate portion on a first side of a longitudinal center axis of the gate electrode parallel to the main surface and a second gate portion on an opposite, second side of the longitudinal center axis. At least one first gate contact extends from a main side defined by a main surface into the first gate portion.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: October 28, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, Michael Hutzler, Oliver Blank
  • Patent number: 8865550
    Abstract: A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: October 21, 2014
    Assignee: Nanya Technology Corp.
    Inventors: Tieh-Chiang Wu, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8859370
    Abstract: A method for forming an impurity region of a vertical transistor includes forming an impurity ion junction region within a semiconductor substrate, and forming a trench by etching the semiconductor substrate in which the impurity ion junction region is formed. The etching process is performed to remove a portion of the impurity ion junction region, so that a remaining portion of the impurity ion junction region is exposed to a lower side wall of the trench to serve as a buried bit line junction region.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: October 14, 2014
    Assignee: SK Hynix Inc.
    Inventors: Yong Seok Eun, Tae Kyun Kim, Kyong Bong Rouh, Eun Shil Park
  • Patent number: 8853774
    Abstract: A semiconductor device includes a first transistor cell including a first gate electrode in a first trench. The semiconductor device further includes a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected. The semiconductor device further includes a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches. The semiconductor device further includes a dielectric in the third trench covering a bottom side and walls of the third trench.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: October 7, 2014
    Assignee: Infineon Technologies AG
    Inventors: Maria Cotorogea, Hans Peter Felsl, Yvonne Gawlina, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, Georg Seibert, Andre Rainer Stegner, Wolfgang Wagner
  • Patent number: 8853033
    Abstract: A method for fabricating a semiconductor device includes: sequentially forming an n? type epitaxial layer, a p type epitaxial layer, and a first n+ region on a first surface of an n+ type silicon carbide substrate; forming a trench by penetrating the first n+ region and the p type epitaxial layer, and etching part of the n? type epitaxial layer; forming a buffer layer in the trench and on the first n+ region; etching the buffer layer to form a buffer layer pattern on both sidewalls defined by the trench; forming a first silicon film on the first n+ region, the buffer layer pattern, and a surface of the n? type epitaxial layer exposed by the trench; oxidizing the first silicon film to form a first silicon oxide film; removing the buffer layer pattern by an ashing process to form a first silicon oxide film pattern; forming a second silicon film on the first silicon oxide film pattern and in the trench; oxidizing the second silicon film to form a second silicon oxide film; and etching the second silicon oxide fi
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: October 7, 2014
    Assignee: Hyundai Motor Company
    Inventors: Youngkyun Jung, Kyoung-Kook Hong, Jong Seok Lee, Dae Hwan Chun
  • Patent number: 8853029
    Abstract: An electronic device has a plurality of trenches formed in a semiconductor layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric having increased thickness at greater depth is located between the field plate section and the vertical drift region.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: October 7, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Marie Denison, Sameer Pendharkar, Philip L. Hower, John Lin
  • Patent number: 8841722
    Abstract: A semiconductor device includes a semiconductor substrate having a first groove. The first groove has a bottom and first and second side surfaces opposite to each other. A first gate insulator extends alongside the first side surface. A first gate electrode is formed in the first groove and on the first gate insulator. A second gate insulator extends alongside the second side surface. A second gate electrode is formed in the first groove and on the second gate insulator. The second gate electrode is separate from the first gate electrode.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: September 23, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Masayoshi Sammi
  • Publication number: 20140273374
    Abstract: Vertical doping in power semiconductor devices and methods for making such dopant profiles are described. The methods include providing a semiconductor substrate, providing an epitaxial layer on the substrate, the epitaxial layer comprising a bottom portion containing a first conductivity type dopant in a substantially constant, first concentration throughout the bottom portion; and an upper portion containing a first conductivity type dopant having a second concentration lower than the first concentration; providing a trench in the epitaxial layer; forming a transistor structure in the trench; and forming a well region in the upper part of the epitaxial layer adjacent the trench, the well region containing a second conductivity type dopant that is opposite the first conductivity type. Other embodiments are described.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Joseph Yedinak, Richard Stokes, Sukhendu Deb Roy, Steven Sapp
  • Patent number: 8836024
    Abstract: An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate, wherein the patterned semiconductor layer defines first and second trenches. The electronic device can also include a first conductive structure within the first trench, a gate electrode within the first trench and overlying the first conductive structure, a first insulating member within the second trench, and a second conductive structure within the second trench. The second conductive structure can include a first portion and a second portion overlying the first portion, the first insulating member can be disposed between the patterned semiconductor layer and the first portion of the second conductive structure; and the second portion of the second conductive structure can contact the patterned semiconductor layer at a Schottky region. Processes of forming the electronic device can take advantage of integrating formation of the Schottky region into a contact process flow.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: September 16, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Balaji Padmanabhan, James Sellers
  • Patent number: 8829609
    Abstract: An insulated gate semiconductor device, comprising: a semiconductor body having a front side and a back side opposite to one another; a drift region, which extends in the semiconductor body and has a first type of conductivity and a first doping value; a body region having a second type of conductivity, which extends in the drift region facing the front side of the semiconductor body; a source region, which extends in the body region and has the first type of conductivity; and a buried region having the second type of conductivity, which extends in the drift region at a distance from the body region and at least partially aligned to the body region in a direction orthogonal to the front side and to the back side.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: September 9, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Donato Corona, Giovanni Samma Trice, Sebastiano Amara, Salvatore Pisano, Antonio Giuseppe Grimaldi
  • Patent number: 8815689
    Abstract: A method for fabricating a semiconductor device includes forming a pad nitride layer that exposes an isolation region over a cell region of a semiconductor substrate; forming a trench in the isolation region of the semiconductor substrate; forming an isolation layer within the trench; etching an active region of the semiconductor substrate by a certain depth to form a recessed isolation region; etching the isolation layer by a certain depth to form a recessed isolation region; depositing a gate metal layer in the recessed active region and the recessed isolation region to form a gate of a cell transistor; forming an insulation layer over an upper portion of the gate; removing the pad nitride layer to expose a region of the semiconductor substrate to be formed with a contact plug; and depositing a conductive layer in the region of the semiconductor substrate to form a contact plug.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: August 26, 2014
    Assignee: SK hynix Inc.
    Inventors: Jin Yul Lee, Dong Seok Kim
  • Publication number: 20140213027
    Abstract: A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line.
    Type: Application
    Filed: February 20, 2014
    Publication date: July 31, 2014
    Applicant: NANYA TECHNOLOGY CORP.
    Inventors: Tieh-Chiang Wu, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8772111
    Abstract: A trench gate semiconductor device is disclosed which has a trench gate structure including an insulator in the upper portion of a first trench, the insulator being on a gate electrode; a source region having a lower end surface positioned lower than the upper surface of the gate electrode; a second trench in the surface portion of a semiconductor substrate between the first trenches, the second trench having a slanted inner surface providing the second trench with the widest trench width at its opening and a bottom plane positioned lower than the lower end surface of the source region, the slanted inner surface being in contact with the source region; and a p-type body-contact region in contact with the slanted inner surface of the second trench. The trench gate semiconductor device and its manufacturing method facilitate increasing the channel density and lowering the body resistance of the parasitic BJT.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: July 8, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Yoshihiro Ikura
  • Patent number: 8753935
    Abstract: Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 17, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Hamza Yilmaz, Sik Lui, Daniel Ng
  • Patent number: 8748262
    Abstract: In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: June 10, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Francine Y. Robb, Stephen P. Robb, Prasad Venkatraman, Zia Hossain
  • Patent number: 8741736
    Abstract: A semiconductor device includes a source, a drain, and a gate configured to selectively enable a current to pass between the source and the drain. The semiconductor device includes a drift zone between the source and the drain and a first field plate adjacent the drift zone. The semiconductor device includes a dielectric layer electrically isolating the first field plate from the drift zone and charges within the dielectric layer close to an interface of the dielectric layer adjacent the drift zone.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: June 3, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Rudolf Berger, Franz Hirler, Ralf Siemieniec, Hans-Joachim Schulze
  • Patent number: 8742490
    Abstract: The present technology is directed generally to a semiconductor device. In one embodiment, the semiconductor device includes a first vertical transistor and a second vertical transistor, and the first vertical transistor is stacked on top of the second vertical transistor. The first vertical transistor is mounted on a lead frame with the source electrode of the first vertical transistor coupled to the lead frame. The second vertical transistor is stacked on the first vertical transistor with the source electrode of the second vertical transistor coupled to the drain electrode of the first vertical transistor.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: June 3, 2014
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Donald R. Disney
  • Patent number: 8728891
    Abstract: Contact openings are produced in a semiconductor body by forming a plurality of self-aligned structures on a main surface of a semiconductor body, each self-aligned structure filling a trench formed in the semiconductor body and extending above and onto the main surface. Adjacent ones of the self-aligned structures have spaced apart sidewalls which face each other. A spacer layer is formed on the sidewalls of the self-aligned structures. Openings are formed in the semiconductor body between adjacent ones of the self-aligned structures while the spacer layer is on the sidewalls of the self-aligned structures. Each opening has a width and a distance to the sidewall of an adjacent trench which corresponds to a thickness of the spacer layer. Self-aligned contact structures can also be produced on a semiconductor body, with or without using the spacer layer.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: May 20, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Heimo Hofer, Martin Poelzl
  • Patent number: 8703563
    Abstract: A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: April 22, 2014
    Assignee: Alpha & Omega Semiconductor Ltd
    Inventors: François Hébert, Anup Bhalla
  • Patent number: 8697520
    Abstract: A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: April 15, 2014
    Assignee: Alpha & Omega Semiconductor Incorporationed
    Inventors: Yeeheng Lee, Yongping Ding, Xiaobin Wang
  • Patent number: 8679921
    Abstract: Lithographic limitations on gate and induced channel length in MOSFETS are avoided by forming non-planar MOSFETS in a cavity extending into a semiconductor substrate. The gate insulator and channel region lie proximate a cavity sidewall having angle ? preferably about ?90 degrees with respect to the semiconductor surface. The channel length depends on the bottom depth of the cavity and the depth from the surface of a source or drain region adjacent the cavity. The corresponding drain or source lies at the cavity bottom. The cavity sidewall extends therebetween. Neither depth is lithographic dependent. Very short channels can be consistently formed, providing improved performance and manufacturing yield. Source, drain and gate connections are brought to the same surface so that complex circuits can be readily constructed. The source and drain regions are preferably formed epitaxially and strain inducing materials can be used therein to improve channel carrier mobility.
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: March 25, 2014
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Stefan Flachowsky, Thilo Scheiper
  • Patent number: 8647972
    Abstract: Embodiments relate to a field-effect transistor (FET) replacement gate apparatus. The apparatus includes one or more of a substrate and insulator including a base and side walls defining a trench. A high-dielectric constant (high-k) layer is formed on the base and side walls of the trench. The high-k layer has an upper surface conforming to a shape of the trench. A first layer is formed on the high-k layer and conforms to the shape of the trench. The first layer includes an aluminum-free metal nitride. A second layer is formed on the first layer and conforms to the shape of the trench. The second layer includes aluminum and at least one other metal. A third layer is formed on the second layer and conforms to the shape of the trench. The third layer includes aluminum-free metal nitride.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Aritra Dasgupta, Unoh Kwon, Sean M. Polvino
  • Publication number: 20140027783
    Abstract: The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located between the plurality of source and drain regions along a first direction; characterized in that the plurality of gate stack structures enclose the plurality of channel regions. In accordance with the semiconductor device and the method of manufacturing the same of the present invention, an all-around nanowire metal multi-gate is formed in self-alignment by punching through and etching the fins at which the channel regions are located using a combination of the hard mask and the dummy gate, thus the device performance is enhanced.
    Type: Application
    Filed: August 27, 2012
    Publication date: January 30, 2014
    Inventors: Huaxiang Yin, Changliang Qin, Qiuxia Xu, Dapeng Chen
  • Patent number: 8618602
    Abstract: A semiconductor device may include, but is not limited to, a semiconductor substrate, a word line, and an isolation region. The semiconductor substrate has an active region and first and second grooves. Each of the first and second grooves extends across the active region. The first groove is wider in width than the second groove. The word line is disposed in the first groove. The isolation region is disposed in the second groove. The isolation region is narrower in width than the word line.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: December 31, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Kiyonori Oyu
  • Patent number: 8603879
    Abstract: A method for fabricating a super-junction semiconductor power device with reduced Miller capacitance includes the following steps. An N-type substrate is provided and a P-type epitaxial layer is formed on the N-type substrate. At least a trench is formed in the P-type epitaxial layer followed by forming a buffer layer on interior surface in the trench. An N-type dopant layer is filled into the trench and then the N-type dopant layer is etched to form a recessed structure at an upper portion of the trench. A gate oxide layer is formed, and simultaneously, dopants in the N-type dopant layer diffuse into the P-type epitaxial layer, forming an N-type diffusion layer. Finally, a gate conductor is filled into the recessed structure and an N-type source doped region is formed around the gate conductor in the P-type epitaxial layer.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: December 10, 2013
    Assignee: Anpec Electronics Corporation
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Yi-Chun Shih