Abstract: A method for fabricating a lateral gallium nitride (GaN) field-effect transistor includes forming a first and second GaN layer coupled to a substrate, removing a first portion of the second GaN layer to expose a portion of the first GaN layer, and forming a third GaN layer coupled to the second GaN layer and the exposed portion of the first GaN layer. The method also includes removing a portion of the third GaN layer to expose a portion of the second GaN layer, forming a source structure coupled to the third GaN layer. A first portion of the second GaN layer is disposed between the source structure and the second GaN layer. A drain structure is formed that is coupled to the third GaN layer or alternatively to the substrate. The method also includes forming a gate structure coupled to the third GaN layer such that a second portion of the third GaN layer is disposed between the gate structure and the second GaN layer.

Abstract: A semiconductor substructure with improved performance and a method of forming the same is described. In one embodiment, the semiconductor substructure includes a substrate, having an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structures is formed of a strain material and is disposed in an recess that extends below the upper surface of the substrate. An interface between the spacer and the source-drain structure can be at least 2 nm above the upper surface of the substrate.

Abstract: According to one embodiment, a nitride semiconductor device includes a substrate; semiconductor stacked layers including a nitride semiconductor provided on the substrate, and having a buffer layer, a carrier running layer provided on the buffer layer, and a barrier layer provided on the carrier running layer; a source electrode and a drain electrode provided on the semiconductor stacked layers and in contact with the semiconductor stacked layers; and a gate electrode provided on the semiconductor stacked layers and provided between the source electrode and the drain electrode. The gate electrode has a stacked structure, and a gate metal layer, a barrier metal layer, a first interconnection layer, and a second interconnection layer including Al are sequentially stacked from a side of a surface of the semiconductor stacked layers in the stacked structure.

Abstract: A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate; and forming a first gate structure on the semiconductor substrate. The method also includes forming offset spacers doped with a certain type of ions to increase an anti-corrosion ability of the offset spacers on both sides of the first gate structure by a stability doping process; and forming trenches in the semiconductor substrate at both sides of the first gate structures. Further, the method includes forming stress layers in the trenches.

Abstract: A method to grow single phase group III-nitride articles including films, templates, free-standing substrates, and bulk crystals grown in semi-polar and non-polar orientations is disclosed. One or more steps in the growth process includes the use of additional free hydrogen chloride to eliminate undesirable phases, reduce surface roughness, and increase crystalline quality. The invention is particularly well-suited to the production of single crystal (11.2) GaN articles that have particular use in visible light emitting devices.

Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a channel region under the gate dielectric layer; and a source region and a drain region located in the semiconductor substrate and on respective sides of the channel region, wherein at least one of the source and drain regions comprises a set of dislocations that are adjacent to the channel region and arranged in the direction perpendicular to a top surface of the semiconductor substrate, and the set of dislocations comprises at least two dislocations.

Abstract: A method and apparatus are provided for recessing a channel region of the PFET and epitaxially growing channel SiGe in the recessed region inside of a horizontally oriented processing furnace. Embodiments include forming an n-channel region and a p-channel region in a front side of a wafer and at least one additional wafer, the n-channel and p-channel regions corresponding to locations for forming an NFET and a PFET, respectively; placing the wafers inside a horizontally oriented furnace having a top surface and a bottom surface, with the wafers oriented vertically between the top and bottom surfaces; recessing the p-channel regions of the wafers inside the furnace; and epitaxially growing cSiGe without hole defects in the recessed p-channel regions inside the furnace.

Abstract: Approaches for forming a replacement metal gate (RMG) of a semiconductor device, are disclosed. Specifically provided is a p-channel field effect transistor (p-FET) and an n-channel field effect transistor (n-FET) formed over a substrate, the p-FET and the n-FET each having a recess formed therein, a high-k layer and a barrier layer formed within each recess, a work-function metal (WFM) selectively grown within the recess of the n-FET, wherein the high-k layer, barrier layer, and WFM are each recessed to a desired height within the recesses, and a metal material (e.g., Tungsten) formed within each recess. By providing a WFM chamfer earlier in the process, the risk of mask materials filling into each gate recess is reduced. Furthermore, the selective WFM growth improves fill-in of the metal material, which lowers gate resistance in the device.

Abstract: A method of fabricating a semiconductor device structure is provided. The method includes the following step. A gate dielectric layer is formed on a substrate. A gate electrode is on the gate dielectric layer. The gate dielectric layer exposed by the gate electrode is treated. A first etching process is performed to remove at least a portion of the gate dielectric layer exposed by the gate electrode. A spacer is formed on the sidewall of the gate electrode. A second etching process is performed to form recesses in the substrate beside the gate electrode. Besides, during the first etching process and the second etching process, an etching rate of the treated gate dielectric layer is greater than an etching rate of the untreated gate dielectric layer.

Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

Abstract: A substrate is provided with a main surface having an off angle of 5° or smaller relative to a reference plane. The reference plane is a {000-1} plane in the case of hexagonal system and is a {111} plane in the case of cubic system. A silicon carbide layer is epitaxially formed on the main surface of the substrate. The silicon carbide layer is provided with a trench having first and second side walls opposite to each other. Each of the first and second side walls includes a channel region. Further, each of the first and second side walls substantially includes one of a {0-33-8} plane and a {01-1-4} plane in the case of the hexagonal system and substantially includes a {100} plane in the case of the cubic system.

Abstract: The present invention discloses a bipolar transistor with an embedded epitaxial external base region, which is designed to solve the problem of the TED effect with the prior art structures. The bipolar transistor with an embedded epitaxial external base region of the present invention comprises at least a collector region, a base region and an external base region on the collector region, an emitter on the base region, and sidewalls at both sides of the emitter. The external base region is grown through an in-situ doping selective epitaxy process and is embedded in the collector region. A portion of the external base region is located beneath the sidewalls. The present invention discloses a method of forming a bipolar transistor with an embedded epitaxial external base region.

Abstract: A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material is converted into a first silicon oxynitride material by a first plasma nitridation process. A second silicon oxide material is subsequently deposited by a second atomic layer deposition process. The second silicon oxide material is converted into a second silicon oxynitride material by a second plasma nitridation process. Multiple repetitions of the atomic layer deposition process and the plasma nitridation process provides a silicon oxynitride material having a ratio of nitrogen atoms to oxygen atoms greater than 1/3, which can be advantageously employed to reduce the leakage current through a gate dielectric.

Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material having the first lattice constant; a middle portion between the lower portion and upper portion, wherein the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; and a pair of notches extending into opposite sides of the middle portion; and an isolation structure surrounding the fin structure, wherein a top surface of the isolation structure is higher than a top surface of the pair of notches.

Abstract: The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at least one embodiment, the negative differential resistance devices may be formed utilizing quantum wells. Embodiments of negative differential resistance devices of present description may achieve high peak drive current to enable high performance and a high peak-to-valley current ratio to enable low power dissipation and noise margins, which allows for their use in logic and/or memory integrated circuitry.

Abstract: Embodiments of the present invention provide an improved finFET and methods of fabrication. A sigma cavity is used with an n-type finFET to allow multiple epitaxial layers to be disposed adjacent to a finFET gate. In some embodiments, stacking faults may be formed in the epitaxial layers using a stress memorization technique.

Abstract: Embodiments of the present invention provide improved methods for fabricating field effect transistors such as finFETs. Stressor regions are used to increase carrier mobility. However, subsequent processes such as deposition of flowable oxide and annealing can damage the stressor regions, diminishing the amount of stress that is induced. Embodiments of the present invention provide a protective layer of silicon or silicon oxide over the stressor regions prior to the flowable oxide deposition and anneal.

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device are disclosed. In an example, the method includes forming a gate structure over a substrate; forming a doped region in the substrate; performing a first etching process to remove the doped region and form a trench in the substrate; and performing a second etching process that modifies the trench by removing portions of the substrate.

Abstract: Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output.

Abstract: A semiconductor device includes a first superlattice buffer layer formed on a substrate. A second superlattice buffer layer is formed on the first superlattice buffer layer. A first semiconductor layer is formed by a nitride semiconductor on the second superlattice buffer layer. A second semiconductor layer is formed by a nitride semiconductor on the first semiconductor layer. The first superlattice buffer layer is formed by alternately and cyclically laminating a first superlattice formation layer and a second superlattice formation layer. The second superlattice buffer layer is formed by alternately and cyclically laminating the first superlattice formation layer and the second superlattice formation layer. The first superlattice formation layer is formed by AlxGa1-xN, and the second superlattice formation layer is formed by AyGa1-yN, where x>y. A concentration of an impurity element doped into the second superlattice buffer layer is higher than that doped into the first superlattice buffer layer.

Abstract: A method of fabricating a semiconductor device structure is provided. The method includes the following step. A gate dielectric layer is formed on a substrate. A gate electrode is on the gate dielectric layer. The gate dielectric layer exposed by the gate electrode is treated. A first etching process is performed to remove at least a portion of the gate dielectric layer exposed by the gate electrode. A spacer is formed on the sidewall of the gate electrode. A second etching process is performed to form recesses in the substrate beside the gate electrode. Besides, during the first etching process and the second etching process, an etching rate of the treated gate dielectric layer is greater than an etching rate of the untreated gate dielectric layer.

Abstract: In a method, a gate dielectric film is formed on a semiconductor substrate. A gate electrode is formed on the gate dielectric film. Impurities of a first conduction-type are introduced into a drain-layer formation region. The impurities of the first conduction-type in the drain-layer formation region are activated by performing heat treatment. Single crystals of the semiconductor substrate in a source-layer formation region are amorphized by introducing inert impurities into the source-layer formation region. Impurities of a second conduction-type is introduced into the source-layer formation region. At least an amorphous semiconductor in the source-layer formation region is brought into a single crystal semiconductor and the impurities of the second conduction-type in the source-layer formation region is activated by irradiating the semiconductor substrate with microwaves.

Abstract: A semiconductor device includes: a Si substrate having first and second major surfaces facing in opposite directions; a buffer layer of AlxGa1-xN (0?x?1) on the first major surface of the Si substrate; an epitaxially grown crystalline layer of AlyGa1-yN (0?y?1, x?y) on the buffer layer; a transistor on the epitaxially grown crystalline layer; and a filler of AlxGa1-xN and having the same x as the buffer layer. A through hole in the Si substrate extends from the second major surface to the buffer layer, and the through hole is filled with the filler.

Abstract: A semiconductor device of an embodiment includes: an SiC layer; a gate insulating film provided on a surface of the SiC layer, the gate insulating film including an oxide film or an oxynitride film in contact with the surface of the SiC layer, the oxide film or the oxynitride film containing at least one element selected from B, Al, Ga (gallium), In, Sc, Y, La, Mg, Ca, Sr, and Ba, a concentration peak of the element in the gate insulating film being on the SiC side of the gate insulating film, the concentration peak of the element being in the oxide film or the oxynitride film, the gate insulating film having a region with a concentration of the element being not higher than 1×1016 cm?3 on the opposite side to the SiC layer with the concentration peak; and a gate electrode on the gate insulating film.

Abstract: The semiconductor device of this embodiment includes: a first region of a first conductivity type SiC; a second region of a first conductivity type SiC, impurity concentration of first conductivity type of the second region being lower than impurity concentration of first conductivity type of the first region; a third region of a second conductivity type SiC provided between the first region and the second region; a Si layer provided on surfaces of the first, second, and third regions, a thickness of-the Si layer on the third region being thicker than a thickness of the Si layer on the second region; a gate insulating film provided on the Si layer; and a date electrode provided on the gate insulating film.

Abstract: The invention concerns a method for producing a transistor. The gate of the transistor is produced after having produced source and drain electrodes of the transistor. From a substrate having a stack of layers comprising at least two surface layers with a first layer of a first semiconductor material intended to produce a conduction channel of the transistor, and a second layer of a second semiconductor material situated on the first layer and intended to at least partly produce the source and drain electrodes of the transistor, the formation of a mask defining a cavity of a gate pattern and the creation of lateral recesses at the periphery of the gate pattern in the second layer and under the mask by an isotropic etching of the second material, and in that it comprises a filling of the lateral recesses with a dielectric material so as to form gate spacers therein.

Abstract: A method of manufacturing a semiconductor device of an embodiment includes: preparing a substrate; and growing a p-type SiC single-crystal layer on the surface of the substrate from a liquid phase that contains Si (silicon), C (carbon), a p-type impurity, and an n-type impurity, the p-type impurity being an element A, the n-type impurity being an element D, the element A and the element D forming a first combination that is at least one combination selected from Al (aluminum) and N (nitrogen), Ga (gallium) and N (nitrogen), and In (indium) and N (nitrogen), and/or a second combination of B (boron) and P (phosphorus), the ratio of the concentration of the element D to the concentration of the element A in the first or second combination being higher than 0.33 but lower than 1.0.

Abstract: In sophisticated semiconductor devices, high-k metal gate electrode structures may be formed in an early manufacturing stage with superior integrity of sensitive gate materials by providing an additional liner material after the selective deposition of a strain-inducing semiconductor material in selected active regions. Moreover, the dielectric cap materials of the gate electrode structures may be removed on the basis of a process flow that significantly reduces the degree of material erosion in isolation regions and active regions by avoiding the patterning and removal of any sacrificial oxide spacers.

Abstract: A substrate with two SiGe regions having different Germanium concentrations and a method for making the same. The method includes: providing a substrate with at least two active regions; epitaxially depositing a first SiGe layer over each active regions; epitaxially depositing a Silicon layer over each SiGe layer; epitaxially depositing a second SiGe layer over each Silicon layer; forming a hard mask over the second SiGe layer of one of the active regions; removing the epitaxially deposited second SiGe layer of the unmasked active region, removing the hard mask, and thermally mixing the remaining Silicon and SiGe layers of the active regions to form a new SiGe layer with uniform Germanium concentration for each of the active regions, where the new SiGe layer with uniform Germanium concentration of one of the at least two active regions has a different concentration of Germanium than the new SiGe layer with uniform Germanium concentration of the other SiGe layer.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a cavity in a semiconductor region laterally adjacent to a gate electrode structure. An EPI strain-inducing fill is deposited into the cavity. The EPI strain-inducing fill includes a main SiGe layer and a Si cap that overlies the main SiGe layer. The EPI strain-inducing fill is doped with boron and has a first peak boron content in an upper portion of the EPI strain-inducing fill of about 2.5 times or greater than an average boron content in an intermediate portion of the main SiGe layer.

Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to different types of transistors having different channel materials. In one aspect, a method of fabricating a semiconductor device includes providing a substrate comprising a silicon substrate having a main surface oriented in a {100} crystal plane and having a notch oriented in a <100> direction. The method additionally includes forming a plurality of silicon protrusions in a first predetermined region by recessing portions of the main surface surrounding the silicon protrusions. The method additionally includes forming shallow trench isolation (STI) structures adjacent to the silicon protrusions to electrically isolate the silicon protrusions, thereby defining channel areas of a transistor of a first type. The method further includes removing at least upper portions of the silicon protrusions, thereby forming trenches between neighboring STI structures and filling the trenches with a III-V material.

Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm?3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.

Abstract: In a semiconductor device, a first active region has a first ?-shape, and the second active region has a second ?-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

Abstract: According to an embodiment, a semiconductor device includes a first layer including a first nitride semiconductor, a second layer provided on the first layer and including a second nitride semiconductor having a wider bandgap than the first nitride semiconductor. The device also includes a source electrode and a drain electrode provided on the second layer; and a gate electrode provided on the second layer and located between the source electrode and the drain electrode. The second layer includes a first region between the gate electrode and the drain electrode, the first region being selectively provided in a surface of the second layer and contains fluorine. A concentration of fluorine in the first region is higher than a concentration of fluorine in a portion underneath the gate electrode in the second layer.

Abstract: A first AlGaN layer formed over a substrate, a second AlGaN layer formed over the first AlGaN layer, an electron transit layer formed over the second AlGaN layer, and an electron supply layer formed over the electron transit layer are provided. A relationship of “0?x1<x2?1” is found when a composition of the first AlGaN layer is represented by Alx1Ga1-x1N, and a composition of the second AlGaN layer is represented by Alx2Ga1-x2N. Negative charges exist at an upper surface of the AlGaN layer more than positive charges existing at a lower surface of the AlGaN layer.

Abstract: Provided is a field-effect transistor which has a high mobility and a low variation of mobility. A field-effect transistor at least comprising a substrate, a semiconductor layer, a source electrode, and a drain electrode is produced by forming the source electrode and/or the drain electrode so that the source electrode and/or the drain electrode has a taper shape in a cross-section which is parallel with a channel length direction and perpendicular to the substrate, and forming the semiconductor layer through coating process.

Abstract: An enhanced switch device and a manufacturing method therefor. The method comprises: providing a substrate, and forming a nitride transistor structure on the substrate; fabricating and forming a dielectric layer on the nitride transistor structure, on which a gate region is defined; forming a groove structure on the gate region; depositing a p-type semiconductor material in the groove; removing the p-type semiconductor material outside the gate region on the dielectric layer; etching the dielectric layer in another position than the gate region on the dielectric layer to form two ohmic contact regions; and forming a source electrode and a drain electrode on the two ohmic contact regions, respectively.

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a metal contact such as one or more metals/alloys on silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example embodiment, an intermediate tin doped III-V material layer is provided between the source/drain and contact metal to significantly reduce contact resistance. Partial or complete oxidation of the tin doped layer can be used to further improve contact resistance. In some example cases, the tin doped III-V material layer has a semiconducting phase near the substrate and an oxide phase near the metal contact. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs, nanowire transistors, etc), as well as strained and unstrained channel structures.

Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.

Abstract: Design constraints for a self protecting GaN HFET and in general any group III V HFET are described. The design constraints depend on the separation between the gate and the drain and the thickness of the buffer material between the channel layer and the substrate. In one embodiment the buffer region is thinned to provide a preferred breakdown location.

Abstract: A semiconductor device and method of fabricating the semiconductor device are disclosed. The method includes forming a plurality of gates on a surface of a substrate, forming sidewalls on side surfaces of the gates, forming a Sigma-shaped recess in the substrate between adjacent gates, forming a SiGe seed layer on an inner surface of the Sigma-shaped recess, forming bulk SiGe doped with boron on a surface of the SiGe seed layer, and filling the Sigma-shaped recess with the boron-doped bulk SiGe, forming a first recess by etching a portion of the SiGe seed layer and the boron-doped bulk SiGe in the Sigma-shaped recess, and forming a SiGe regeneration layer in the first recess beneath the surface of the substrate, wherein the SiGe regeneration layer is doped with boron, and the boron-doped SiGe regeneration layer has a higher concentration of boron than the SiGe seed layer or the boron-doped bulk SiGe.

Abstract: A semiconductor device having a fin gate that improves an operation current, and a method of manufacturing the same are provided. The semiconductor device includes an active pillar formed on a semiconductor substrate, and including a first region and a second region surrounding at least one surface of the first region, and a fin gate extending to overlap an upper surface and a lateral surface of the active pillar. The first region of the active pillar is formed of a semiconductor layer having a lattice constant smaller than that of the second region of the active pillar.

Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A third silicon germanium region is over the second silicon germanium region, wherein the third silicon germanium region has a third germanium percentage lower than the second germanium percentage.

Abstract: The present invention discloses a strip-shaped gate-modulated tunneling field effect transistor with double-diffusion and a preparation method thereof, belonging to a field of CMOS field effect transistor logic device and the circuit.

Abstract: A semiconductor device having a fin gate that improves an operation current, and a method of manufacturing the same. The semiconductor device includes an active pillar formed on a semiconductor substrate, the active pillar including an inner region and an outer region surrounding the inner region, and a fin gate overlapping an upper surface and a lateral surface of the active pillar. The inner portion of the active pillar includes a first semiconductor layer having a first lattice constant, and the outer region of the active pillar includes a second semiconductor layer having a second lattice constant smaller than the first lattice constant.

Abstract: Embodiments of the present disclosure provide techniques and configurations associated with conversion of thin transistor elements from silicon (Si) to silicon germanium (SiGe). In one embodiment, a method includes providing a semiconductor substrate having a channel body of a transistor device disposed on the semiconductor substrate, the channel body comprising silicon, forming a cladding layer comprising germanium on the channel body, and annealing the channel body to cause the germanium to diffuse into the channel body. Other embodiments may be described and/or claimed.

Abstract: In order to provide a method for producing a SiC-MOSFET capable of increasing Vth without deteriorating channel mobility, before forming a gate insulation film, (a) silicon carbide substrate is oxidized by a low temperature oxidation method represented by plasma oxidation to form a silicon oxide film. Next, (b) the silicon oxide film is removed. After repeating the processes (a) and (b) once or more, (c) the gate insulation film is formed.

Abstract: A method for forming a semiconductor device includes forming a dielectric layer on a first substrate and wafer bonding the dielectric layer of the first substrate to a second substrate including SiC with a passivating layer formed on the SiC. A portion of the first substrate is removed from a side opposite the dielectric layer. The dielectric layer is patterned to form a gate dielectric for a field effect transistor formed on the second substrate.

Abstract: Method for fabricating a transistor comprising the steps consisting of: forming sacrificial zones in a semi-conductor layer, either side of a transistor channel zone, forming insulating spacers on said sacrificial zones against the sides of the gate of said transistor, removing said sacrificial zones so as to form cavities, with the cavities extending on either side of said channel zone and penetrating under said spacers, forming doped semi-conductor material in said cavities, with said semi-conductor material penetrating under said spacers.

Abstract: An electrode comes in ohmic contact with an AlGaN layer. A semiconductor device SD has a nitride semiconductor layer GN2, and an AlxGa(1?x)N layer AGN (hereinafter referred to as “AlGaN layer AGN), and Al electrodes DE, SE. in the AlGaN layer AGN, 0<X?0.2 is satisfied. Also, both of a concentration of a p-type impurity and a concentration of an n-type impurity in the AlGaN layer AGN are 1×1016 cm?3 or lower. In this example, the p-type impurity is exemplified by, for example, Be, C, and Mg, and the n-type impurity is exemplified by Si, S, and Se. Also, the Al electrodes DE and SE are connected to the AlGaN layer AGN. Because a composition ratio of Al is limited to the above-mentioned range, the Al electrodes DE and SE are brought into ohmic contact with the AlGaN layer AGN.