Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopant and a second dopant, and the second dopant comprises a group V material.

Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Abstract: Some embodiments of the present disclosure relates to a method of forming a semiconductor device having a strained channel and an associated device. In some embodiments, the method includes performing a first etching process by selectively exposing a substrate to a first etchant to produce a recess defined by sidewalls and a bottom surface of the substrate. An implantation process is performed to form an etch stop layer along the bottom surface. A second etching process is performed by exposing the sidewalls and the bottom surface defining the recess to a second etchant to form a source/drain recess. The source/drain recess laterally extends past the etch stop layer in opposing directions. A semiconductor material is formed within the source/drain recess.

Abstract: A tensile strained silicon layer and a compressively strained silicon germanium layer are formed on a strain relaxed silicon germanium buffer layer substrate. A relaxed silicon layer is formed on the substrate and the compressively strained silicon germanium layer is formed on the relaxed silicon layer. The compressively strained silicon germanium layer can accordingly have approximately the same concentration of germanium as the underlying strain relaxed buffer layer substrate, which facilitates gate integration. The tensile strained silicon layer and the compressively strained silicon germanium layer can be configured as fins used in the fabrication of FinFET devices. The relaxed silicon layer and a silicon germanium layer underlying the tensile silicon layer can be doped in situ to provide punch through stop regions adjoining the fins.

Abstract: The semiconductor device includes a substrate comprising first and second regions, in the first region, first and second gate electrodes formed parallel to each other on the substrate, and being spaced apart from each other by a first distance, in the second region, third and fourth gate electrodes formed parallel to each other on the substrate, and being spaced apart from each other by a second distance which is greater than the first distance, in the first region, a first recess formed on the substrate between the first and second gate electrodes, in the second region, a second recess formed on the substrate between the third and fourth gate electrodes, a first epitaxial source/drain filling the first recess and a second epitaxial source/drain filling the second recess, wherein an uppermost portion of an upper surface of the first epitaxial source/drain is higher than an uppermost portion of an upper surface of the second epitaxial source/drain.

Abstract: A method of forming a semiconductor structure includes forming a dummy gate above a semiconductor substrate. The dummy gate defines a source-drain region adjacent to the dummy gate and a channel region below the dummy gate. A silicon-germanium layer is epitaxially grown above the source-drain region with a target concentration of germanium atoms. The semiconductor structure is annealed to diffuse the germanium atoms from the silicon-germanium layer into the channel region to form a silicon-germanium channel region.

Abstract: An embodiment of a silicon carbide semiconductor device includes one or more inner cells each having a MOSFET and one or more outer peripheral cells that does not have a MOSFET structure, and the area (surface area) of the p+ contact region of each of the outermost peripheral cells is less than the surface area of an p+ contact region of each of the inner cells, for example, so that a unit total resistance of p+ contact regions of the outermost peripheral cells, as measured in a depth direction of the semiconductor substrate with respect to a unit area in a surface of the semiconductor substrate, is greater than a unit total resistance of the p+ contact regions of the inner cells, as measured in the depth direction of the semiconductor substrate with respect to the unit area in the surface of the semiconductor substrate.

Abstract: A method includes forming a gate electrode structure above a channel region defined in a semiconductor material. The semiconductor material is recessed in a source/drain region. A first material is epitaxially grown in the source/drain region. The first material includes a dopant species having a first concentration. A diffusion blocking layer is formed in the source/drain region above the first material. A second material is epitaxially grown in the source/drain region above the diffusion blocking layer. The second material comprises the dopant species having a second concentration greater than the first concentration.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a gate dielectric over the semiconductor wafer, and forming a gate over the gate dielectric. At least one recess is formed in the semiconductor wafer proximate the gate and the gate dielectric, at least a portion of the at least one recess extending beneath the gate. The at least one recess in the semiconductor wafer is filled with a semiconductive material.

Abstract: A control wafer making device, a method of measuring an epitaxy thickness in a control wafer, and a method for monitoring a control wafer are provided. In various embodiments, the control wafer making device includes a wafer substrate removing element and an epitaxy forming element. In various embodiments, a control wafer includes a substrate, a recess, a blocking layer, and an epitaxy. The substrate has a surface, and the recess is in the surface of the substrate. The blocking layer is over the surface of the substrate other than the recess. The epitaxy is in the recess. In various embodiments, the thickness of the epitaxy of the control wafer is measured by a polarized light.

Abstract: The present invention provides a method of manufacturing a fin field effect transistor, comprising: providing an SOI substrate comprising a substrate layer (100), a BOX layer (120) and an SOI layer (130); forming a basic fin structure from an SOI layer; forming source/drain regions (110) on both sides of the basic fin structure; forming a fin structure between the source/drain regions (110) from a basic fin structure; and forming a gate stack across the fin structure. The method of manufacturing a fin field effect transistor provided in the present invention can integrate a high-k gate dielectric layer, a metal gate, and stressed source/drain regions into the fin field effect transistor to enhance the performance of the semiconductor device.

Abstract: A process of forming a nitride semiconductor device is disclosed. The process includes steps of (a) implanting impurities into a portion of nitride semiconductor layers epitaxially grown on a substrate; (b) forming a silicon nitride (SiN) film on the nitride semiconductor layers; and (c) annealing the nitride semiconductor layers for activating the implanted impurities as covering the nitride semiconductor layers by the SiN film. The process has a feature that the SiN film shows, in a Fourier Transformation Infrared (FT-IR) spectroscopy measured before the step of annealing, absorbance peaks attributed to translational motions of a Si—H bond and an N—H bond at most 1/30 of an absorbance peak attributed to a SiN bond.

Abstract: A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins.

Abstract: An optoelectronic light emission device is provided that includes a gain region of at least one type III-V semiconductor layer that is present on a lattice mismatched semiconductor substrate. The gain region of the type III-V semiconductor layer has a nanoscale area using nano-cavities. The optoelectronic light emission device is free of defects.

Abstract: Semiconductor structures and methods of fabrication are provided, with one or both of an extended source-to-channel interface or an extended drain-to-channel interface. The fabrication method includes, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of a semiconductor structure being fabricated, the recessing forming a first cavity surface and a second cavity surface within the cavity; and implanting one or more dopants into the semiconductor material through the first cavity surface to define an implanted region within the semiconductor material, and form an extended channel interface, the extended channel interface including, in part, an interface of the implanted region within the semiconductor material to the channel region of the semiconductor structure. In one embodiment, the semiconductor structure with the extended channel interface is a FinFET.

Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

Abstract: According to example embodiments, an electronic device includes a substrate, an insulating layer on the substrate, and a diode layer on the insulating layer. The diode layer includes a two dimensional (2D) material layer. The 2D material layer includes an N-type region and a P-type region. According to example embodiments, a method of manufacturing an electronic device includes forming an insulating film on a substrate, forming a 2D material layer on the insulating film, and dividing the 2D material layer into an N-type region and a P-type region.

Abstract: A method of forming a semiconductor structure includes forming a dummy gate above a semiconductor substrate. The dummy gate defines a source-drain region adjacent to the dummy gate and a channel region below the dummy gate. A silicon-germanium layer is epitaxially grown above the source-drain region with a target concentration of germanium atoms. The semiconductor structure is annealed to diffuse the germanium atoms from the silicon-germanium layer into the channel region to form a silicon-germanium channel region.

Abstract: A structure including a first semiconductor material portion and a second semiconductor material portion is provided. An oxygen impermeable hard mask is then formed directly on a surface of the first semiconductor material portion. Next, a silicon germanium layer is epitaxially formed on the second semiconductor material portion, but not the first semiconductor material portion. An oxygen permeable hard mask is then formed over the first and second semiconductor material portions. A thermal condensation process is then performed which converts the second semiconductor material portion into a germanium-containing semiconductor material portion. The oxygen permeable hard mask and the oxygen impermeable hard mask are then removed. A functional gate structure can be formed atop the remaining first semiconductor material portion and the thus formed germanium-containing semiconductor material portion.

Abstract: A lateral bipolar junction transistor is fabricated using a semiconductor-on-insulator substrate. The transistor includes a germanium gradient within a doped silicon base region, there being an increasing germanium content in the direction of the collector region of the transistor. The use of a substrate including parallel silicon fins to fabricate lateral bipolar junction transistors facilitates the inclusion of both CMOS FinFET devices and lateral bipolar junction transistors having graded silicon germanium base regions on the same chip.

Abstract: A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is smaller than the first band gap. The HEMT further includes a third III-V compound layer having a third band gap over the second III-V compound layer, wherein the third band gap is greater than the first band gap. A gate electrode is formed over the third III-V compound layer. A source region and a drain region are over the third III-V compound layer and on opposite sides of the gate electrode.

Abstract: Methods for manufacturing a semiconductor device including a field effect transistor include forming first fins protruding from a substrate including a first region and a second region, the first fins including silicon-germanium (SiGe), forming a first mask pattern to expose the first fins disposed in the second region, the first mask pattern covering the first fins disposed in the first region, oxidizing the first fins in the second region to form second fins in the second region, and forming germanium (Ge)-rich layers each disposed on a surface of a respective one of the second fins.

Abstract: The disclosed technology generally relates to complementary metal-oxide-silicon (CMOS) devices, and more particularly to an n-channel metal-oxide-silicon (nMOS) device and a p-channel metal-oxide-silicon (pMOS) device that are under different types of strains. In one aspect, a method comprises providing trenches in a dielectric layer on a semiconductor substrate, where at least a first trench defines an nMOS region and a second trench defines a pMOS region, and where the trenches extend through the dielectric layer and abut a surface of the substrate. The method additionally includes growing a first seed layer in the first trench on the surface and growing a common strain-relaxed buffer layer in the first trench and the second trench, where the common strain-relaxed buffer layer comprises silicon germanium (SiGe). The method further includes growing a common channel layer comprising germanium (Ge) in the first and second trenches and on the common strain-relaxed buffer layer.

Abstract: A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin. The first gate is disposed over the first fin. The second gate is disposed over the second fin. A gap is formed between the first gate and the second gate, and the gap gets wider toward the substrate. The insulating structure is disposed in the gap. The insulating structure has a top surface and a bottom surface opposite to each other. The bottom surface faces the substrate. An edge of the top surface facing the first gate is curved inward the top surface.

Abstract: The present invention provides a manufacturing method of a fin-shaped field effect transistor (FinFET), comprises the following steps. Firstly, providing a substrate having a fin structure; forming a gate structure on the fin structure perpendicular to a extending direction of the fin structure; performing an amorphous implantation to form an amorphous layer on a exposed portion of the fin structure exposed by the gate structure and a light-doping implantation; forming a sacrificial spacer on sides of the gate structure covering a portion of the amorphous layer on the fin structure; forming a trench on the fin structure adjacent to the sacrificial spacer; growing an alloy in the trench; and then removing the sacrificial spacer. The invention also provides a FinFET device thereof.

Abstract: A method for producing a multi-gate fin field-effect transistor (FinFET) is provided. The method includes forming a channel layer and a gate medium layer on a substrate; forming an amorphous silicon layer on the substrate, and etching the amorphous silicon layer, to form at least one fin; forming, by using an epitaxial growth process, a first protective layer from both sides to the middle of the substrate along a length direction of the at least one fin until a groove is formed in a middle location along the length direction of the at least one fin; forming a gate electrode layer on the substrate, performing planarization processing on the gate electrode layer to expose the first protective layer, and etching away the first protective layer by using an etching process, so as to form a gate electrode; and forming a source electrode and a drain electrode on the substrate.

Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.

Abstract: Methods for forming a HEMT device are provided. The method includes forming an ultra-thin barrier layer on the plurality of thin film layers. A dielectric thin film layer is formed over a portion of the ultra-thin barrier layer to leave exposed areas of the ultra-thin barrier layer. A SAG S-D thin film layer is formed over the exposed areas of the ultra-thin barrier layer while leaving the dielectric thin film layer exposed. The dielectric thin film layer is then removed to expose the underlying ultra-thin barrier layer. The underlying ultra-thin barrier layer is treating with fluorine to form a treated area. A source and drain is added on the SAG S-D thin film layer, and a dielectric coating is deposited over the ultra-thin barrier layer treated with fluorine such that the dielectric coating is positioned between the source and the drain.

Abstract: Metal semiconductor alloy contacts are provided on each of a source region and a drain region which are present in a semiconductor substrate. A transition metal is then deposited on each of the metal semiconductor alloy contacts, and during the deposition of the transition metal, the deposited transition metal reacts preferably, but not necessarily always, in-situ with a portion of each the metal semiconductor alloy contacts forming a transition metal-metal semiconductor alloy liner atop each metal semiconductor alloy contact. Each transition metal-metal semiconductor alloy liner that is provided has outer edges that are vertically coincident with outer edges of each metal semiconductor alloy contact. The transition metal-metal semiconductor alloy liner is more etch resistant as compared to the underlying metal semiconductor alloy. As such, the transition metal-metal semiconductor alloy liner can serve as an effective etch stop layer during any subsequently performed etch process.

Abstract: The invention relates to a method by means of which the average single crystal size, in particular the diameter of the single crystals, in a semiconductor thin film applied to a foreign substrate can be increased by an order of magnitude with respect to prior methods. The method is characterized in that a thin semiconductor film is applied to the foreign substrate in a first step. Then the foreign substrate is heated to such an extent that the semiconductor thin film melts. Then the temperature is slowly decreased to below the melting temperature of the semiconductor material. During the cooling process, the foreign substrate is heated in such a way that, proceeding from the surface of the foreign substrate, the temperature continuously decreases in a vertical direction perpendicular through the semiconductor thin film to the surface of the thin film.

Abstract: The present disclosure provides devices and methods which provide for strained epitaxial regions. A method of semiconductor fabrication is provided that includes forming a gate structure over a fin of a semiconductor substrate and forming a recess in the fin adjacent the gate structure. A sidewall of the recess is then altered. Exemplary alterations include having an altered profile, treating the sidewall, and forming a layer on the sidewall. An epitaxial region is then grown in the recess. The epitaxial region interfaces the altered sidewall of the recess and is a strained epitaxial region.

Abstract: A method of manufacturing a semiconductor device having a doped layer may be provided. The method includes providing a substrate having a first region and a second region, forming a gate dielectric layer on the substrate, forming a first gate electrode layer on the gate dielectric layer, forming a first doped layer on the first gate electrode layer, forming a first capping layer on the first doped layer, forming a mask pattern on the first capping layer in the first region, the mask pattern exposing the first capping layer in the second region, removing the first capping layer and the first doped layer in the second region, removing the mask pattern, and forming a second doped layer on the first capping layer in the first region and the first gate electrode layer in the second region.

Abstract: III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

Abstract: In various aspects, methods of forming a semiconductor device and semiconductor devices are provided. In some illustrative embodiments herein, a silicon/germanium layer is provided on a semiconductor substrate. On the silicon/germanium layer, at least one insulating material layer is formed. After having performed a thermal annealing process, the at least one insulating material layer is removed in subsequent process sequences such that the silicon/germanium layer is at least partially exposed. In further processing sequences which are to be subsequently applied, a gate electrode is formed on the exposed silicon/germanium layer.

Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

Abstract: Several embodiments of a tunneling transistor are disclosed. In one embodiment, a tunneling transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a gate stack including a metallic gate electrode and a gate dielectric, and a tunneling junction that is substantially parallel to an interface between the metallic gate electrode and the gate dielectric. As a result of the tunneling junction that is substantially parallel with the interface between the metallic gate electrode and the gate dielectric, an on-current of the tunneling transistor is substantially improved as compared to that of a conventional tunneling transistor. In another embodiment, a tunneling transistor includes a heterostructure that reduces a turn-on voltage of the tunneling transistor.

Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

Abstract: A method of forming a stacked low temperature transistor and related devices. At least some of the illustrative embodiments are methods comprising forming at least one integrated circuit device on a front surface of a bulk semiconductor substrate, and depositing an inter-layer dielectric on the at least one integrated circuit device. A semiconductor layer may then be deposited on the inter-layer dielectric. In some embodiments, a transistor is formed within the semiconductor layer. In some examples, the transistor includes a gate structure formed over the semiconductor layer as well as source/drain regions formed within the semiconductor layer disposed adjacent to and on either side of the gate structure. A metal layer may then be deposited over the transistor, after which an annealing process is performed to induce a reaction between the source/drain regions and the metal layer.

Abstract: A method for fabricating a semiconductor device is provided. A first gate pattern and a second gate pattern are adjacent to each other and are formed on an active region of a substrate. The active region is defined by an isolation film. A first recess is formed between the first gate pattern and the second gate pattern. A first sacrificial film pattern is formed on a bottom surface of the first recess using a directional deposition process. A second recess is formed by etching the first recess using the first sacrificial film pattern as a etch mask. The first recess is laterally extended to form the second recess.

Abstract: A semiconductor structure includes a substrate, a nucleation layer on the substrate, a compositionally graded layer on the nucleation layer, and a layer of a nitride semiconductor material on the compositionally graded layer. The layer of nitride semiconductor material includes a plurality of substantially relaxed nitride interlayers spaced apart within the layer of nitride semiconductor material. The substantially relaxed nitride interlayers include aluminum and gallium and are conductively doped with an n-type dopant, and the layer of nitride semiconductor material including the plurality of nitride interlayers has a total thickness of at least about 2.0 ?m.

Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

Abstract: The invention relates to a field-effect transistor and a method for its manufacturing having at least one layer, said layer comprising a III-V compound semiconductor, wherein the compound semiconductor comprises at least one element from the chemical group III being selected from any of gallium, aluminium, indium and/or boron and wherein the compound semiconductor comprises at least one element from the chemical group V being selected from nitrogen, phosphorous and/or arsenic, wherein the compound semiconductor comprises at least nitrogen, wherein the field-effect transistor comprises at least any of a source electrode and/or a drain electrode, said source electrode and/or drain electrode comprising at least one doped region extending from the surface into the at least one layer, wherein the depth of penetration of said doped region is selected from approximately 10 nm to approximately 200 nm.

Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.

Abstract: A structure and method for fabricating a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) with self-aligned and overlapped extensions using a replacement gate process is disclosed. The a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) structure may be formed by forming a III-V compound semiconductor-containing heterostructure having multiple layers and a T-shaped gate structure using a gate replacement process. The T-shaped gate structure may be formed with a bottom surface substantially below an upper surface of the III-V compound semiconductor-containing heterostructure and an upper surface above the III-V compound semiconductor-containing heterostructure. An undoped region may be formed below the bottom surface of the T-shaped gate structure on a layer of the III-V compound semiconductor-containing heterostructure.

Abstract: A structure and method for fabricating a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) with self-aligned and overlapped extensions using a gate last process is disclosed. The a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) structure may be formed by forming a III-V compound semiconductor-containing heterostructure having at least one layer; forming a doped contact layer on the III-V compound semiconductor-containing heterostructure; and forming a gate structure having a bottom surface substantially below an upper surface of the III-V compound semiconductor-containing heterostructure and an upper surface above the doped contact layer. An undoped region may be formed below the bottom surface of the T-shaped gate structure on a layer of the III-V compound semiconductor-containing heterostructure.

Abstract: The invention provides an ultra-low-on-resistance, excellent-reliability semiconductor device that can finely be processed using SiC and a semiconductor device producing method.

Abstract: Embodiments that relate to mechanisms for providing a stable dislocation profile are provided. A semiconductor substrate having a gate stack is provided. An opening is formed adjacent to a side of the gate stack. A first part of an epitaxial growth structure is formed in the opening. A second part of the epitaxial growth structure is formed in the opening. The first part and the second part of the epitaxial growth structure are formed along different directions.

Abstract: A field effect transistor is provided. The field effect transistor includes a semiconductor region formed on a substrate, wherein the semiconductor region comprises an undoped channel region, a source region including a first dopant type, and a drain region including a second dopant type, and wherein the channel region is formed of a group III-V compound semiconductor material. The field effect transistor further includes a high-K gate formed on the channel region, wherein the high-K gate is configured to generate electron tunneling between the source region and the drain region when a gate voltage is applied, and wherein a first contact surface between the source region and the channel region and a second contact surface between the drain region and the channel region are inclined.

Abstract: A method for fabricating a lateral gallium nitride (GaN) field-effect transistor includes forming a first and second GaN layer coupled to a substrate, removing a first portion of the second GaN layer to expose a portion of the first GaN layer, and forming a third GaN layer coupled to the second GaN layer and the exposed portion of the first GaN layer. The method also includes removing a portion of the third GaN layer to expose a portion of the second GaN layer, forming a source structure coupled to the third GaN layer. A first portion of the second GaN layer is disposed between the source structure and the second GaN layer. A drain structure is formed that is coupled to the third GaN layer or alternatively to the substrate. The method also includes forming a gate structure coupled to the third GaN layer such that a second portion of the third GaN layer is disposed between the gate structure and the second GaN layer.