Gate Insulator Structure Constructed Of Diverse Dielectrics (e.g., Mnos, Etc.) Or Of Nonsilicon Compound Patents (Class 438/287)
  • Publication number: 20150072497
    Abstract: A semiconductor device includes a semiconductor substrate, an ONO (oxide/nitride/oxide) film provided on the semiconductor substrate, a control gate provided on the ONO film, a first low-resistance layer, and a second low-resistance layer in contact with the first low-resistance layer, the second low-resistance layer having a sheet resistance lower than the first low-resistance layer. With this configuration, it is possible to downsize the memory cell and provide a fabrication method of the semiconductor device in which the peripheral circuit can be fabricated with simple fabrication processes.
    Type: Application
    Filed: November 13, 2014
    Publication date: March 12, 2015
    Inventors: Hiroaki KOUKETSU, Masaya HOSAKA
  • Patent number: 8975143
    Abstract: Fluorine is located in selective portions of a gate oxide to adjust characteristics of the gate oxide. In some embodiments, the fluorine promotes oxidation which increases the thickness of the selective portion of the gate oxide. In some embodiments, the fluorine lowers the dielectric constant of the oxide at the selective portion. In some examples, having fluorine at selective portions of a select gate oxide of a non volatile memory may reduce program disturb of the memory.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: March 10, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Byoung W. Min
  • Publication number: 20150060991
    Abstract: The performance of a semiconductor device having a memory element is improved. An insulating film, which is a gate insulating film for a memory element, is formed on a semiconductor substrate, and a gate electrode for the memory element is formed on the insulating film. The insulating film has a first insulating film, a second insulating film thereon, and a third insulating film thereon. The second insulating film is a high-dielectric constant insulator film having a charge accumulating function and contains hafnium, silicon, and oxygen. Each of the first insulating film and the third insulating film has a band gap larger than the band gap of the second insulating film.
    Type: Application
    Filed: August 27, 2014
    Publication date: March 5, 2015
    Inventors: Masaharu Mizutani, Masao Inoue, Hiroshi Umeda, Masaru Kadoshima
  • Patent number: 8969162
    Abstract: Provided is a three-dimensional semiconductor device and method for fabricating the same. The device includes a first electrode structure and a second electrode structure stacked sequentially on a substrate. The first and second electrode structures include stacked first electrodes and stacked second electrodes, respectively. Each of the first and second electrodes includes a horizontal portion parallel with the substrate and an extension portion extending from the horizontal portion along a direction penetrating an upper surface of the substrate. Here, the substrate may be closer to top surfaces of the extension portions of the first electrodes than to the horizontal portion of at least one of the second electrodes.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Hwang, Hansoo Kim, Wonseok Cho, Jaehoon Jang
  • Publication number: 20150054073
    Abstract: Semiconductor devices and methods for manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask; removing a portion of the second shielding layer which is next to the other of the source and drain regions; forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer; and forming a stressed interlayer dielectric layer on the substrate.
    Type: Application
    Filed: November 26, 2012
    Publication date: February 26, 2015
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Qingqing Liang, Huicai Zhong
  • Publication number: 20150054074
    Abstract: Semiconductor devices and methods of manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate; forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and removing the first shielding layer; forming a shielding spacer on a sidewall of the second shielding layer; forming the other of the source and drain regions with the second shielding layer and the shielding spacer as a mask; removing at least a portion of the shielding spacer; and forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of the second shielding layer or a possible remaining portion of the shielding spacer.
    Type: Application
    Filed: October 8, 2012
    Publication date: February 26, 2015
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Qingqing Liang, Huicai Zhong
  • Publication number: 20150053930
    Abstract: Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance. A work function semiconductor material such as a silver bromide or a lanthanum oxide is deposited so as to include clusters of different sizes such as dimers, trimers, and tetramers, formed from isolated monomers. A type of Atomic Layer Deposition system is used to deposit on semiconductor wafers molecular clusters to form thin film junctions having selected energy gaps. A beam of ions contains different ionic clusters which are then selected for deposition by passing the beam through a filter in which different apertures select clusters based on size and orientation.
    Type: Application
    Filed: August 20, 2014
    Publication date: February 26, 2015
    Inventor: John H. Zhang
  • Publication number: 20150056775
    Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a gate structure, performing a first oxidation process to form a first SiO layer at least covering a bottom corner of the conductive layer, performing a first etching process to remove the first SiO layer and a portion of the dielectric layer to form a cavity, performing a second oxidation process to form a second SiO layer covering sidewalls of the cavity and a third SiO layer covering a surface of the substrate, forming a first SiN layer filling in the cavity and covering the gate structure on the substrate, and removing a portion of the first SiN layer to form a SiN structure including a foot portion filling in the cavity and an erection portion upwardly extended from the foot portion, and the erection portion covering sidewalls of the gate structure.
    Type: Application
    Filed: October 3, 2014
    Publication date: February 26, 2015
    Inventors: Ya-Huei Huang, Shen-De Wang, Wen-Chung Chang, Feng-Ji Tsai, Chien-Hung Chen
  • Patent number: 8962432
    Abstract: A method for forming semiconductor devices using damascene techniques provides self-aligned conductive lines that have an end-to-end spacing less than 60 nm without shorting. The method includes using at least one sacrificial hardmask layer to produce a mandrel and forming a void in the mandrel. The sacrificial hardmask layers are formed over a base material which is advantageously an insulating material. Another hardmask layer is also disposed over the base material and under the mandrel in some embodiments. Spacer material is formed alongside the mandrel and filling the void. The spacer material serves as a mask and at least one etching procedure is carried out to translate the pattern of the spacer material into the base material. The patterned base material includes trenches and raised portions. Conductive features are formed in the trenches using damascene techniques.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ying Lee, Jyu-Horng Shieh
  • Patent number: 8957472
    Abstract: A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: February 17, 2015
    Assignee: Spansion LLC
    Inventors: Ashot Melik-Martirosian, Mark T. Ramsbey, Mark W. Randolph
  • Patent number: 8956941
    Abstract: To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability. First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: February 17, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Eiji Tsukuda, Kozo Katayama, Kenichiro Sonoda, Tatsuya Kunikiyo
  • Publication number: 20150044839
    Abstract: A photoresist stripping and cleaning composition free from N-alkylpyrrolidones and added quaternary ammonium hydroxides comprising a component (A) which comprises the polar organic solvents N-methylimidazole, dimethylsulfoxide and 1-aminopropane-2-ol.
    Type: Application
    Filed: March 18, 2013
    Publication date: February 12, 2015
    Applicant: BASF SE
    Inventors: Simon Braun, Christian Bittner, Andreas Klipp
  • Publication number: 20150041925
    Abstract: Provided are P type MOSFETs and methods for manufacturing the same. The method may include forming source/drain regions in a semiconductor substrate; forming an interfacial oxide layer on the semiconductor substrate; forming a high K gate dielectric layer on the interfacial oxide layer; forming a first metal gate layer on the high K gate dielectric layer; implanting dopants into the first metal gate layer through conformal doping; and performing annealing to change an effective work function of a gate stack including the first metal gate layer, the high K gate dielectric, and the interfacial oxide layer.
    Type: Application
    Filed: December 7, 2012
    Publication date: February 12, 2015
    Inventors: Huilong Zhu, Qiuxia Xu, Yanbo Zhang, Hong Yang
  • Patent number: 8952462
    Abstract: The present disclosure provides an apparatus that includes a semiconductor device. The semiconductor device includes a substrate. The semiconductor device also includes a first gate dielectric layer that is disposed over the substrate. The first gate dielectric layer includes a first material. The first gate dielectric layer has a first thickness that is less than a threshold thickness at which a portion of the first material of the first gate dielectric layer begins to crystallize. The semiconductor device also includes a second gate dielectric layer that is disposed over the first gate dielectric layer. The second gate dielectric layer includes a second material that is different from the first material. The second gate dielectric layer has a second thickness that is less than a threshold thickness at which a portion of the second material of the second gate dielectric layer begins to crystallize.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Hao Chen, Da-Yuan Lee, Kuang-Yuan Hsu
  • Publication number: 20150037958
    Abstract: A semiconductor device includes a region in a semiconductor substrate having a top surface with a first charge storage layer on the top surface. A first conductive line is on the first charge storage layer. A second charge storage layer is on the top surface. A second conductive line is on the second charge storage layer. A third charge storage layer is on the top surface. A third conductive line is on the third charge storage layer. A fourth charge storage layer has a first side adjoining a first sidewall of the first conductive line and a second side adjoining a first sidewall of the second conductive line. A fifth charge storage layer has a first side adjoining a second sidewall of the second conductive line and a second side adjoining a first sidewall of the third conductive line. Source and drain regions are formed in the substrate on either side of the semiconductor device.
    Type: Application
    Filed: October 17, 2014
    Publication date: February 5, 2015
    Inventors: MARK D. HALL, MEHUL D. SHROFF
  • Patent number: 8946007
    Abstract: After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a semiconductor-on-insulator (SOI) substrate. The source trench and the drain trench are filled with at least a second semiconductor material that is different from the first semiconductor material to form source and drain regions. A planarized dielectric layer is formed and a handle substrate is attached over the source and drain regions. The bottom semiconductor layer is removed selective to the second semiconductor material, the buried insulator layer, and a shallow trench isolation structure. The removal of the bottom semiconductor layer exposes a horizontal surface of the buried insulator layer present between source and drain regions on which a conductive material layer is formed as a back gate electrode.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Kangguo Cheng, Ali Khakifirooz, Douglas C. La Tulipe, Jr.
  • Patent number: 8941118
    Abstract: A III-nitride transistor includes a III-nitride channel layer, a barrier layer over the channel layer, the barrier layer having a thickness of 1 to 10 nanometers, a dielectric layer on top of the barrier layer, a source electrode contacting the channel layer, a drain electrode contacting the channel layer, a gate trench extending through the dielectric layer and barrier layer and having a bottom located within the channel layer, a gate insulator lining the gate trench and extending over the dielectric layer, and a gate electrode in the gate trench and extending partially toward the source and the drain electrodes to form an integrated gate field-plate, wherein a distance between an interface of the channel layer and the barrier layer and the bottom of the gate trench is greater than 0 nm and less than or equal to 5 nm.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: January 27, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Rongming Chu, David F. Brown, Adam J. Williams
  • Patent number: 8932923
    Abstract: A gate structure of a semiconductor device having a NFET and a PFET, includes a lower layer of a hafnium-based dielectric over the gates of the NFET and PFET, and an upper layer of a lanthanide dielectric. The dielectrics are annealed to mix them above the NFET resulting in a lowered work function, and corresponding threshold voltage reduction. An annealed, relatively thick titanium nitride cap over the mixed dielectric above the NFET gate also lowers the work function and threshold voltage. Above the TiN cap and the hafnium-based dielectric over the PFET gate, is another layer of titanium nitride that has not been annealed. A conducting layer of tungsten covers the structure.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: January 13, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hoon Kim, Kisik Choi
  • Patent number: 8932915
    Abstract: A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: January 13, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masumi Saitoh, Toshinori Numata, Yukio Nakabayashi
  • Patent number: 8932929
    Abstract: The invention relates to a thin film transistor memory and its fabricating method. This memory using the substrate as the gate electrode from bottom to up includes a charge blocking layer, a charge storage layer, a charge tunneling layer, an active region of the device and source/drain electrodes. The charge blocking layer is the ALD grown Al2O3 film. The charge storage layer is the two layer metal nanocrystals which include the first layer metal nanocrystals, the insulating layer and the second layer metal nanocrystals grown by ALD method in sequence from bottom to up. The charge tunneling layer is the symmetrical stack layer which includes the SiO2/HfO2/SiO2 or Al2O3/HfO2/Al2O3 film grown by ALD method in sequence from bottom to up. The active region of the device is the IGZO film grown by the RF sputtering method, and it is formed by the standard lithography and wet etch method.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: January 13, 2015
    Assignee: Fudan University
    Inventors: Shijin Ding, Sun Chen, Xingmei Cui, Pengfei Wang, Wei Zhang
  • Publication number: 20150008501
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a stacked layer structure including first to n-th semiconductor layers (n is a natural number equal to or larger than 2) stacked in a first direction which is perpendicular to a surface of a semiconductor substrate, and an upper insulating layer stacked on the n-th semiconductor layer, the stacked layer structure extending in a second direction which is parallel to the surface of the semiconductor substrate, and first to n-th NAND strings provided on surfaces of the first to n-th semiconductor layers in a third direction which is perpendicular to the first and second directions respectively.
    Type: Application
    Filed: July 2, 2014
    Publication date: January 8, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kiwamu SAKUMA, Masahiro KIYOTOSHI
  • Publication number: 20150008537
    Abstract: An N-type MOSFET and a method for manufacturing the same are disclosed. In one aspect, the method comprises forming source/drain regions in a semiconductor substrate. The method also includes forming an interfacial oxide layer on the semiconductor substrate. The method also includes forming a high-k gate dielectric layer on the interfacial oxide layer. The method also includes forming a first metal gate layer on the high-k gate dielectric layer. The method also includes implanting dopants into the first metal gate layer through conformal doping. The method also includes annealing a gate stack to change an effective work function of the gate stack which includes the first metal gate layer, the high-k gate dielectric, and the interfacial oxide layer.
    Type: Application
    Filed: September 23, 2014
    Publication date: January 8, 2015
    Inventors: Huilong Zhu, Qiuxia Xu, Yanbo Zhang, Hong Yang
  • Publication number: 20150008504
    Abstract: A non-volatile memory structure includes a substrate, a gate electrode formed on the substrate, conductive spacers respectively formed on two sides of the gate electrode, and an oxide-nitride-oxide (ONO) structure having an inverted T shape formed on the substrate. The gate electrode includes a gate conductive layer and a gate dielectric layer. The ONO structure includes a base portion and a body portion. The base portion of the ONO structure is sandwiched between the gate electrode and the substrate, and between the conductive spacer and the substrate. The body portion of the T-shaped ONO structure is upwardly extended from the base portion and sandwiched between the gate electrode and the conductive spacer.
    Type: Application
    Filed: July 5, 2013
    Publication date: January 8, 2015
    Inventors: Chun-Lung Chang, Tzu-Ping Chen, Chih-Haw Lee, Kuan-Yi Tseng, Chih-Jung Chen, Chien-Hung Chen
  • Patent number: 8927409
    Abstract: An apparatus includes a wafer annealing tool and a plurality of electrodes coupled to the wafer annealing tool, wherein the electrodes are configured to be in physical contact with a wafer so that, when the wafer is annealed, a negative electrical bias is formed across one or more gate stacks of the wafer.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventor: Martin M. Frank
  • Patent number: 8927372
    Abstract: A semiconductor device may include a first insulating layer disposed on a substrate, a gate electrode disposed on the first insulating layer, and a second insulating layer disposed on the gate electrode and the first insulating layer. The second insulating layer includes a first discharge site.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: January 6, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongkuk Jeong, Seung Ho Chae, Jung Shik Heo
  • Publication number: 20150001610
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit having a split-gate nonvolatile memory device includes forming a charge storage structure overlying a semiconductor substrate and having a first sidewall and a second sidewall and forming an interior cavity. The method forms a control gate in the interior cavity. Further, the method forms a first select gate overlying the semiconductor substrate and adjacent the first sidewall. A first memory cell is formed by the control gate and the first select gate. The method also forms a second select gate overlying the semiconductor substrate and adjacent the second sidewall. A second memory cell is formed by the control gate and the second select gate.
    Type: Application
    Filed: June 27, 2013
    Publication date: January 1, 2015
    Inventors: Zufa Zhang, Khee Yong Lim, Elgin Quek
  • Publication number: 20150004763
    Abstract: A memory device includes an array of NAND strings of memory cells. The device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips. The device includes charge storage structures in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate planes in the stacks and inter-stack semiconductor body elements of a plurality of bit line structures. At least one reference line structure is arranged orthogonally over the stacks, including vertical conductive elements between the stacks in electrical communication with a reference conductor between the bottom plane of conductive strips and a substrate, and linking elements over the stacks connecting the vertical conductive elements. The vertical conductive elements have a higher conductivity than the semiconductor body elements.
    Type: Application
    Filed: September 15, 2014
    Publication date: January 1, 2015
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: HANG-TING LUE
  • Patent number: 8921238
    Abstract: A method for processing a high-k dielectric layer includes the following steps. A semiconductor substrate is provided, and a high-k dielectric layer is formed thereon. The high-k dielectric layer has a crystalline temperature. Subsequently, a first annealing process is performed, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature. A second annealing process is performed, and a process temperature of the second annealing process is substantially larger than the crystalline temperature.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: December 30, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Shao-Wei Wang, Yu-Ren Wang, Chien-Liang Lin, Wen-Yi Teng, Tsuo-Wen Lu, Chih-Chung Chen, Ying-Wei Yen
  • Publication number: 20140374814
    Abstract: An embedded flash memory device includes a gate stack, and source and drain regions in the semiconductor substrate. The first source and drain regions are on opposite sides of the gate stack. The gate stack includes a bottom dielectric layer over the semiconductor substrate, a charge trapping layer over the bottom dielectric layer, a top dielectric layer over the charge trapping layer, a high-k dielectric layer over the top dielectric layer, and a metal gate over the high-k dielectric layer.
    Type: Application
    Filed: June 21, 2013
    Publication date: December 25, 2014
    Inventors: Wei Cheng Wu, Harry-Hak-Lay Chuang
  • Publication number: 20140374815
    Abstract: An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack.
    Type: Application
    Filed: June 21, 2013
    Publication date: December 25, 2014
    Inventors: Wei Cheng Wu, Harry-Hak-Lay Chuang
  • Publication number: 20140370678
    Abstract: A method for producing a memory device with nanoparticles, comprising the steps of: a) forming, in a semi-conductor substrate, source and drain regions, and at least one first dielectric on a zone of the substrate arranged between the source and drain regions and intended to form a channel of the memory device, b) deposition of an ionic liquid, comprising nanoparticles of an electrically conductive material in suspension, covering the first dielectric, c) formation of a deposition of nanoparticles on the first dielectric, d) removal of the remaining ionic liquid, e) forming a second dielectric and a control gate on at least one part of the deposition of nanoparticles.
    Type: Application
    Filed: August 29, 2014
    Publication date: December 18, 2014
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE AUX ENERGIES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Simon Deleonibus, Jean-Marie Basset, Paul Campbell, Thibaut Gutel, Paul-Henri Haumesser, Gilles Marchand, Catherine Santini
  • Patent number: 8912089
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a stacked body on a substrate. The stacked body includes a plurality of first conductive layers including a metallic element as a main component and a plurality of second conductive layers including a metallic element as a main component provided respectively between the first conductive layers. The method includes making a hole to pierce the stacked body. The method includes making a slit to divide the stacked body. The method includes making a gap between the first conductive layers by removing the second conductive layers by etching via the slit or the hole. The method includes forming a memory film including a charge storage film at a side wall of the hole. The method includes forming a channel body on an inner side of the memory film inside the hole.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: December 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiichi Omoto, Yoshihiro Uozumi, Tadashi Iguchi, Osamu Yamane, Kazuyuki Masukawa, Yoshihiro Yanai
  • Publication number: 20140362644
    Abstract: A memory structure comprises a semiconductor strip having a multi-gate channel region, the p-type terminal region adjacent a first side of the channel region and an n-type terminal region adjacent the second side of the channel region. A plurality of word lines is arranged to cross the semiconductor strip at cross points in the channel region. The bit line is coupled to a first end of the semiconductor strip, and a reference line is coupled to a second end of the semiconductor strip. Charge storage structures are disposed between the word lines in the plurality word lines and the channel region of the semiconductor strip, whereby memory cells are disposed in series along the semiconductor strip between the bit line and the reference line. Biasing unselected word lines can be used to select n-channel or p-channel modes in a single selected cell for read, program or erase.
    Type: Application
    Filed: March 13, 2014
    Publication date: December 11, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Hang-Ting LUE, Wei-Chen CHEN
  • Publication number: 20140363942
    Abstract: Tungsten silicide layers can be used in CMOS transistors in which the work function of the tungsten silicide layers can be tuned for use in PMOS and NMOS devices. A co-sputtering approach can be used in which silicon and tungsten are deposited on a high dielectric constant gate dielectric layer. The tungsten silicide layer can be annealed at or above a critical temperature to optimize the resistivity of the tungsten silicide layer. In some embodiments, the concentration of as-deposited tungsten silicide can be between 50 at % silicon to 80 at % silicon. The critical temperatures can be lower at higher silicon concentration, such as 700 C. at 63 at % silicon to 600 C. at 74 at % silicon.
    Type: Application
    Filed: June 11, 2013
    Publication date: December 11, 2014
    Inventors: Zhendong Hong, Ashish Bodke, Susie Tzeng
  • Patent number: 8907396
    Abstract: Devices, memory arrays, and methods are disclosed. In an embodiment, one such device has a source/drain zone that has first and second active regions, and an isolation region and a dielectric plug between the first and second active regions. The dielectric plug may extend below upper surfaces of the first and second active regions and may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: December 9, 2014
    Assignee: Micron Technology, Inc
    Inventors: John Hopkins, James Mathew, Jie Sun, Gordon Haller
  • Publication number: 20140353739
    Abstract: A semiconductor device including a first gate structure and a second gate structure immediately adjacent to each other with a spacer therebetween. Line width of the top of the second gate structure is not less than that of the bottom thereof. A fabrication method thereof is also disclosed. A transient first gate structure and a temporary gate structure are formed by etching through a first hard mask. A second gate structure is formed between a first spacer and a second spacer opposite to each other and disposed respectively on the transient first gate structure and temporary gate structure. The second gate structure is covered with a second hard mask. An etch process is performed through a patterned photoresist layer to remove exposed first hard mask and temporary gate structure and to partially remove exposed portion of first hard mask and transient first gate structure to form the first gate structure.
    Type: Application
    Filed: June 3, 2013
    Publication date: December 4, 2014
    Inventors: Hsiang-Chen Lee, Ping-Chia Shih, Chi-Cheng Huang, Wan-Fang Chung, Yu-Chun Chang, Je-Yi Su
  • Publication number: 20140353591
    Abstract: A transistor using a single crystal silicon nanowire and a method for fabricating the transistor is disclosed. The transistor using a single crystal silicon nanowire comprises a substrate and a single crystal silicon nanowire formed on the substrate. Here, the single crystal silicon nanowire comprises a source region and a drain region formed longitudinally with the single crystal silicon nanowire and separate from each other, and a channel region located between the source region and the drain region, wherein the perpendicular thickness of the channel region to the longitudinal direction is thinner than the thickness of the source region and the drain region.
    Type: Application
    Filed: January 4, 2012
    Publication date: December 4, 2014
    Applicant: Korea University Research And Business Foundation
    Inventors: Sangsig Kim, Myeong-Won Lee, Youngin Jeon
  • Patent number: 8901616
    Abstract: A method of forming a semiconductor device that includes forming a high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the high-k gate dielectric layer and the semiconductor substrate. A scavenging metal stack may be formed on the high-k gate dielectric layer. An annealing process may be applied to the scavenging metal stack during which the scavenging metal stack removes oxide material from the oxide containing interfacial layer, wherein the oxide containing interfacial layer is thinned by removing of the oxide material. A gate conductor layer is formed on the high-k gate dielectric layer. The gate conductor layer and the high-k gate dielectric layer are then patterned to provide a gate structure. A source region and a drain region are then formed on opposing sides of the gate structure.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Frank, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8900952
    Abstract: A method of forming a semiconductor device that includes forming a high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the high-k gate dielectric layer and the semiconductor substrate. A scavenging metal stack may be formed on the high-k gate dielectric layer. An annealing process may be applied to the scavenging metal stack during which the scavenging metal stack removes oxide material from the oxide containing interfacial layer, wherein the oxide containing interfacial layer is thinned by removing of the oxide material. A gate conductor layer is formed on the high-k gate dielectric layer. The gate conductor layer and the high-k gate dielectric layer are then patterned to provide a gate structure. A source region and a drain region are then formed on opposing sides of the gate structure.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Frank, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 8901665
    Abstract: The present disclosure provides a method of semiconductor fabrication including forming an inter-layer dielectric (ILD) layer on a semiconductor substrate. The ILD layer has an opening defined by sidewalls of the ILD layer. A spacer element is formed on the sidewalls of the ILD layer. A gate structure is formed in the opening adjacent the spacer element. In an embodiment, the sidewall spacer also for a decrease in the dimensions (e.g., length) of the gate structure formed in the opening.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: December 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Andrew Joseph Kelly, Pei-Shan Chien, Yung-Ta Li, Chan Syun Yang
  • Patent number: 8896071
    Abstract: A technique for isolating electrodes on different layers of a multilayer electronic device across an array containing more than 100000 devices on a plastic substrate. The technique comprises depositing a bilayer of a first dielectric layer (6) of a solution-processible polymer dielectric and a layer of parylene (9) to isolate layers of conductor or semiconductor on different levels of the device. The density of defects located in the active area of one of the multilayer electronic devices is typically more than 1 in 100000.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: November 25, 2014
    Assignee: Plastic Logic Limited
    Inventors: Timothy Von Werne, Catherine Mary Ramsdale, Henning Sirringhaus
  • Patent number: 8895382
    Abstract: A MOS solid-state imaging device is provided in which withstand voltage and 1/f noise of a MOS transistor are improved. In the MOS solid-state imaging device whose unit pixel has at least a photoelectric converting portion and a plurality of field effect transistors, the thickness of gate insulating film in a part of the field effect transistors is different from the thickness of gate insulating film in the other field effect transistors among the plurality of the field effect transistors.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: November 25, 2014
    Assignee: Sony Corporation
    Inventors: Noriko Takagi, Hiroyuki Mori
  • Publication number: 20140339624
    Abstract: A charge-retaining transistor includes a control gate and an inter-gate dielectric alongside the control gate. A charge-storage node of the transistor includes first semiconductor material alongside the inter-gate dielectric. Islands of charge-trapping material are alongside the first semiconductor material. An oxidation-protective material is alongside the islands. Second semiconductor material is alongside the oxidation-protective material, and is of some different composition from that of the oxidation-protective material. Tunnel dielectric is alongside the charge-storage node. Channel material is alongside the tunnel dielectric. Additional embodiments, including methods, are disclosed.
    Type: Application
    Filed: May 15, 2013
    Publication date: November 20, 2014
    Applicant: Micron Technology, Inc.
    Inventor: D.V. Nirmal Ramaswamy
  • Patent number: 8889515
    Abstract: A semiconductor device includes a substrate including a first region and a second region, a gate dielectric layer formed on the substrate, and a metal electrode layer formed on the gate dielectric layer and including a compound of carbon and nitrogen, wherein a metal electrode formed from the metal electrode layer in the first region has a work function lower than a work function of a metal electrode formed from the metal electrode layer in the second region and a nitrogen concentration of the metal electrode of the first region is smaller than a nitrogen concentration of the metal electrode of the second region.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: November 18, 2014
    Assignee: SK Hynix Inc.
    Inventors: Yun-Hyuck Ji, Woo-Young Park
  • Patent number: 8889516
    Abstract: A method is disclosed for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having an oxide layer on a surface of the semiconductor substrate, and removing the oxide layer to expose the surface of the semiconductor substrate. The method also includes performing a thermal annealing process on the semiconductor substrate using an inert gas as a thermal annealing protective gas after removing the oxide layer, and forming an insulating layer on the semiconductor substrate after performing the thermal annealing process. Further, the method includes forming a high-K gate dielectric layer on a surface of the insulating layer, and forming a protective layer on a surface of the high-K gate dielectric layer.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: November 18, 2014
    Assignee: Semiconductor Manufacturing International Corp.
    Inventor: Hualong Song
  • Patent number: 8889517
    Abstract: A broadband, omnidirectional, multi-layer, dielectric reflector for an LED in a white light emitting device provides both near 100% reflectivity across the visible spectrum of light, and electrical insulation between the substrate and the electrical circuitry used to power and control the LED. When a sealant material, having a higher index of refraction than air, is used to protect the LED and the accompanying electrical circuitry, an aluminum reflector layer or substrate is provided to make up for the loss of reflectivity at certain angles of incidence. The dielectric reflector includes two separate sections with two different thicknesses, a thinner section below the LED providing better heat conductivity, and a thicker section surrounding the LED providing better reflectivity.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: November 18, 2014
    Assignee: JDS Uniphase Corporation
    Inventors: Richard A. Bradley, Jr., Georg J. Ockenfuss
  • Patent number: 8889505
    Abstract: A method for manufacturing a semiconductor device includes forming a first-conductivity-type well and a second-conductivity-type well in a silicon substrate; stacking a first high-dielectric-constant insulating film and a first cap dielectric film above the silicon substrate; removing at least the first cap dielectric film from above the second-conductivity-type well; conducting a first annealing at a first temperature to cause an element included in the first cap dielectric film to diffuse into the first high-dielectric-constant insulating film disposed above the first-conductivity-type well; after the first annealing, stacking a second high-dielectric-constant insulating film and a second cap dielectric film above the silicon substrate; removing the second cap dielectric film disposed above the first-conductivity-type well; and conducting a second annealing at a second temperature lower than the first temperature to cause an element included in the second cap dielectric film to diffuse into the second high-
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: November 18, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Shinichi Akiyama, Kazuya Okubo, Nobuyuki Ohtsuka
  • Patent number: 8883624
    Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: November 11, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventor: Krishnaswamy Ramkumar
  • Publication number: 20140327093
    Abstract: A field-effect transistor comprises a substrate, a gate dielectric layer, a barrier layer, a metal gate electrode and a source/drain structure. The gate dielectric layer is disposed on the substrate. The barrier layer having a titanium-rich surface is disposed on the gate dielectric layer. The metal gate electrode is disposed on the titanium-diffused surface. The source/drain structure is formed in the substrate and adjacent to the metal gate electrode.
    Type: Application
    Filed: May 2, 2013
    Publication date: November 6, 2014
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kun-Yuan LO, Chih-Wei YANG, Cheng-Guo CHEN, Rai-Min HUANG, Jian-Cun KE
  • Patent number: 8871595
    Abstract: An embodiment of a method of integrating a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming in a first region of a substrate a channel of a memory device from a semiconducting material overlying a surface of the substrate, the channel connecting a source and a drain of the memory device; forming a charge trapping dielectric stack over the channel adjacent to a plurality of surfaces of the channel, wherein the charge trapping dielectric stack includes a blocking layer on a charge trapping layer over a tunneling layer; and forming a MOS device over a second region of the substrate.
    Type: Grant
    Filed: March 31, 2012
    Date of Patent: October 28, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Fredrick Jenne, Sagy Levy