Abstract: A semiconductor device includes a gate insulation layer formed over a substrate and having a high dielectric constant, a gate electrode formed over the gate insulation layer and a work function control layer formed between the substrate and the gate insulation layer and inducing a work function shift of the gate electrode.

Abstract: The invention provides a method of forming an electron memory storage device and the resulting device. The device comprises a gate structure which, in form, comprises a first gate insulating layer formed over a semiconductor substrate, a self-forming electron trapping layer of noble metal nano-crystals formed over the first gate insulating layer, a second gate insulating layer formed over the electron trapping layer, a gate electrode formed over the second gate insulating layer, and source and drain regions formed on opposite sides of the gate structure.

Abstract: An object of this invention is to provide a semiconductor device (an RFID) with reduced loss of voltage/current corresponding to a threshold value of a transistor, and having a voltage/current rectification property. Another object of this invention is to simplify a fabrication process and a circuit configuration. A rectifier circuit is provided in an element included in a semiconductor device (RFID) capable of communicating data wirelessly. As compared to the case where only a diode is provided, coils are provided between gate terminals and drain terminals of transistors constituting the diode in a rectifier circuit, so that the coils overlap an antenna which receives a radio wave, whereby a voltage output by the rectifier circuit is increased using electromagnetic coupling between the antenna which receives a radio wave and the coils, so that the rectification efficiency is improved.

Abstract: A memory cell (100) comprising a transistor, the transistor comprising a substrate (101), a first source/drain region (102), a second source/drain region (112), a gate (104) and a gate insulating layer (103) positioned between the substrate (101) and the gate (104), wherein the gate insulating layer (103) is in a direct contact with the substrate (101) and comprises charge traps (131) distributed over an entire volume of the gate insulating layer (101).

Abstract: A method is provided that includes providing a semiconductor substrate including at least a thin gate oxide pFET device region and a thick gate oxide pFET device region and forming a thin gate oxide pFET within the thin gate oxide pFET device region and a thick gate oxide pFET within the thick gate oxide pFET device region. The thin gate oxide pFET that is formed includes a layer of SiGe on an upper surface of the thin gate oxide pFET device region, a high k gate dielectric located on an upper surface of the layer of SiGe, a pFET threshold voltage adjusting layer located on an upper surface of the high k gate dielectric, and a gate conductor material atop the pFET threshold voltage adjusting layer. The thick gate oxide pFET that is formed includes a thermal oxide located on an upper surface of the thick gate oxide pFET device region, a silicon layer located on an upper surface of the thermal oxide and a gate conductor material located atop the silicon layer.

Abstract: A method of fabricating a non-volatile memory device includes: forming a tunnel insulation layer pattern and a floating gate electrode layer pattern over a semiconductor substrate; forming an isolation trench by etching an exposed portion of the semiconductor substrate so that the isolation trench is aligned with the tunnel insulation layer pattern and the floating gate electrode layer pattern; forming an isolation layer by filling the isolation trench with a filling insulation layer; forming a hafnium-rich hafnium silicon oxide layer over the isolation layer and the floating gate electrode layer pattern; forming a hafnium-rich hafnium silicon oxynitride layer by carrying out a first nitridation on the hafnium-rich hafnium silicon oxide layer; forming a silicon-rich hafnium silicon oxide layer over the hafnium-rich hafnium silicon oxynitride layer; forming a silicon-rich hafnium silicon oxynitride layer by carrying out a second nitridation on the silicon-rich hafnium silicon oxide layer; and forming a control

Abstract: A method for fabricating a microelectronic device with one or plural asymmetric double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first semiconducting block configured to form a first gate of a double-gate transistor, and at least a second semiconducting block configured to form a second gate of the double-gate transistor, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block.

Abstract: A normally-off power field-effect transistor semiconductor structure is provided. The structure includes a channel, a source electrode, a gate electrode and trapped charges which arranged between the gate electrode and the channel such that the channel is in an off-state when the source electrode and the gate electrode are on the same electric potential. Further, a method for forming a semiconductor device and a method for programming a power field effect transistor are provided.

Abstract: A manufacturing method of a non-volatile memory is disclosed. A gate structure is formed on a substrate and includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer is partly removed, thereby a symmetrical opening is formed among the gate conductive layer, the substrate and the gate dielectric layer, and a cavity is formed on end sides of the gate dielectric layer. A first oxide layer is formed on a sidewall and bottom of the gate conductive layer, and a second oxide layer is formed on a surface of the substrate. A nitride material layer is formed covering the gate structure, the first and second oxide layer and the substrate and filling the opening. An etching process is performed to partly remove the nitride material layer, thereby a nitride layer is formed on a sidewall of the gate conductive layer and extending into the opening.

Abstract: A non-volatile memory including a substrate, a stacked gate structure, two doped regions and a plurality of spacers is provided. The stacked gate structure is disposed on the substrate, wherein the stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer and a conductive layer in sequence from bottom to top relative to the substrate. The doped regions are disposed in the substrate at two sides of the stacked gate structure, respectively, and bottom portions of the doped regions contact with the substrate under the doped regions. The spacers are respectively disposed between each side of each of the doped regions and the substrate, and top portions of the spacers are lower than top portions of the doped regions.

Abstract: A dielectric such as a gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from elements such as zirconium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.

Abstract: Memory arrays and methods of their formation are disclosed. One such memory array has memory-cell strings are formed adjacent to separated substantially vertical, adjacent semiconductor structures, where the separated semiconductor structures couple the memory cells of the respective strings in series. For some embodiments, two dielectric pillars may be formed from a dielectric formed in a single opening, where each of the dielectric pillars has a pair of memory-cell strings adjacent thereto and where at least one memory cell of one of the strings on one of the pillars and at least one memory cell of one of the strings on the other pillar are commonly coupled to an access line.

Abstract: The present invention relates to a semiconductor device which is capable of simultaneously improving a short channel effect of a PMOS and the current of an NMOS and a method for manufacturing the same. The semiconductor device includes first and second gates formed over first and second areas of a semiconductor substrate, respectively; and first and second junction areas formed in a portion of the semiconductor substrate corresponding to both sides of the first gate and a portion of the semiconductor substrate corresponding to both sides of the second gate, and including a projection, respectively, wherein the projection of the first junction area has a height higher than the height of the projection of the second junction area, and the second junction area is formed such that it has a depth from the surface of the semiconductor substrate deeper than the depth of the first junction area.

Abstract: In one embodiment a method enabling in situ dopant implantation during growth of a III-nitride semiconductor body, comprises establishing a growth environment for the III-nitride semiconductor body in a composite III-nitride chamber having a dopant implanter and a growth chamber, growing the III-nitride semiconductor body in the growth chamber, and implanting the III-nitride semiconductor body in situ in the growth chamber using the dopant implanter. A semiconductor device produced using the disclosed method comprises a III-nitride semiconductor body having a first conductivity type formed over a support substrate, and at least one doped region produced by in situ dopant implantation of the III-nitride semiconductor body during its growth, that at least one doped region having a second conductivity type.

Abstract: A method for manufacturing a non-volatile memory and a structure thereof are provided. The manufacturing method comprises the following steps. Firstly, a substrate is provided. Next, a semiconductor layer is formed on the substrate. Then, a Si-rich dielectric layer is formed on the semiconductor layer. After that, a plurality of silicon nanocrystals is formed in the Si-rich dielectric layer by a laser annealing process to form a charge-storing dielectric layer. Last, a gate electrode is formed on the charge-storing dielectric layer.

Abstract: A first aspect of the present invention provides a semiconductor manufacturing apparatus including: a load lock chamber; a transfer chamber; and a treatment chamber 1 and a treatment chamber 2 which carry out treatment using plasma, wherein, in the treatment chamber 2, an exhaust means is provided with a control means for making an oxygen partial pressure into 1*10?5 [Pa] or less.

Abstract: A method for formation of a carbon-based field effect transistor (FET) includes depositing a first dielectric layer on a carbon layer located on a substrate; forming a gate electrode on the first dielectric layer; etching an exposed portion of the first dielectric layer to expose a portion of the carbon layer; depositing a second dielectric layer over the gate electrode to form a spacer, wherein the second dielectric layer is deposited by atomic layer deposition (ALD), and wherein the second dielectric layer does not form on the exposed portion of the carbon layer; forming source and drain contacts on the carbon layer and forming a gate contact on the gate electrode to form the carbon-based FET.

Abstract: A nonvolatile memory device and a manufacturing method thereof are provided. The manufacturing method includes the following steps. First, a substrate is provided. Then, a tunneling dielectric layer is formed on the substrate, and a dummy gate is form on the tunneling dielectric layer. Subsequently, an interlayer dielectric layer is formed around the dummy gate, and the dummy gate is removed to form an opening. Following that, a charge storage layer is formed on the inner side wall of the opening, and the charge storage layer covers the tunneling dielectric layer. Moreover, an inter-gate dielectric layer is formed on the charge storage layer, and a metal gate is formed on the inter-gate dielectric layer. Accordingly, a stacked gate structure of the nonvolatile memory device includes the tunneling dielectric layer, the charge storage layer, the inter-gate dielectric layer, and the metal gate.

Abstract: An integrated circuit of an array of nonvolatile memory cells has a dielectric stack layer over the substrate, and implanted regions in the substrate under the dielectric stack layer. The dielectric stack layer is continuous over a planar region, that includes locations of the dielectric stack layer that store nonvolatile data, such that these locations are accessed by word lines/bit lines.

Abstract: A semiconductor device manufacturing method of an embodiment includes the steps of: forming a first insulating layer on a semiconductor substrate; forming on the first insulating layer an amorphous or polycrystalline semiconductor layer having a narrow portion; forming on the semiconductor layer a second insulating layer having a thermal expansion coefficient larger than that of the semiconductor layer; performing thermal treatment; removing the second insulating layer; forming a gate insulating film on the side faces of the narrow portion; forming a gate electrode on the gate insulating film; and forming a source-drain region in the semiconductor layer.

Abstract: According to one aspect of the invention, there is provided a semiconductor device fabrication method comprising: forming a first gate electrode via a first gate insulating film on a P-type semiconductor region formed in a surface portion of a semiconductor substrate, and forming a second gate electrode via a second gate insulating film on an N-type semiconductor region formed in the surface portion of the semiconductor substrate; forming a first insulating film on side surfaces of the first gate electrode and the first gate insulating film, and forming a second insulating film on side surfaces of the second gate electrode and the second gate insulating film; forming a mask having a pattern corresponding to the P-type semiconductor region; etching away the second insulating film by using the mask; removing the mask; and forming a first gate electrode sidewall insulating film on the side surfaces of the first insulating film, and forming a second gate electrode sidewall insulating film on the side surfaces

Abstract: A nonvolatile read-only memory having a thin nitrided tunnel insulator surface with a charge blocking insulator over the nitrided surface is presented. The tunnel insulator may be formed of a metal oxide, a metal oxycarbide, a semiconductor oxide, or oxycarbide. The dielectric structure may be formed by nitridation of a surface of a tunnel insulator using ammonia and deposition of a blocking insulator having a larger band gap than the tunnel insulator. The dielectric structure may form part of a memory device, as well as other devices and systems.

Abstract: A method of making a gate structure includes the following steps. First, a gate is formed. Then, a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer are formed to cover the gate from bottom to top. Later, a dry etching is performed to etch the second silicon oxide layer. After that, a wet etching is performed to etch the silicon nitride layer and the first silicon oxide layer. The aforesaid wet etching is performed by utilizing an RCA cleaning solution. Furthermore, the silicon nitride layer is formed by the SINGEN process. Therefore, the first and second silicon oxide layer and the silicon nitride layer can be etched together by the RCA cleaning solution.

Abstract: A method for manufacturing a semiconductor device which includes steps of forming a dummy layer on a semiconductor substrate, forming a groove 12 in the semiconductor substrate while using the dummy layer as a mask, forming a tunnel insulating film and a trap layer to cover an inner surface of the groove and the dummy layer, eliminating the trap layer formed above the upper surface and at the sides of the dummy layer, and forming a top insulating film to cover a remaining trap layer and the exposed tunnel insulating film.

Abstract: A memory cell comprising: a semiconductor substrate with a surface with a source region and a drain region disposed below the surface of the substrate and separated by a channel region; a tunneling barrier dielectric structure with an effective oxide thickness of greater than 3 nanometers disposed above the channel region; a conductive layer disposed above the tunneling barrier dielectric structure and above the channel region; a charge trapping structure disposed above the conductive layer and above the channel region; a top dielectric structure disposed above the charge trapping structure and above the channel region; and a top conductive layer disposed above the top dielectric structure and above the channel region are described along with devices thereof and methods for manufacturing.

Abstract: The present disclosure provides a method for forming a semiconductor device that includes forming a replacement gate structure overlying a channel region of a substrate. A mandrel dielectric layer is formed overlying source and drain regions of the substrate. The replacement gate structure is removed to provide an opening exposing the channel region of the substrate. A functional gate structure is formed over the channel region including a work function metal layer. A protective cap structure is formed over the functional gate structure. At least one via is etched through the mandrel dielectric layer selective to the protective cap structure to expose a portion of at least one of the source region and the drain region. A conductive fill is then formed in the vias to provide a contact to the at least one of the source region and the drain region.

Abstract: A manufacturing method of a semiconductor device, including the steps of: loading into a processing chamber a substrate having a high dielectric gate insulating film and a metal electrode, with a side wall exposed by etching; applying oxidation processing to the substrate by supplying thereto hydrogen-containing gas and oxygen-containing gas excited by plasma, with the substrate heated to a temperature not allowing the high dielectric gate insulating film to be crystallized, in the processing chamber; and unloading the substrate after processing from the processing chamber.

Abstract: A method of ONO integration of a non-volatile memory device (e.g. EEPROM, floating gate FLASH and SONOS) into a baseline MOS device (e.g. MOSFET) is described. In an embodiment the bottom two ONO layers are formed prior to forming the channel implants into the MOS device, and the top ONO layer is formed simultaneously with the gate oxide of the MOS device.

Abstract: There is provided an improved method for depositing thin films using precursors to deposit binary oxides by atomic layer deposition (ALD) techniques. Also disclosed is an ALD method for depositing a high-k dielectric such as hafnium lanthanum oxide (HfLaO) on a substrate. Embodiments of the present invention utilize a combination of ALD precursor elements and cycles to deposit a film with desired physical and electrical characteristics. Electronic components and systems that integrate devices fabricated with methods consistent with the present invention are also disclosed.

Abstract: A method for forming a field effect transistor device includes forming an oxide layer on a substrate, forming a dielectric layer on the oxide layer, forming a first TiN layer on the dielectric layer, forming a metallic layer on the first layer, forming a second TiN layer on the metallic layer, removing a portion of the first TiN layer, the metallic layer, and the second TiN layer to expose a portion of the dielectric layer, forming a layer of stoichiometric TiN on the exposed portion of the dielectric layer and the second TiN layer, heating the device, and forming a polysilicon layer on the device.

Abstract: Embodiments of methods of forming non-volatile memory structures are provided. In one such embodiment, first and second source/drain regions are formed on a substrate so that the first and second source/drain regions define an intervening channel region. A charge blocking layer is formed over the channel region. A trapping layer is formed over the charge blocking layer. A tunnel layer of two or more sub-layers is formed over the trapping layer, where the two or more sub-layers form a crested barrier tunnel layer. A control gate is formed over the tunnel layer.

Abstract: A gate insulating film having a high dielectric constant, a semiconductor device provided with the gate insulating film, and a method for manufacturing such film and device are provided. The semiconductor device is provided with a group 14 (IVA) semiconductor board and a first oxide layer. The first oxide layer is composed of MO2 existing on the board, where M is a first metal species selected from the group 4 (IVB); and M?xOy, where M? is a second metal species selected from the group 3 (IIIB) and a group composed of lanthanide series, and x and y are integers decided by the oxidation number of M.

Abstract: A method for fabricating a microelectronic device comprising: a support, an etched stack of thin layers comprising: at least one first block and at least one second block resting on the support, in which at least one drain region and at least one source region, respectively, are capable of being formed, several semiconductor bars connecting a first zone of the first block and another zone of the second block, and able to form a multi-branch transistor channel, or several transistor channels, the device also comprising: a gate surrounding said bars and located between said first block and said second block, the gate being in contact with a first and a second insulating spacer in contact with at least one sidewall of the first block and with at least one sidewall of the second block, respectively, and at least partially separated from the first block and the second block, via said insulating spacers.

Abstract: Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. A rare earth-rare earth alloy incorporated metal nitride layer is formed above a gate dielectric. This process provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting NMOS transistors.

Abstract: The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400° C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer.

Abstract: A method of manufacturing a nonvolatile semiconductor memory includes: forming an insulator structure on a semiconductor substrate in a first region; forming a first gate insulating film on the semiconductor substrate outside the first region; blanket depositing a first gate material film and etching-back the first gate material film to form a first gate electrode on the first gate insulating film lateral to the insulator structure; removing the insulator structure; blanket forming a second gate insulating film; blanket depositing a second gate material film and etching-back the second gate material film to form a second gate electrode on the second gate insulating film in the first region; and silicidation of upper surfaces of the first and second gate electrodes. Any one of the first and second gate insulating films is a charge trapping film.

Abstract: Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor. A second array of second memory cells extends in a second direction, opposite to the first direction, from a second surface of the semiconductor. Both arrays may be non-volatile memory arrays. For example, one of the memory arrays may be a NAND flash memory array, while the other may be a one-time-programmable memory array.

Abstract: The present invention provides a dielectric film having a high permittivity and a high heat resistance. An embodiment of the present invention is a dielectric film (103) including a composite oxynitride containing an element A made of Hf, an element B made of Al or Si, and N and O, wherein mole fractions of the element A, the element B, and N expressed as B/(A+B+N) range from 0.015 to 0.095 and N/(A+B+N) equals or exceeds 0.045, and has a crystalline structure.

Abstract: The charge retention characteristics of a non-volatile memory, particularly, a MONOS-type non-volatile memory is improved. In a non-volatile memory cell including a tunnel silicon oxide film (107), a silicon nitride film (104) serving as a charge storage film, a silicon oxide film (105), and a gate electrode (108) which are sequentially formed on a semiconductor substrate, the tunnel silicon oxide film (107) has a stacked structure of a silicon oxynitride film (102) and a silicon oxide film (103). Herein, it is configured such that a density of nitrogen atoms contained in the silicon oxynitride film (102) decreases as a distance from an interface with the semiconductor substrate increases in a film-thickness direction of the silicon oxynitride film (102).

Abstract: A nonvolatile memory device includes a plurality of strings each having vertically-stacked active layers over a plurality of word lines, at least one bit line connection unit vertically formed over one end of the word lines and having a stairway shape, and a plurality of bit lines each coupled to each of a plurality of active regions of the bit line connection unit.

Abstract: An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel barrier layer may comprise a part of the gate dielectric of the HVTs. The tunnel barrier layer may constitute the entire gate dielectric of the HVTs. The corresponding tunnel barrier layer may be formed between or upon shallow trench isolation (STIs). Therefore, the manufacturing efficiency of a driver chip IC may be increased.

Abstract: In a non-volatile memory device, active fin structures extending in a first direction may be formed on a substrate. A tunnel insulating layer may be formed on surfaces of the active fin structures and bottom surfaces of trenches that may be defined by the active fin structures. A charge trapping layer and a blocking layer may be sequentially formed on the tunnel insulating layer. A gate electrode structure may include first portions disposed over top surfaces of the active fin structures and second portions vertically spaced apart from portions of the charge trapping layer that may be disposed over the bottom surfaces of the trenches, and may extend in a second direction substantially perpendicular to the first direction. Thus, lateral electron diffusion may be reduced in the charge trapping layer, and thereby the data retention performance and/or reliability of the non-volatile memory device may be improved.

Abstract: The present disclosure fabricates an embedded metal-oxide-nitride-oxide-silicon (MONOS) memory device. The memory device is stacked with memory layers having a low aspect ratio. The memory device can be easily fabricated with only two extra masks for saving cost. The present disclosure uses a general method for mass-producing TFT and is thus fit for fabricating NAND-type or NOR-type flash memory to be used as embedded memory in a system-on-chip.

Abstract: Disclosed is a semiconductor device using an oxide semiconductor, with stable electric characteristics and high reliability. In a process for manufacturing a bottom-gate transistor including an oxide semiconductor film, dehydration or dehydrogenation is performed by heat treatment and oxygen doping treatment is performed. The transistor including a gate insulating film subjected to the oxygen doping treatment and the oxide semiconductor film subjected to the dehydration or dehydrogenation by the heat treatment is a transistor having high reliability in which the amount of change in threshold voltage of the transistor by the bias-temperature stress (BT) test can be reduced.

Abstract: Provided is a novel electronic device that comprises graphite, graphene or the like. An electronic device having a substrate, a layer comprising a 6-member ring-structured carbon homologue as the main ingredient, a pair of electrodes, a layer comprising aluminium oxide as the main ingredient and disposed between the pair of electrodes, and a layer comprising aluminium as the main ingredient, wherein the layer comprising aluminium oxide as the main ingredient is disposed between the layer comprising a 6-member ring-structured carbon homologue as the main ingredient and the layer comprising aluminium as the main ingredient so as to be in contact with the two layers.

Abstract: The present invention provides a high-quality semiconductor device in which deterioration in transistor characteristics and an increase in interface layer due to a gate insulating film are suppressed, and a method for manufacturing the same. In the present invention, an interface layer, a diffusion suppressing layer and a high dielectric constant insulating film are formed sequentially in this order on one surface of a silicon substrate.

Abstract: A method is provided for fabricating a semiconductor device. A semiconductor substrate is provided. A first high-k dielectric layer is formed on the semiconductor substrate. A first treatment is performed on the high-k dielectric layer. In an embodiment, the treatment includes a UV radiation in the presence of O2 and/or O3. A second high-k dielectric layer is formed on the treated first high-k dielectric layer. A second treatment is performed on the second high-k dielectric layer. In an embodiment, the high-k dielectric layer forms a gate dielectric layer of a field effect transistor.

Abstract: A semiconductor device includes a gate insulation film formed over a semiconductor substrate; a cap film formed over the gate insulation film; a silicon oxide film formed over the cap film; a metal gate electrode formed over the silicon oxide film; and source/drain diffused layers formed in the semiconductor substrate on both sides of the metal gate electrode.

Abstract: The semiconductor device includes the nonvolatile memory cell in the main surface of a semiconductor substrate. The nonvolatile memory cell has a first insulating film over the semiconductor substrate, a conductive film, a second insulating film, the charge storage film capable of storing therein charges, a third insulating film over the charge storage film, a first gate electrode, a fourth insulating film in contact with the set of stacked films from the first insulating film to the foregoing first gate electrode, a fifth insulating film juxtaposed with the first insulating film over the foregoing semiconductor substrate, a second gate electrode formed over the fifth insulating film to be adjacent to the foregoing first gate electrode over the side surface of the fourth insulating film, and source/drain regions with the first and second gate electrodes interposed therebetween. The conductive film and the charge storage film are formed to two-dimensionally overlap.

Abstract: A reduction of a resistance of a bit line of a memory cell array and a reduction of a forming area of the memory cell array are planed. Respective bit lines running at right angles to a word line are composed of a diffusion bit line formed in a semiconductor substrate and a linear metal bit line on an upper side of the diffusion bit line. The diffusion bit line is formed in a linear pattern on a lower side of the metal bit line in the same manner, and the metal bit line is connected with the diffusion bit line between the word lines. An interlayer insulating film is formed on the memory cell array, and the metal bit line is formed with being buried in it.