Gate Insulator Structure Constructed Of Diverse Dielectrics (e.g., Mnos, Etc.) Or Of Nonsilicon Compound Patents (Class 438/287)
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Publication number: 20110233689Abstract: There is provided a semiconductor device that includes a III-V Group compound semiconductor having a zinc-blende-type crystal structure, an insulating material being in contact with the (111) plane of the III-V Group compound semiconductor, a plane of the III-V Group compound semiconductor equivalent to the (111) plane, or a plane that has an off angle with respect to the (111) plane or the plane equivalent to the (111) plane, and an MIS-type electrode being in contact with the insulating material and including a metal conductive material.Type: ApplicationFiled: November 27, 2009Publication date: September 29, 2011Applicants: SUMITOMO CHEMICAL COMPANY, LIMITED, THE UNIVERSITY OF TOKYO, NATIONAL INSTITUTE FOR MATERIALS SCIENCEInventors: Masahiko Hata, Noboru Fukuhara, Hisashi Yamada, Shinichi Takagi, Masakazu Sugiyama, Mitsuru Takenaka, Tetsuji Yasuda, Noriyuki Miyata, Taro Itatani, Hiroyuki Ishii, Akihiro Ohtake, Jun Nara
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Publication number: 20110233647Abstract: Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.Type: ApplicationFiled: September 27, 2010Publication date: September 29, 2011Inventors: Shenqing FANG, Angela HUI, Gang XUE, Alexander NICKEL, Kashmir SAHOTA, Scott BELL, Chun CHEN, Wai LO
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Publication number: 20110233649Abstract: A non-volatile semiconductor memory device includes: a charge accumulation layer (CAL) on a substrate; a memory gate formed onto the substrate through the CAL; a first side gate formed through a first insulating film on a first side of the memory gate; a second side gate formed through a second insulating film on a second side opposite to the first side; a first impurity implantation region (IIR1) in the substrate adjacent the first side gate; a second impurity implantation region (IIR2) formed in the substrate on a side of the second side gate; and a channel region between IIR1 and IIR2. The channel region includes a first region corresponding to a boundary between the CAL and the substrate; a select side region between the first region and IIR1; and an assist side region between the first region and IIR2. The select side region is longer than the assist side region.Type: ApplicationFiled: March 28, 2011Publication date: September 29, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Masakuni SHIMIZU
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Patent number: 8026143Abstract: The object of the present invention is to provide a method of manufacturing high permittivity gate dielectrics for a device such as an MOSFET. A HfSiO film is formed by sputtering a Hf metal film on a SiO2 film (or a SiON film) on a Si wafer. A TiO2 film is formed by sputtering a Ti metal film on the HfSiO film and subjecting the Ti metal film to a thermal oxidation treatment. A TiN metal film is deposited on the TiO2 film. The series of treatments are performed continuously, without exposing the films and the wafer to atmospheric air. The resultant TiN/TiO2/HfSiO/SiO2/Si structure satisfies the conditions: EOT<1.0 nm, low leakage current, and hysteresis <20 mV.Type: GrantFiled: November 1, 2007Date of Patent: September 27, 2011Assignee: Canon Anelva CorporationInventors: Naomu Kitano, Takashi Minami, Motomu Kosuda, Heiji Watanabe
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Publication number: 20110227140Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a memory film, and a SiGe film. The stacked body includes a plurality of conductive layers and a plurality of insulating layers alternately stacked above the substrate. The memory film includes a charge storage film. The memory film is provided on a sidewall of a memory hole punched through the stacked body. The SiGe film is provided inside the memory film in the memory hole.Type: ApplicationFiled: July 12, 2010Publication date: September 22, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Megumi ISHIDUKI, Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hideaki Aochi
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Publication number: 20110230028Abstract: In a manufacturing method of a straight word line NOR flash memory array, a source line is implanted after the formation of a word line in the NOR type flash memory array is completed, and a discrete implant region is formed in the NOR type flash memory array and parallel to a component isolation structure, and each discrete implant region constitutes an electric connection with a low impedance between a source line and source contacts on the source line. With such discrete distribution, adjacent memory cells will not be short-circuited or failed even if a deviation of a mash occurs during the manufacturing process.Type: ApplicationFiled: March 22, 2010Publication date: September 22, 2011Inventors: Yider Wu, Hung-Wei Chen
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Patent number: 8021948Abstract: A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.Type: GrantFiled: December 18, 2008Date of Patent: September 20, 2011Assignee: IMECInventors: Bogdan Govoreanu, Stefan De Gendt, Sven Van Elshocht, Tom Schram
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Patent number: 8022465Abstract: Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×1011/cm?2, and methods for forming such memory cells.Type: GrantFiled: November 15, 2005Date of Patent: September 20, 2011Assignee: Macronrix International Co., Ltd.Inventors: Yen-Hao Shih, Min-Ta Wu, Shin-Chin Lee, Jung-Yu Hsieh, Erh-Kun Lai, Kuang Yeu Hsieh
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Publication number: 20110220987Abstract: According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, an interconnection, and a contact plug. The base includes a substrate and a peripheral circuit formed on a surface of the substrate. The stacked body includes a plurality of conductive layers and a plurality of insulating layers alternately stacked above the base. The memory film is provided on an inner wall of a memory hole punched through the stacked body to reach a lowermost layer of the conductive layers. The memory film includes a charge storage film. The interconnection is provided below the stacked body. The interconnection electrically connects the lowermost layer of the conductive layers in an interconnection region laid out on an outside of a memory cell array region and the peripheral circuit. The contact plug pierces the stacked body in the interconnection region to reach the lowermost layer of the conductive layers in the interconnection region.Type: ApplicationFiled: July 22, 2010Publication date: September 15, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyasu Tanaka, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Hideaki Aochi
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Publication number: 20110220986Abstract: A memory device including a substrate, a conductive layer, a charge storage layer, first and second dopant regions and first and second cell dopant regions is provided. A plurality of trenches is deployed in the substrate. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first and second dopant regions having a first conductive type are configured in the substrate under bottoms of the trenches and in an upper portion of the substrate between two adjacent trenches, respectively. The first and second cell dopant regions having a second conductive type are configured in the substrate between lower portions of side surfaces of the trenches and in the substrate adjacent to the bottoms of the second dopant regions, respectively. The first and the second conductive types are different dopant types.Type: ApplicationFiled: March 15, 2010Publication date: September 15, 2011Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Fong Huang, I-Shen Tsai, Shang-Wei Lin, Miao-Chih Hsu, Kuan-Fu Chen
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Publication number: 20110223756Abstract: A method and apparatus are described for fabricating metal gate electrodes (85, 86) over a high-k gate dielectric layer (32) having a rare earth oxide capping layer (44) in at least the NMOS device area by treating the surface of a rare earth oxide capping layer (44) with an oxygen-free plasma process (42) to improve photoresist adhesion, forming a patterned photoresist layer (52) directly on the rare earth oxide capping layer (44), and then applying a wet etch process (62) to remove the exposed portion of the rare earth oxide capping layer (44) from the PMOS device area.Type: ApplicationFiled: March 11, 2010Publication date: September 15, 2011Inventors: James K. Schaeffer, Eric D. Luckowski, Todd C. Bailey, Amy L. Child, Daniel Jaeger, Renee Mo, Ying H. Tsang
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Publication number: 20110220995Abstract: A semiconductor device is provided that, in an embodiment, is in the form of a high voltage MOS (HVMOS) device. The device includes a semiconductor substrate and a gate structure formed on the semiconductor substrate. The gate structure includes a gate dielectric which has a first portion with a first thickness and a second portion with a second thickness. The second thickness is greater than the first thickness. A gate electrode is disposed on the first and second portion. In an embodiment, a drift region underlies the second portion of the gate dielectric. A method of fabricating the same is also provided.Type: ApplicationFiled: March 10, 2010Publication date: September 15, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsueh-Liang Chou, Ruey-Hsin Liu, Chih-Wen Yao, Hsiao-Chin Tuan
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Publication number: 20110221009Abstract: An apparatus has a semiconductor device that includes: a semiconductor substrate having a channel region, a high-k dielectric layer disposed at least partly over the channel region, a gate electrode disposed over the dielectric layer and disposed at least partly over the channel region, wherein the gate electrode is made substantially of metal, and a gate contact engaging the gate electrode at a location over the channel region. A different aspect involves a method for making a semiconductor device that includes: providing a semiconductor substrate having a channel region, forming a high-k dielectric layer at least partly over the channel region, forming a gate electrode over the dielectric layer and at least partly over the channel region, the gate electrode being made substantially of metal, and forming a gate contact that engages the gate electrode at a location over the channel region.Type: ApplicationFiled: March 10, 2010Publication date: September 15, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Harry Hak-Lay Chuang, Lee-Wee Teo, Han-Gan Chew
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Publication number: 20110220988Abstract: A method for manufacturing NAND memory cells includes providing a substrate having a first doped region formed therein; forming a first dielectric layer, a storage layer and a patterned hard mask on the substrate; forming a STI in the substrate through the patterned hard mask and removing the patterned hard mask to define a plurality of recesses; forming a second dielectric layer and a first conductive layer filling the recesses on the substrate; and performing a planarization process to remove a portion of the first conductive layer and the second dielectric layer to form a plurality of self-aligned islanding gate structures.Type: ApplicationFiled: May 24, 2011Publication date: September 15, 2011Inventors: Chun-Sung Huang, Ping-Chia Shih, Chiao-Lin Yang, Chi-Cheng Huang
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Patent number: 8017485Abstract: Methods of fabricating a semiconductor device are provided, the methods include forming a first dielectric layer, a data storage layer, and a second dielectric layer, which are sequentially stacked, on a semiconductor substrate. A mask having a first opening exposing a first region of the second dielectric layer is formed on the second dielectric layer. A gate electrode filling at least a portion of the first opening is formed. A second opening exposing a second region of the second dielectric layer is formed by etching the mask such that the second region is spaced apart from the first region. A second dielectric pattern and a data storage pattern are formed by sequentially etching the exposed second region of the second dielectric layer and the data storage layer. The second dielectric pattern is formed to have a greater width than a lower surface of the gate electrode.Type: GrantFiled: October 20, 2009Date of Patent: September 13, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Du-Hyun Cho, Tae-Hyuk Ahn, Sang-Sup Jeong, Jin-Hyuk Yoo
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Patent number: 8017484Abstract: Methods of forming transistor devices and structures thereof are disclosed. A first dielectric material is formed over a workpiece, and a second dielectric material is formed over the first dielectric material. The workpiece is annealed, causing a portion of the second dielectric material to combine with the first dielectric material and form a third dielectric material. The second dielectric material is removed, and a gate material is formed over the third dielectric material. The gate material and the third dielectric material are patterned to form at least one transistor.Type: GrantFiled: December 7, 2006Date of Patent: September 13, 2011Assignee: Infineon Technologies AGInventor: Hongfa Luan
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Patent number: 8017470Abstract: The invention includes a method of forming a structure over a semiconductor substrate. A silicon dioxide containing layer is formed across at least some of the substrate. Nitrogen is formed within the silicon dioxide containing layer. Substantially all of the nitrogen within the silicon dioxide is at least 10 ? above the substrate. After the nitrogen is formed within the silicon dioxide layer, conductively doped silicon is formed on the silicon dioxide layer.Type: GrantFiled: June 23, 2010Date of Patent: September 13, 2011Assignee: Round Rock Research, LLCInventors: Kevin L. Beaman, John T. Moore
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Publication number: 20110215394Abstract: According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, a contact plug, a global bit line, and a plurality of local bit lines. The base has a substrate and a peripheral circuit formed on the substrate. The stacked body has a plurality of conductive layers and insulating layers stacked alternately above the base. The memory film includes a charge storage film provided on an inner wall of a memory hole formed in a stacking direction of the stacked body. The channel body is provided inside the memory film in the memory hole. The contact plug is provided by piercing the stacked body. The global bit line is provided between the peripheral circuit and the stacked body and connected to a lower end portion of the contact plug. The plurality of local bit lines are provided above the stacked body and divided in an extending direction of the plurality of local bit lines.Type: ApplicationFiled: June 11, 2010Publication date: September 8, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yosuke Komori, Masaru Kidoh, Ryota Katsumata
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Patent number: 8012824Abstract: A method of reducing impurities in a high-k dielectric layer comprising the following steps. A substrate is provided. A high-k dielectric layer having impurities is formed over the substrate. The high-k dielectric layer being formed by an MOCVD or an ALCVD process. The high-k dielectric layer is annealed to reduce the impurities within the high-k dielectric layer.Type: GrantFiled: June 16, 2006Date of Patent: September 6, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Liang-Gi Yao, Ming-Fang Wang, Shih-Chang Chen, Mong-Song Liang
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Publication number: 20110211394Abstract: Storage transistors for flash memory areas in semiconductor devices may be provided on the basis of a self-aligned charge storage region. To this end, a floating spacer element may be provided in some illustrative embodiments, while, in other cases, the charge storage region may be efficiently embedded in the electrode material in a self-aligned manner during a replacement gate approach. Consequently, enhanced bit density may be achieved, since additional sophisticated lithography processes for patterning the charge storage region may no longer be required.Type: ApplicationFiled: November 4, 2010Publication date: September 1, 2011Inventors: Thilo Scheiper, Sven Beyer, Uwe Griebenow, Jan Hoentschel
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Patent number: 8008147Abstract: It is possible to prevent the deterioration of device characteristic as much as possible. A semiconductor device includes: a semiconductor substrate; a gate insulating film provided above the semiconductor substrate and containing a metal, oxygen and an additive element; a gate electrode provided above the gate insulating film; and source/drain regions provided in the semiconductor substrate on both sides of the gate electrode. The additive element is at least one element selected from elements of Group 5, 6, 15, and 16 at a concentration of 0.003 atomic % or more but 3 atomic % or less.Type: GrantFiled: January 22, 2009Date of Patent: August 30, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yuuichi Kamimuta, Akira Nishiyama, Yasushi Nakasaki, Tsunehiro Ino, Masato Koyama
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Patent number: 8008156Abstract: A method for making a nitride read only memory device with buried diffusion spacers is disclosed. An oxide-nitride-oxide (ONO) layer is formed on top of a silicon substrate, and a polysilicon gate is formed over the ONO layer. The polysilicon gate is formed less than a length of the ONO layer. Two buried diffusion spacers are formed beside two sidewalls of the polysilicon gate and over the ONO layer. Two buried diffusion regions are implanted on the silicon substrate next to the two buried diffusion spacers. The two buried diffusion regions are then annealed such that the approximate interfaces of the buried diffusion regions are under the sidewalls of the polysilicon gate. The structure of a nitride read only memory device with buried diffusion spacers is also described.Type: GrantFiled: June 7, 2009Date of Patent: August 30, 2011Assignee: Macronix International Co., Ltd.Inventor: Chien Hung Liu
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Patent number: 8008155Abstract: An electrode structure, e.g., a gate electrode for a transistor, includes: a volume of semiconductor material; a gate oxide on the semiconductor volume; a barrier layer, including silicon nitride, on the gate oxide layer; an adhesion layer on the barrier layer; and a metallic layer on the adhesion layer.Type: GrantFiled: June 11, 2007Date of Patent: August 30, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jaeman Yoon, Yungi Kim, Hyeoungwon Seo, Kangyoon Lee
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Publication number: 20110204454Abstract: An integrated circuit (IC) includes a substrate having a top semiconductor surface including at least one MOS device including a source and a drain region spaced apart to define a channel region. A SiON gate dielectric layer that has a plurality of different N concentration portions is formed on the top semiconductor surface. A gate electrode is on the SiON layer. The plurality of different N concentration portions include (i) a bottom portion extending to the semiconductor interface having an average N concentration of <2 atomic %, (ii) a bulk portion having an average N concentration >10 atomic %, and (iii) a top portion on the bulk portion extending to a gate electrode interface having an average N concentration that is ?2 atomic % less than a peak N concentration of the bulk portion.Type: ApplicationFiled: February 23, 2010Publication date: August 25, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: James Joseph Chambers, Hiroaki Niimi, Brian Keith Kirkpatrick
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Publication number: 20110207280Abstract: A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MxOy?2x/y M+SiO2 is positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.Type: ApplicationFiled: May 3, 2011Publication date: August 25, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Takashi Ando, Changhwan Choi, Martin M. Frank, Vijay Narayanan
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Patent number: 8003548Abstract: A method for forming an atomic deposition layer is provided, which includes: (a) performing a first water pulse on a substrate; (b) performing a precursor pulse on the hydroxylated substrate, wherein the precursor reacts with the hydroxyl groups and forms a layer; (c) purging the substrate with an inert carrier gas; (d) exposing the layer to a second water pulse for at least about 3 seconds so that the layer has a minimum of 70 percent of surface hydroxyl groups thereon; (e) purging the layer with the inert carrier gas; and (f) repeating steps (b) to (e) to form a resultant atomic deposition layer.Type: GrantFiled: June 3, 2010Date of Patent: August 23, 2011Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chen-Hua Yu, Liang-Gi Yao
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Patent number: 8003507Abstract: The present disclosure provides a method of fabricating a semiconductor device.Type: GrantFiled: June 4, 2009Date of Patent: August 23, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Jr Jung Lin, Yi-Shien Mor, Chien-Hao Chen, Kuo-Tai Huang, Yi-Hsing Chen
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Publication number: 20110198708Abstract: Transistors are provided including first and second source/drain regions, a channel region and a gate stack having a first gate dielectric over a substrate, the first gate dielectric having a dielectric constant higher than a dielectric constant of silicon dioxide, and a metal material in contact with the first gate dielectric, the metal material being doped with an inert element. Integrated circuits including the transistors and methods of forming the transistors are also provided.Type: ApplicationFiled: February 12, 2010Publication date: August 18, 2011Inventors: Cancheepuram V Srividya, Suraj Mathew, Dan Gealy
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Publication number: 20110198709Abstract: A semiconductor device includes a gate stack structure. The gate stack structure includes an interfacial layer formed on a semiconductor substrate, a high-k dielectric formed on the interfacial layer, a silicide gate including a diffusive material and an impurity metal, and formed over the high-k dielectric, and a barrier metal with a barrier effect to the diffusive material, and formed between the high-k dielectric and the metal gate. The impurity metal has a barrier effect to the diffusive material so that the diffusive material in the silicide gate can be prevented from being introduced into the high-k dielectric.Type: ApplicationFiled: February 9, 2011Publication date: August 18, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Hiroshi Sunamura
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Patent number: 7998820Abstract: A device and method of formation are provided for a high-k gate dielectric and gate electrode. The high-k dielectric material is formed, and a silicon-rich film is formed over the high-k dielectric material. The silicon-rich film is then treated through either oxidation or nitridation to reduce the Fermi-level pinning that results from both the bonding of the high-k material to the subsequent gate conductor and also from a lack of oxygen along the interface of the high-k dielectric material and the gate conductor. A conductive material is then formed over the film through a controlled process to create the gate conductor.Type: GrantFiled: August 7, 2007Date of Patent: August 16, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Liang-Gi Yao
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Patent number: 7999305Abstract: A semiconductor device includes an element region having a channel region, and a unit gate structure inducing a channel in the channel region, the unit gate structure including a tunnel insulating film formed on the element region, a charge storage insulating film formed on the tunnel insulating film, a block insulating film formed on the charge storage insulating film, and a control gate electrode formed on the block insulating film, wherein a distance between the element region and the control gate electrode is shorter at a center portion of the unit gate structure than at both ends thereof, as viewed in a section parallel to a channel width direction.Type: GrantFiled: January 29, 2009Date of Patent: August 16, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Ryota Fujitsuka, Yoshio Ozawa, Katsuaki Natori
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Publication number: 20110193180Abstract: The present disclosure provides an apparatus that includes a semiconductor device. The semiconductor device includes a substrate. The semiconductor device also includes a first gate dielectric layer that is disposed over the substrate. The first gate dielectric layer includes a first material. The first gate dielectric layer has a first thickness that is less than a threshold thickness at which a portion of the first material of the first gate dielectric layer begins to crystallize. The semiconductor device also includes a second gate dielectric layer that is disposed over the first gate dielectric layer. The second gate dielectric layer includes a second material that is different from the first material. The second gate dielectric layer has a second thickness that is less than a threshold thickness at which a portion of the second material of the second gate dielectric layer begins to crystallize.Type: ApplicationFiled: February 5, 2010Publication date: August 11, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jian-Hao Chen, Da-Yuan Lee, Kuang-Yuan Hsu
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Publication number: 20110193156Abstract: The electrically erasable programmable memory and its manufacturing method of the present invention forms above the floating gate the polysilicon spacer regions that are extended from the central part of the source region; the insulating part between the polysilicon spacer region and the floating gate has a smaller thickness to increase the capacitance between the floating gate and the polysilicon spacer region and further increasing the voltage coupled to the floating gate. Therefore, the present invention can effectively increase the coupling capacitance at the drain terminal, and has an advantage of low cost and easy production.Type: ApplicationFiled: October 13, 2008Publication date: August 11, 2011Applicant: GRACE SEMICONDUCTOR MANUFACTURING CORPORATIONInventor: Yaoqi Dong
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Patent number: 7994007Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes forming a shallow trench isolation (STI) region extending in a first direction on a semiconductor substrate, forming a mask layer extending in a second direction that intersects with the first direction on the semiconductor substrate and forming a trench on the semiconductor substrate by using the STI region and the mask layer as masks. In addition, the method includes forming a charge storage layer so as to cover the trench and forming a conductive layer on side surfaces of the trench and the mask layer. Word lines are formed from the conductive layer on side surfaces of the trench that oppose in the first direction by etching. The word lines are separated from each other and extend in the second direction.Type: GrantFiled: December 17, 2008Date of Patent: August 9, 2011Assignee: Spansion LLCInventors: Fumiaki Toyama, Fumihiko Inoue
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Patent number: 7994011Abstract: A method of manufacturing a nonvolatile memory device having a three-dimensional memory device includes alternately stacking a plurality of first and second material layers having a different etching selectivity on a semiconductor substrate; forming an opening penetrating the plurality of first and second material layers; removing the first material layers exposed by the opening to form extended portions extending in a direction perpendicular to the semiconductor substrate from the opening; conformally forming a charge storage layer along a surface of the opening and the extended portions; and removing the charge storage layer formed on sidewalls of the second material layers to locally form the charge storage layer patterns in the extended portions.Type: GrantFiled: November 10, 2009Date of Patent: August 9, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Imsoo Park, Young-Hoo Kim, Changki Hong, Jaedong Lee, Daehong Eom, Sung-Jun Kim
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Publication number: 20110189829Abstract: A memory device includes a first active region on a substrate and first and second source/drain regions on the substrate abutting respective first and second sidewalls of the first active region. A first gate structure is disposed on the first active region between the first and second source/drain regions. A second active region is disposed on the first gate structure between and abutting the first and second source/drain regions. A second gate structure is disposed on the second active region overlying the first gate structure.Type: ApplicationFiled: April 12, 2011Publication date: August 4, 2011Inventors: Eun-Jung Yun, Sung-Young Lee, Min-Sang Kim, Sung-Min Kim, Kyoung-Hwan Yeo
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Patent number: 7989242Abstract: An array substrate for a liquid crystal display device includes: a gate line and a gate electrode on a substrate, the gate electrode connected to the gate line; a gate insulating layer on the gate line and the gate electrode, the gate insulating layer including an organic insulating material such that a radical of carbon chain has a composition ratio of about 8% to about 11% by weight; a semiconductor layer on the gate insulating layer over the gate electrode; a data line crossing the gate line to define a pixel region; source and drain electrodes on the semiconductor layer, the source electrode connected to the data line and the drain electrode spaced apart from the source electrode; a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer having a drain contact hole exposing the drain electrode; and a pixel electrode on the passivation layer, the pixel electrode connected to the drain electrode through the drain contact hole.Type: GrantFiled: December 19, 2008Date of Patent: August 2, 2011Assignee: LG Display Co., Ltd.Inventors: Byung-Geol Kim, Gee-Sung Chae, Jae-Seok Heo, Woong-Gi Jun
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Patent number: 7989283Abstract: A manufacturing method of a semiconductor device is provided for improving the reliability of a semiconductor device including a MISFET with a high dielectric constant gate insulator and a metal gate electrode. A first Hf-containing insulating film containing Hf, La, and O as a principal component is formed as a high dielectric constant gate insulator for an n-channel MISFET. A second Hf-containing insulating film containing Hf, Al, and O as a principal component is formed as a high dielectric constant gate insulator for a p-channel MISFET. Then, a metal film and a silicon film are formed and patterned by dry etching to thereby form first and second gate electrodes. Thereafter, parts of the first and second Hf-containing insulating films not covered with the first and second gate electrodes are removed by wet etching.Type: GrantFiled: October 1, 2010Date of Patent: August 2, 2011Assignee: Renesas Electronics CorporationInventors: Shinichi Yamanari, Ryoichi Yoshifuku, Masaaki Shinohara, Takahiro Maruyama, Kenji Kawai, Yusaku Hirota
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Patent number: 7989280Abstract: A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.Type: GrantFiled: December 18, 2008Date of Patent: August 2, 2011Assignee: Intel CorporationInventors: Justin K. Brask, Suman Datta, Mark L. Doczy, James M. Blackwell, Matthew V. Metz, Jack T. Kavalieros, Robert S. Chau
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Publication number: 20110180864Abstract: A memory device is provided, including a substrate, a conductive layer, a charge storage layer, a plurality of isolation structures, a plurality of first doped regions, and a plurality of second doped regions. The substrate has a plurality of trenches. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The isolation structures are disposed in the substrate between two adjacent trenches, respectively. The first doped regions are disposed in an upper portion of the substrate between each isolation structure and each trench, respectively. The second doped regions are disposed in the substrate under a bottom portion of the trenches, in which each isolation structure is disposed between two adjacent second doped regions.Type: ApplicationFiled: January 22, 2010Publication date: July 28, 2011Applicant: MACRONIX International Co., Ltd.Inventors: YU-FONG HUANG, Miao-Chih Hsu, Kuan-Fu Chen, Tzung-Ting Han
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Patent number: 7985649Abstract: A method of making a semiconductor device on a semiconductor layer is provided. The method includes: forming a select gate dielectric layer over the semiconductor layer; forming a select gate layer over the select gate dielectric layer; and forming a sidewall of the select gate layer by removing at least a portion of the select gate layer. The method further includes growing a sacrificial layer on at least a portion of the sidewall of the select gate layer and under at least a portion of the select gate layer and removing the sacrificial layer to expose a surface of the at least portion of the sidewall of the select gate layer and a surface of the semiconductor layer under the select gate layer. The method further includes forming a control gate dielectric layer, a charge storage layer, and a control gate layer.Type: GrantFiled: January 7, 2010Date of Patent: July 26, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Brian A. Winstead, Cheong M. Hong, Sung-Taeg Kang, Konstantin V. Loiko, Spencer E. Williams
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Publication number: 20110176363Abstract: A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer.Type: ApplicationFiled: March 29, 2011Publication date: July 21, 2011Applicant: SPANSION LLCInventors: Shibly S. AHMED, Jun KANG, Hsiao-Han THIO, Imran KHAN, Dong-Hyuk JU, Chuan LIN
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Publication number: 20110175176Abstract: A method for forming a semiconductor structure is disclosed. The method includes forming a high-k dielectric layer over a semiconductor substrate and forming a gate layer over the high-k dielectric layer. The method also includes heating the gate layer to 350° C., wherein, if the gate layer includes non-conductive material, the non-conductive material becomes conductive. The method further includes annealing the substrate, the high-k dielectric layer, and the gate layer in excess of 350° C. and, during the annealing, applying a negative electrical bias to the gate layer relative to the semiconductor substrate. A semiconductor structure is also disclosed. The semiconductor structure includes a high-k dielectric layer over a semiconductor substrate, and a gate layer over the high-k dielectric layer. The gate layer has a negative electrical bias during anneal. A p-channel FET including this semiconductor structure is also disclosed.Type: ApplicationFiled: January 20, 2010Publication date: July 21, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Martin M. Frank
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Publication number: 20110177661Abstract: Methods of manufacturing NOR-type flash memory device include forming a tunnel oxide layer on a substrate, forming a first conductive layer on the tunnel oxide layer, forming first mask patterns parallel to one another on the first conductive layer in a y direction of the substrate, and selectively removing the first conductive layer and the tunnel oxide layer using the first mask patterns as an etch mask. Thus, first conductive patterns and tunnel oxide patterns are formed, and first trenches are formed to expose the surface of the substrate between the first conductive patterns and the tunnel oxide patterns. A photoresist pattern is formed to open at least one of the first trenches, and impurity ions are implanted using the photoresist pattern as a first ion implantation mask to form an impurity region extending in a y direction of the substrate. The photoresist pattern is removed.Type: ApplicationFiled: June 2, 2010Publication date: July 21, 2011Inventors: Young-Soo Song, Joong-Shik Shin
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Publication number: 20110177664Abstract: A method for fabricating SONOS memory is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer on the surface of the semiconductor substrate; forming a hard mask on the second silicon oxide layer; patterning the hard mask, the second silicon oxide layer, the silicon nitride layer, and the first silicon oxide layer to form a patterned hard mask and a stacked structure; forming a gate oxide layer on surface of the patterned hard mask; removing the gate oxide layer and the patterned hard mask; forming a patterned polysilicon layer on surface of the stacked structure; and forming a source/drain region in the semiconductor substrate adjacent to two sides of the polysilicon layer.Type: ApplicationFiled: January 20, 2010Publication date: July 21, 2011Inventors: Ping-Chia Shih, Yu-Cheng Yin
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Patent number: 7981808Abstract: A method of forming a gate dielectric layer includes forming a first dielectric layer over a semiconductor substrate using a first plasma, performing a first in-situ plasma nitridation of the first dielectric layer to form a first nitrided dielectric layer, forming a second dielectric layer over the first dielectric layer using a second plasma, performing a second in-situ plasma nitridation of the second dielectric layer to form a second nitrided dielectric layer; and annealing the first nitrided dielectric layer and the second nitrided dielectric layer, wherein the gate dielectric layer comprises the first nitrided dielectric layer and the second nitrided dielectric layer. In other embodiments, the steps of forming a dielectric layer using a plasma and performing an in-situ plasma nitridation are repeated so that more than two nitrided dielectric layers are formed and used as the gate dielectric layer.Type: GrantFiled: September 30, 2008Date of Patent: July 19, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Tien Ying Luo, Olubunmi O. Adetutu
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Publication number: 20110169105Abstract: A method of manufacturing a semiconductor device includes forming a polysilicon pattern, source/drain, and side-wall spacer, epitaxially growing silicide films on the source/drain, epitaxially growing silicon films selectively on the silicide film, removing the polysilicon pattern, forming a gate insulating film and gate electrode.Type: ApplicationFiled: January 6, 2011Publication date: July 14, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Kazuya OKUBO
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Patent number: 7977189Abstract: The present invention relates to a semiconductor device that includes a semiconductor substrate (10) having source/drain diffusion regions (14) formed therein and control gates (20) formed thereon, with grooves (18) being formed on the surface of the semiconductor substrate (10) and being located below the control gates (20) and between the source/drain diffusion regions (14). The grooves (18) are separated from the source/drain diffusion regions (14), thereby increasing the effective channel length to maintain a constant channel length for charge accumulation while enabling the manufacture of smaller memory cells. The present invention also provides a method of manufacturing the semiconductor device.Type: GrantFiled: July 14, 2009Date of Patent: July 12, 2011Assignee: Spansion LLCInventor: Masahiko Higashi
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Patent number: 7977733Abstract: A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.Type: GrantFiled: February 27, 2009Date of Patent: July 12, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhiro Shiino, Atsuhiro Sato, Takeshi Kamigaichi, Fumitaka Arai
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Patent number: 7977732Abstract: Provided are nonvolatile memory devices and methods of forming nonvolatile memory devices. Nonvolatile memory devices include a device isolation layer that defines an active region in a substrate. Nonvolatile memory devices further include a first insulating layer, a nonconductive charge storage pattern, a second insulating layer and a control gate line that are sequentially disposed on the active region. The charge storage pattern includes a horizontal portion and a protrusion disposed on an upper portion of an edge of the horizontal portion.Type: GrantFiled: September 26, 2008Date of Patent: July 12, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Taek Park, Won-Seok Jung