After Formation Of Source Or Drain Regions And Gate Electrode Patents (Class 438/290)
  • Patent number: 10062724
    Abstract: A sensing pixel array used in an image sensor includes sensing pixel units each including a photodiode, a row reset transistor, a buffer transistor, and a column control transistor at least. Photodiode converts light into a sensing signal. Row reset transistor is coupled to a reference reset signal and photodiode, and is controlled by a row reset signal. Buffer transistor is coupled to the output of photodiode to receive and buffer the sensing signal. Column control transistor is electrically connected to the control end or the output of the buffer transistor and is used as a switch which can be closed or open according to a column control signal to control whether to transfer charge of the reference reset signal to a capacitor when the row reset transistor becomes conductive.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: August 28, 2018
    Assignee: PixArt Imaging Inc.
    Inventors: Peng-Sheng Chen, Jui-Te Chiu, Han-Chi Liu
  • Patent number: 9177965
    Abstract: A nonvolatile memory device includes a substrate, a stacked structure with conductive materials and first insulating materials and the conductive materials and the first insulating materials are alternately stacked on the substrate, and a plurality of pillars in contact with the substrate and the pillars extend through the stacked structure in a direction perpendicular to the substrate. The device also includes information storage layers between the conductive materials and the first insulating materials, and second insulating materials between the first insulating materials and the pillars.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: November 3, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changhyun Lee, Sung-II Chang, Byoungkeun Son
  • Patent number: 9029225
    Abstract: The present disclosure discloses a method for manufacturing an N-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate diel
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: May 12, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qiuxia Xu, Huilong Zhu, Huajie Zhou, Gaobo Xu
  • Patent number: 9029227
    Abstract: A p-channel flash memory is formed with a charge storage stack embedded in a hetero-junction layer in which a raised source/drain is formed. Embodiments include forming a dummy gate stack on a substrate, forming a layer on the substrate by selective epitaxial growth, on each side of the dummy gate stack, forming spacers on the layer, forming raised source/drains, removing the dummy gate stack, forming a cavity between the spacers, and forming a memory gate stack in the cavity. Different embodiments include forming the layer of a narrow bandgap material, a narrow bandgap layer under the spacers and a wide bandgap layer adjacent thereto, or a wide bandgap layer under the spacers, a narrow bandgap layer adjacent thereto, and a wide bandgap layer on the narrow bandgap layer.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: May 12, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Eng Huat Toh, Elgin Quek, Ying Keung Leung, Sanford Chu
  • Patent number: 9006843
    Abstract: A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3, or alternatively, less than one-quarter the dopant concentration of the source and the drain.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: April 14, 2015
    Assignee: SuVolta, Inc.
    Inventors: Pushkar Ranade, Lucian Shifren, Sachin R. Sonkusale
  • Patent number: 8987080
    Abstract: Provided are methods for making metal gates suitable for FinFET structures. The methods described herein generally involve forming a high-k dielectric material on a semiconductor substrate; depositing a high-k dielectric cap layer over the high-k dielectric material; depositing a PMOS work function layer having a positive work function value; depositing an NMOS work function layer; depositing an NMOS work function cap layer over the NMOS work function layer; removing at least a portion of the PMOS work function layer or at least a portion of the NMOS work function layer; and depositing a fill layer. Depositing a high-k dielectric cap layer, depositing a PMOS work function layer or depositing a NMOS work function cap layer may comprise atomic layer deposition of TiN, TiSiN, or TiAlN. Either PMOS or NMOS may be deposited first.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: March 24, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Xinliang Lu, Seshadri Ganguli, Atif Noori, Maitreyee Mahajani, Shih Chung Chen, Yu Lei, Xinyu Fu, Wei Tang, Srinivas Gandikota
  • Patent number: 8952462
    Abstract: The present disclosure provides an apparatus that includes a semiconductor device. The semiconductor device includes a substrate. The semiconductor device also includes a first gate dielectric layer that is disposed over the substrate. The first gate dielectric layer includes a first material. The first gate dielectric layer has a first thickness that is less than a threshold thickness at which a portion of the first material of the first gate dielectric layer begins to crystallize. The semiconductor device also includes a second gate dielectric layer that is disposed over the first gate dielectric layer. The second gate dielectric layer includes a second material that is different from the first material. The second gate dielectric layer has a second thickness that is less than a threshold thickness at which a portion of the second material of the second gate dielectric layer begins to crystallize.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jian-Hao Chen, Da-Yuan Lee, Kuang-Yuan Hsu
  • Patent number: 8921181
    Abstract: Methods for forming an electronic device having a fluorine-stabilized semiconductor substrate surface are disclosed. In an exemplary embodiment, a layer of a high-? dielectric material is formed together with a layer containing fluorine on a semiconductor substrate. Subsequent annealing causes the fluorine to migrate to the surface of the semiconductor (for example, silicon, germanium, or silicon-germanium). A thin interlayer of a semiconductor oxide may also be present at the semiconductor surface. The fluorine-containing layer can comprise F-containing WSix formed by ALD from WF6 and SiH4 precursor gases. A precise amount of F can be provided, sufficient to bind to substantially all of the dangling semiconductor atoms at the surface of the semiconductor substrate and sufficient to displace substantially all of the hydrogen atoms present at the surface of the semiconductor substrate.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: December 30, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Dipankar Pramanik
  • Publication number: 20140370679
    Abstract: A semiconductor device according an aspect of the present disclosure may include an isolation layer formed within a substrate and formed to define an active region, a junction formed in the active region, well regions formed under the isolation layer, and a plug embedded within the substrate between the junction and the well regions and formed extend to a greater depth than the well regions.
    Type: Application
    Filed: September 2, 2014
    Publication date: December 18, 2014
    Inventor: Wan Cheul SHIN
  • Patent number: 8912527
    Abstract: A multi-quantum well structure includes two first barrier layers, two well layers sandwiched between the two first barrier layers, and a doped second barrier layer sandwiched between the two well layers. The second barrier layer has its conduction band and forbidden band gradually transiting to those of one of the well layers, and a dopant concentration of the second barrier layer gradually changes along a direction from one well layer to the other. The invention also relates to a light emitting diode structure having the multi-quantum well structure.
    Type: Grant
    Filed: July 4, 2013
    Date of Patent: December 16, 2014
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Shih-Cheng Huang, Ya-Wen Lin, Po-Min Tu
  • Patent number: 8889518
    Abstract: The present invention provides a laterally diffused metal oxide semiconductor (LDMOS) transistor and a method for fabricating it. The LDMOS transistor includes an n-type epitaxial layer formed on a p-type substrate, and an asymmetric conductive spacer which acts as its gate. The LDMOS transistor also includes a source and a drain region on either side of the asymmetric conductive spacer, and a channel region formed by ion-implantation on the asymmetric conductive spacer. The height of the asymmetric conductive spacer increases from the source region to the drain region. The channel region is essentially completely under the asymmetric conductive spacer and has smaller length than that of the channel region of the prior art LDMOS transistors. The LDMOS transistor of the present invention also includes a field oxide layer surrounding the active region of the transistor, and a thin dielectric layer isolating the asymmetric conductive spacer from the n-type epitaxial layer.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: November 18, 2014
    Assignee: Micrel, Inc.
    Inventors: Martin Alter, Paul McKay Moore
  • Publication number: 20140319625
    Abstract: A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate; and forming a trench in the semiconductor substrate by etching the semiconductor substrate. The methods also includes forming a threshold-adjusting layer doped with a certain type of threshold-adjusting ions to adjust the threshold voltage of the transistor on the semiconductor substrate in the trench; and forming a carrier drifting layer on the threshold-adjusting layer. Further the method includes forming a gate structure on the carrier drifting layer corresponding to the trench.
    Type: Application
    Filed: September 10, 2013
    Publication date: October 30, 2014
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: NEIL ZHAO
  • Patent number: 8835294
    Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure on the substrate, the gate structure including a dummy gate, removing the dummy gate from the gate structure thereby forming a trench, forming a work function metal layer partially filling the trench, forming a fill metal layer filling a remainder of the trench, performing a chemical mechanical polishing (CMP) to remove portions of the metal layers outside the trench, and implanting Si, C, or Ge into a remaining portion of the fill metal layer.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Guan Chew, Ming Zhu, Lee-Wee Teo, Harry Hak-Lay Chuang, Yi-Ren Chen
  • Patent number: 8796802
    Abstract: Semiconductor photodetectors are provided that may enable optimized usage of an active detector array. The semiconductor photodetectors may have a structure that can be produced and/or configured as simply as possible. A radiation detector system is also provided.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: August 5, 2014
    Assignee: First Sensor AG
    Inventors: Michael Pierschel, Frank Kudella
  • Publication number: 20140154853
    Abstract: The present disclosure discloses a method for manufacturing an N-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate diel
    Type: Application
    Filed: December 7, 2012
    Publication date: June 5, 2014
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Qiuxia Xu, Huilong Zhu, Huajie Zhou, Gaobo Xu
  • Publication number: 20140141586
    Abstract: A device includes a semiconductor substrate, isolation regions extending into the semiconductor substrate, a plurality of semiconductor fins higher than top surfaces of the isolation regions, and a plurality of gate stacks. Each of the gate stacks includes a gate dielectric on a top surface and sidewalls of one of the plurality of semiconductor fin, and a gate electrode over the gate dielectric. The device further includes a plurality of semiconductor regions, each disposed between and contacting two neighboring ones of the plurality of semiconductor fins. The device further includes a plurality of contact plugs, each overlying and electrically coupled to one of the plurality of semiconductor regions. An electrical connection electrically interconnects the plurality of semiconductor regions and the gate electrodes of the plurality of gate stacks.
    Type: Application
    Filed: January 28, 2014
    Publication date: May 22, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hsin Hu, Min-Chang Liang
  • Patent number: 8728903
    Abstract: A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A second isolation is formed on the semiconductor substrate, and a second element region is isolated via the second isolation. A second gate insulating film is formed on the second element region, and a second gate electrode is formed on the second gate insulating film. A first oxide film is formed between the first isolation and the first element region. A second oxide film is formed between the second isolation and the second element region. The first isolation has a width narrower than the second isolation, and the first oxide film has a thickness thinner than the second oxide film.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshitake Yaegashi, Junichi Shiozawa
  • Patent number: 8722523
    Abstract: When forming sophisticated semiconductor devices including high-k metal gate electrode structures, a raised drain and source configuration may be used for controlling the height upon performing a replacement gate approach, thereby providing superior conditions for forming contact elements and also obtaining a well-controllable reduced gate height.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: May 13, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Till Schloesser, Peter Baars, Frank Jakubowski
  • Patent number: 8686511
    Abstract: A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3?, or alternatively, less than one-quarter the dopant concentration of the source and the drain.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: April 1, 2014
    Assignee: SuVolta, Inc.
    Inventors: Pushkar Ranade, Lucian Shifren, Sachin R. Sonkusale
  • Patent number: 8679902
    Abstract: A method for fabricating a nanowire field effect transistor device includes depositing a first sacrificial layer on a substrate, depositing a first layer of a semiconductor material on the first sacrificial layer, depositing a second sacrificial layer on the first layer of semiconductor material, depositing a second layer of the semiconductor material on the second sacrificial layer, pattering and removing portions of the first sacrificial layer, the first semiconductor layer, the second sacrificial layer, and the second semiconductor layer, patterning a dummy gate stack, removing the dummy gate stack, removing portions of the sacrificial layer to define a first nanowire including a portion of the first semiconductor layer and a second nanowire including a portion of the second semiconductor layer, and forming gate stacks about the first nanowire and the second nanowire.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Tenko Yamashita, Chun-chen Yeh
  • Patent number: 8664067
    Abstract: An MOS transistor includes a doping profile that selectively increases the dopant concentration of the body region. The doping profile has a shallow portion that increases the dopant concentration of the body region just under the surface of the transistor under the gate, and a deep portion that increases the dopant concentration of the body region under the source and drain regions. The doping profile may be formed by implanting dopants through the gate, source region, and drain region. The dopants may be implanted in a high energy ion implant step through openings of a mask that is also used to perform another implant step. The dopants may also be implanted through openings of a dedicated mask.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: March 4, 2014
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Donald R. Disney
  • Patent number: 8664715
    Abstract: A transistor is formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: March 4, 2014
    Assignee: Advanced Analogic Technologies Incorporated
    Inventors: Donald R. Disney, Richard K. Williams
  • Publication number: 20140038378
    Abstract: A metal oxide semiconductor field effect transistor (MOSFET) with source side punch-through protection implant. Specifically, the MOSFET comprises a semiconductor substrate, a gate stack formed above the semiconductor substrate, source and drain regions, and a protection implant. The semiconductor substrate comprises a first p-type doping concentration. The source and drain regions comprise an n-type doping concentration, and are formed on opposing sides of the gate stack in the semiconductor substrate. The protection implant comprises a second p-type doping concentration, and is formed in the semiconductor substrate under the source region and surrounds the source region in order to protect the source region from the depletion region corresponding to the drain region.
    Type: Application
    Filed: August 12, 2013
    Publication date: February 6, 2014
    Applicant: Spansion LLC
    Inventors: Imran KHAN, Richard M. FASTOW, Dong-Hyuk JU
  • Patent number: 8633083
    Abstract: A metal oxide semiconductor field effect transistor (MOSFET) with source side punch-through protection implant. Specifically, the MOSFET comprises a semiconductor substrate, a gate stack formed above the semiconductor substrate, source and drain regions, and a protection implant. The semiconductor substrate comprises a first p-type doping concentration. The source and drain regions comprise an n-type doping concentration, and are formed on opposing sides of the gate stack in the semiconductor substrate. The protection implant comprises a second p-type doping concentration, and is formed in the semiconductor substrate under the source region and surrounds the source region in order to protect the source region from the depletion region corresponding to the drain region.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: January 21, 2014
    Assignee: Spansion LLC
    Inventors: Imran Khan, Richard Fastow, Dong-Hyuk Ju
  • Patent number: 8629027
    Abstract: An asymmetric insulated-gate field-effect transistor (100 or 102) has a source (240 or 280) and a drain (242 or 282) laterally separated by a channel zone (244 or 284) of body material (180 or 182) of a semiconductor body. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A more heavily doped pocket portion (250 or 290) of the body material extends largely along only the source. The source has a main source portion (240M or 280M) and a more lightly doped lateral source extension (240E or 280E). The drain has a main portion (242M or 282M) and a more lightly doped lateral drain extension (242E or 282E). The drain extension is more lightly doped than the source extension. The maximum concentration of the semiconductor dopant defining the two extensions occurs deeper in the drain extension than in the source extension. Additionally or alternatively, the drain extension extends further laterally below the gate electrode than the source extension.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: January 14, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Constantin Bulucea, William D. French, Sandeep R. Bahl, Jeng-Jiun Yang, D. Courtney Parker, Peter B. Johnson, Donald M. Archer
  • Patent number: 8586438
    Abstract: Recesses are formed in a pMOS region 2, and a SiGe layer is then formed so as to cover a bottom surface and a side surface of each of the recesses. Next, a SiGe layer containing Ge at a lower content than that in the SiGe layer is formed on each of the SiGe layers.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: November 19, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Naoyoshi Tamura, Yosuke Shimamune, Hirotaka Maekawa
  • Publication number: 20130295732
    Abstract: The present invention provides a method for making a field effect transistor, comprising of the following steps: providing a silicon substrate with a first type, forming a shallow trench by photolithography and etching processes, and forming silicon dioxide shallow trench isolations inside the shallow trench; forming by deposition a high-K gate dielectric layer and a metal gate electrode layer on the substrate and the shallow trench isolations; forming a gate structure by photolithography and etching processes; forming source/drain extension regions by ion implantation of dopants of a second type; depositing an insulating layer to form sidewalls tightly adhered to the sides of the gate; forming source/drain regions and PN junction interfaces between the source/drain region and the silicon substrate by ion implantation of dopants of the second type; and performing microwave annealing to activate implanted ions.
    Type: Application
    Filed: September 28, 2011
    Publication date: November 7, 2013
    Applicant: FUDAN UNIVERSITY
    Inventors: Dongping Wu, Yinghua Piao, Zhiwei Zhu, Shili Zhang, Wei Zhang
  • Patent number: 8574991
    Abstract: An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: November 5, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Uwe Griebenow, Maciej Wiatr
  • Patent number: 8570455
    Abstract: A semiconductor device includes a supporting substrate; a semiconductor film on the supporting substrate; a gate insulating film on the semiconductor film; a gate electrode on the gate insulating film; and a source region and a drain region formed by introducing impurity elements to the semiconductor film. The thickness of the semiconductor film is within the range of 20 nm to 40 nm. Low-concentration regions are provided between the source region and a channel forming region, and between the drain region and the channel forming region, respectively. The low-concentration regions each have an impurity concentration smaller than that of the source region and that of the drain region, and the impurity concentration in a lower surface side region on the side of the supporting substrate is smaller than that of an upper surface side region on the opposite side.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: October 29, 2013
    Assignee: NLT Technologies, Ltd.
    Inventors: Shigeru Mori, Isao Shouji, Hiroshi Tanabe
  • Patent number: 8563384
    Abstract: A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3?, or alternatively, less than one-quarter the dopant concentration of the source and the drain.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: October 22, 2013
    Assignee: SuVolta, Inc.
    Inventors: Pushkar Ranade, Lucian Shifren, Sachin R. Sonkusale
  • Publication number: 20130256796
    Abstract: A method of fabricating a metal-oxide-semiconductor field-effect transistor (MOSFET) device on a substrate includes doping a channel region of the MOSFET device with dopants of a first type. A source and a drain are formed in the substrate with dopants of a second type. Selective dopant deactivation is performed in a region underneath a gate of the MOSFET device.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 3, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Dhanyakumar Mahaveer SATHAIYA, Kai-Chieh YANG, Wei-Hao WU, Ken-Ichi GOTO, Zhiqiang WU, Yuan-Chen SUN
  • Patent number: 8525257
    Abstract: The present invention provides a laterally diffused metal oxide semiconductor (LDMOS) transistor and a method for fabricating it. The LDMOS transistor includes an n-type epitaxial layer formed on a p-type substrate, and an asymmetric conductive spacer which acts as its gate. The LDMOS transistor also includes a source and a drain region on either side of the asymmetric conductive spacer, and a channel region formed by ion-implantation on the asymmetric conductive spacer. The height of the asymmetric conductive spacer increases from the source region to the drain region. The channel region is essentially completely under the asymmetric conductive spacer and has smaller length than that of the channel region of the prior art LDMOS transistors. The LDMOS transistor of the present invention also includes a field oxide layer surrounding the active region of the transistor, and a thin dielectric layer isolating the asymmetric conductive spacer from the n-type epitaxial layer.
    Type: Grant
    Filed: November 18, 2009
    Date of Patent: September 3, 2013
    Assignee: Micrel, Inc.
    Inventors: Martin Alter, Paul Moore
  • Patent number: 8524562
    Abstract: A method to reduce (avoid) Fermi Level Pinning (FLP) in high mobility semiconductor compound channel such as Ge and III-V compounds (e.g. GaAs or InGaAs) in a Metal Oxide Semiconductor (MOS) device. The method is using atomic hydrogen which passivates the interface of the high mobility semiconductor compound with the gate dielectric and further repairs defects. The methods further improve the MOS device characteristics such that a MOS device with a quantum well is created.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: September 3, 2013
    Assignee: IMEC
    Inventors: Wei-E Wang, Han Chung Lin, Marc Meuris
  • Publication number: 20130221444
    Abstract: According to one embodiment, with gate electrodes and side walls as a mask, oblique ion implanting of the impurity is carried out for the semiconductor substrate, so that channel impurity layers having different dopant concentrations are simultaneously implanted beneath a first and a second gate electrode.
    Type: Application
    Filed: September 6, 2012
    Publication date: August 29, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hirofumi IGARASHI
  • Publication number: 20130207180
    Abstract: The symmetric LDMOS transistor comprises a semiconductor substrate (1), a well (2) of a first type of conductivity in the substrate, and wells (3) of an opposite second type of conductivity. The wells (3) of the second type of conductivity are arranged at a distance from one another. Source/drain regions (4) are arranged in the wells of the second type of conductivity. A gate dielectric (7) is arranged on the substrate, and a gate electrode (8) on the gate dielectric. A doped region (10) of the second type of conductivity is arranged between the wells of the second type of conductivity at a distance from the wells. The gate electrode has a gap (9) above the doped region (10), and the gate electrode overlaps regions that are located between the wells (3) of the second type of conductivity and the doped region (10).
    Type: Application
    Filed: May 30, 2011
    Publication date: August 15, 2013
    Applicant: AMS AG
    Inventors: Jong Mun Park, Georg Rohrer
  • Patent number: 8455322
    Abstract: Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Rajendran Krishnasamy, Kathryn T. Schonenberg
  • Patent number: 8445342
    Abstract: A short channel semiconductor device is formed with halo regions that are separated from the bottom of the gate electrode and from each other. Embodiments include implanting halo regions after forming source/drain regions and source/drain extension regions. An embodiment includes forming source/drain extension regions in a substrate, forming source/drain regions in the substrate, forming halo regions under the source/drain extension regions, after forming the source drain regions, and forming a gate electrode on the substrate between the source/drain regions. By forming the halo regions after the high temperature processing involved informing the source/drain and source/drain extension regions, halo diffusion is minimized, thereby maintaining sufficient distance between halo regions and reducing short channel NMOS Vt roll-off.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: May 21, 2013
    Assignee: Globalfoundries Inc.
    Inventors: Bin Yang, Man Fai Ng
  • Patent number: 8404551
    Abstract: A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3, or alternatively, less than one-quarter the dopant concentration of the source and the drain.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: March 26, 2013
    Assignee: Suvolta, Inc.
    Inventors: Pushkar Ranade, Lucian Shifren, Sachin R. Sonkusale
  • Patent number: 8389369
    Abstract: An electronic device can include a drain region of a transistor, a channel region of the transistor, and a doped region that is disposed under substantially all of the channel region, is not disposed under substantially all of a heavily doped portion of the drain region, and has a higher dopant concentration compared to the channel region. A process of forming an electronic device can include forming a drain region, a channel region, and a doped region, wherein the drain region has a conductivity type opposite that of the channel and doped region. After forming the drain, channel, and doped regions, the doped region is disposed under substantially all of the channel region, the doped region is not disposed under substantially all of a heavily doped portion of the drain region, and the drain region is laterally closer to the doped region than to the channel region.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: March 5, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Gary H. Loechelt
  • Publication number: 20130043534
    Abstract: The present disclosure discloses a lateral DMOS with recessed source contact and method for making the same. The lateral DMOS comprises a recessed source contact which has a portion recessed into a source region to reach a body region of the lateral DMOS. The lateral DMOS according to various embodiments of the present invention may have greatly reduced size and may be cost saving for fabrication.
    Type: Application
    Filed: August 18, 2011
    Publication date: February 21, 2013
    Inventors: Donald R. Disney, Lei Zhang, Tiesheng Li
  • Patent number: 8361872
    Abstract: A method of forming a semiconductor device includes: forming a channel of a field effect transistor (FET) in a substrate; forming a heavily doped region in the substrate; and forming recesses adjacent the channel and the heavily doped region. The method also includes: forming an undoped or lightly doped intermediate layer in the recesses on exposed portions of the channel and the heavily doped region; and forming source and drain regions on the intermediate layer such that the source and drain regions are spaced apart from the heavily doped region by the intermediate layer.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: January 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Toshiharu Furukawa, Robert R. Robison
  • Patent number: 8357574
    Abstract: A method for fabricating an integrated device is disclosed. The disclosed method provides improved formation selectivity of epitaxial films over a pre-determined region designed for forming an epi film and a protective layer preferred not to form an epi, polycrystalline, or amorphous film thereon during an epi film formation process. In an embodiment, the improved formation selectivity is achieved by providing a nitrogen-rich protective layer to decrease the amount of growth epi, polycrystalline, or amorphous film thereon.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: January 22, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hsi Yeh, Hsien-Hsin Lin, Hui Ouyang, Chi-Ming Yang
  • Patent number: 8357579
    Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A dopant-rich layer having first type dopants is formed on a sidewall and a bottom of each of the recesses. A silicon-containing material structure is formed in each of the recesses. The silicon-containing material structure has second type dopants. The second type dopants are opposite to the first type dopants.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: January 22, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: King-Yuen Wong, Ming-Lung Cheng, Chien-Tai Chan, Da-Wen Lin, Chung-Cheng Wu
  • Publication number: 20130011986
    Abstract: The present application discloses a method for manufacturing a full silicide metal gate bulk silicon multi-gate fin field effect transistor, which comprises the steps of: forming at least one fin on the semiconductor substrate; forming a gate stack structure on top and side surfaces of the fin; forming a source/drain extension area in the fin on both sides of the gate stack structure; forming a source/drain area on both sides of the source/drain extension area; forming silicide on the source/drain area; forming a full silicide metal gate electrode; and forming contact and implementing metalization. The present invention eliminates the self-heating effect and the floating body effect of SOI devices, then has a much lower cost, overcomes such defects as the polysilicon gate depletion effect, Boron penetration effect, and large series resistance of polysilicon gate electrodes, and has good compatibility with the planar COMS technology, thus it can be easily integrated.
    Type: Application
    Filed: August 3, 2011
    Publication date: January 10, 2013
    Inventors: Huajie Zhou, Qiuxia Xu
  • Patent number: 8329566
    Abstract: The present invention relates to a method of manufacturing a semiconductor device, wherein the method comprises: providing a substrate; forming a source region, a drain region, a dummy gate structure, and a gate dielectric layer on the substrate, wherein the dummy gate structure is between the source region and the drain region on the substrate, and the gate dielectric layer is between the substrate and the dummy gate structure; annealing the source region and the drain region; removing the dummy gate structure to form an opening; implanting dopants into the substrate from the opening to form a steep retrograded well; annealing to activate the dopants; and forming a metal gate on the gate dielectric layer by deposition.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: December 11, 2012
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Wenwu Wang
  • Publication number: 20120302026
    Abstract: A method for forming a transistor includes providing a substrate, forming a well region in the substrate, and forming a gate structure on a surface of the well region. The gate structure includes a gate oxide layer on the surface of the well region and a gate on the gate oxide layer. The method further includes forming source/drain regions in the substrate at opposite sides of the gate structure and performing an ion doping to the substrate to adjust a threshold voltage. The ion doping is performed after the source/drain regions are formed to reduce the impact to the diffusion of the ions caused by heat treatments performed before the ion doping. The method further includes heating the substrate after the ion doping at a temperature from about 400° C. to about 500° C.
    Type: Application
    Filed: October 14, 2011
    Publication date: November 29, 2012
    Applicant: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Meng ZHAO
  • Patent number: 8309420
    Abstract: A semiconductor structure is provided with (i) an empty well having relatively little well dopant near the top of the well and (ii) a filled well having considerably more well dopant near the top of the well. Each well is defined by a corresponding body-material region (108 or 308) of a selected conductivity type. The regions respectively meet overlying zones (104 and 304) of the opposite conductivity type. The concentration of the well dopant reaches a maximum in each body-material region no more than 10 times deeper below the upper semiconductor surface than the overlying zone's depth, decreases by at least a factor of 10 in moving from the empty-well maximum-concentration location through the overlying zone to the upper semiconductor surface, and increases, or decreases by less than a factor of 10, in moving from the filled-well maximum-concentration location through the other zone to the upper semiconductor surface.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: November 13, 2012
    Assignee: National Semiconductor Corporation
    Inventor: Constantin Bulucea
  • Patent number: 8298879
    Abstract: The present invention generally relates to thin film transistors (TFTs) and methods of making TFTs. The active channel of the TFT may comprise one or more metals selected from the group consisting of zinc, gallium, tin, indium, and cadmium. The active channel may also comprise nitrogen and oxygen. To protect the active channel during source-drain electrode patterning, an etch stop layer may be deposited over the active layer. The etch stop layer prevents the active channel from being exposed to the plasma used to define the source and drain electrodes. The etch stop layer and the source and drain electrodes may be used as a mask when wet etching the active material layer that is used for the active channel.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: October 30, 2012
    Assignee: Applied Materials, Inc.
    Inventor: Yan Ye
  • Publication number: 20120235213
    Abstract: The present invention provides a semiconductor structure with a stressed layer in the channel and method for forming the same. The semiconductor structure comprises a substrate; a gate stack, including a gate dielectric layer formed over the substrate, gate layer formed over the gate dielectric layer, a source region and a drain region formed in the substrate by both sides of the gate stack; one or more spacers formed on both sides of the gate stack; and an embedded stressed layer formed under the gate stack in the substrate. In the embodiments of the present invention, the carrier mobility can be effectively increased by the embedded stressed layer added in the channel under the gate stack, so that the driving current of transistors is improved. Moreover, the technological process for forming this embedded stressed layer in the present invention has a lower thermal budget, which therefore assists in maintaining a higher stress level in the channel region.
    Type: Application
    Filed: June 24, 2010
    Publication date: September 20, 2012
    Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
  • Patent number: 8258035
    Abstract: A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion (215) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant (253, 254).
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: September 4, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Leo Mathew, John J. Hackenberg, David C. Sing, Tab A. Stephens, Daniel G. Tekleab, Vishal P. Trivedi