Abstract: A method includes forming a fin that includes a first semiconductor layers and a second semiconductor layers alternatively disposed; forming a gate stack on the fin and a gate spacer disposed on a sidewall of the gate stack; etching the fin within a source/drain region, resulting in a source/drain trench; recessing the first semiconductor layers in the source/drain trench, resulting in first recesses underlying the gate spacer; forming inner spacers in the first recesses; recessing the second semiconductor layers in the source/drain trench, resulting in second recesses; and epitaxially growing a source/drain feature in the source/drain trench, wherein the epitaxially growing further includes a first epitaxial semiconductor layer extending into the second recesses; and a second epitaxial semiconductor layer on the first epitaxial semiconductor layer and filling in the source/drain trench, wherein the first and second epitaxial semiconductor layers are different in composition.

Abstract: A Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor with implant alignment spacers includes a gate stack comprising a first nitride layer. The first nitride layer is formed on a silicon layer. The gate stack is separated from a substrate by a first oxide layer. The gate stack includes a polysilicon layer formed from the silicon layer, and a second oxide layer is formed on a sidewall of the polysilicon layer. A drain region of the LDMOS transistor is implanted with a first implant aligned to a first edge formed by the second oxide layer. A second nitride layer conformingly covers the second oxide layer. A nitride etch-stop layer conformingly covers the second nitride layer.

Abstract: A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.

Abstract: A method for manufacturing a Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor with implant alignment spacers includes etching a gate stack comprising a first nitride layer. The first nitride layer is on a silicon layer. The gate stack is separated from a substrate by a first oxide layer. The gate stack is oxidized to form a polysilicon layer from the silicon layer, and to form a second oxide layer on a sidewall of the polysilicon layer. A drain region of the LDMOS transistor is implanted with a first implant aligned to a first edge formed by the second oxide layer. A second nitride layer is formed conformingly covering the second oxide layer. A nitride etch-stop layer is formed conformingly covering the second nitride layer.

Abstract: A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.

Abstract: A method for manufacturing a Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor with implant alignment spacers includes etching a gate stack comprising a first nitride layer. The first nitride layer is on a silicon layer. The gate stack is separated from a substrate by a first oxide layer. The gate stack is oxidized to form a polysilicon layer from the silicon layer, and to form a second oxide layer on a sidewall of the polysilicon layer. A drain region of the LDMOS transistor is implanted with a first implant aligned to a first edge formed by the second oxide layer. A second nitride layer is formed conformingly covering the second oxide layer. A nitride etch-stop layer is formed conformingly covering the second nitride layer.

Abstract: A semiconductor device comprising a passive magnetoelectric transducer structure adapted for generating a charge via mechanical stress caused by a magnetic field. The first transducer structure has a first terminal electrically connectable to the control terminal of an electrical switch, and having a second terminal electrically connectable to the first terminal of the electrical switch for providing a control signal for opening/closing the switch. The switch may be a FET. A passive magnetic switch using a magnetoelectric transducer structure. Use of a passive magnetoelectric transducer structure for opening or closing a switch without the need for an external power supply.

Abstract: A method of fabricating a semiconductor device includes forming first gate structure and a second gate structure over a core device region of a substrate. The method further includes forming stressors at opposite sides of the first gate structure. The method further includes doping the stressors to form a first source region and a first drain region of a first device. The method further includes doping into the substrate and at opposite sides of the second gate structure to form a second source region and a second drain region of a second device, wherein the first source region, the first drain region, the second source region and the second drain region are of a same conductivity, and the first source region comprises a different material from the second source region.

Abstract: A standard cell establishment method is disclosed. The standard cell establishment method includes the following operations: setting a first implant split case; obtaining a plurality of characteristic parameters according to the first implant split case; applying the plurality of characteristic parameters to a device delay metric so as to obtain a speed parameter; optimizing a channel parameter if the speed parameter is better than a previous speed parameter; and establishing a standard cell if the channel parameter is optimized successfully.

Abstract: A semiconductor device may include a semiconductor substrate. The semiconductor device may further include a gate electrode that overlaps the semiconductor substrate. The semiconductor device may further include a channel region that overlaps at least one of the gate electrode and the semiconductor substrate. The semiconductor device may further include a stress adjustment element that contacts the channel region and is positioned between the channel region and a surface of the semiconductor substrate in a direction perpendicular to the surface of the semiconductor substrate. A maximum width of the channel region in a direction parallel to the surface of the semiconductor substrate is greater than a maximum width of the stress adjustment element in the direction parallel to the surface of the semiconductor substrate in a cross-sectional view of the semiconductor device.

Abstract: The invention provides a fabrication method of a field-effect transistor. The method includes: forming a support structure with a superlattice feature on a semiconductor substrate, where the support structure includes a first semiconductor material layer and a second semiconductor material layer that are alternately disposed, and an isolation layer is disposed on two sides of the support structure; forming, along a boundary between the isolation layer and the support structure, a dummy gate structure that covers the support structure, where a length of the dummy gate structure in a gate length direction is less than the first semiconductor material layer; removing, along the gate length direction, an area other than a sacrificial layer in the first semiconductor material layer to form an insulation groove,; and forming a source and a drain in a preset source drain area along the gate length direction.

Abstract: A semiconductor device includes a source region, a drain region, a core channel region, and a barrier layer. The core channel region is between the source region and the drain region. The barrier layer is between the core channel region and the drain region. The barrier layer is a graded doped barrier layer.

Abstract: Semiconductor devices, such as photonics devices, employ substantially curved-shaped Silicon-Germanium (SiGe) structures and are fabricated using zero-change CMOS fabrication process technologies. In one example, a closed-loop resonator waveguide-coupled photodetector includes a silicon resonator structure formed in a silicon substrate, interdigitated n-doped well-implant regions and p-doped well-implant regions forming multiple silicon p-n junctions around the silicon resonator structure, and a closed-loop SiGe photocarrier generation region formed in a pocket within the interdigitated n-doped and p-doped well implant regions. The closed-loop SiGe region is located so as to substantially overlap with an optical mode of radiation when present in the silicon resonator structure, and traverses the multiple silicon p-n junctions around the silicon resonator structure.

Abstract: A semiconductor structure a base substrate and a sidewall spacer layer formed on the base substrate. The sidewall spacer layer includes a plurality of first sidewall spacer layers and a plurality of second sidewall spacer layers spaced apart from each other. At least one sidewall of a second sidewall spacer layer of the plurality of second sidewall spacer layers is formed on a first sidewall spacer layer of the plurality of first sidewall spacer layers. The plurality of first sidewall spacer layers has a thickness greater than the plurality of second sidewall spacer layers, based on a surface of the base substrate. The plurality of first sidewall spacer layers has a material structure different than the plurality of second sidewall spacer layers.

Abstract: A MOSFET includes: a semiconductor base substrate having n-type column regions and p-type column regions, the n-type column regions and the p-type column regions forming a super junction structure; and a gate electrode which is formed on a first main surface side of the semiconductor base substrate by way of a gate insulation film, wherein crystal defects whose density is increased locally as viewed along a depth direction are formed in the n-type column regions and the p-type column regions, using the first main surface as a reference and assuming a depth to a deepest portion of the super junction structure as Dp, a depth at which density of the crystal defects exhibits a maximum value as Dd, and a half value width of density distribution of the crystal defects as W, a relationship of 0.25Dp?Dd<0.95Dp and a relationship of 0.05Dp<W<0.5Dp are satisfied.

Abstract: A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.

Abstract: A semiconductor device 1 includes: a well region 5 provided on a surface layer of a semiconductor substrate 2; a source region 14S and a drain region 15D disposed to be distant from each other on the surface layer of the well region 5; a channel region 6 provided between the source region 14S and the drain region 15D; and a gate electrode 8 provided over the channel region 6 with a gate insulator 7 interposed therebetween. A gate length of the gate electrode 8 is 1.5 ?m or less, the channel region 6 includes indium as a channel impurity, a distance between a surface of the channel region 6 and a concentration peak position of the channel impurity is 20 nm to 70 nm, and a concentration of the channel impurity gradually decreases in a direction from the concentration peak position of the channel impurity to the surface of the channel region.

Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.

Abstract: A semiconductor device of an embodiment includes a nitride semiconductor layer, a first electrode provided on the nitride semiconductor layer, a second electrode provided on the nitride semiconductor layer, a third electrode provided above the nitride semiconductor layer, the third electrode provided between the first electrode and the second electrode, the third electrode containing a polycrystalline nitride semiconductor containing a p-type impurity, and a first insulating layer provided between the nitride semiconductor layer and the third electrode.

Abstract: A semiconductor device may include a semiconductor substrate. The semiconductor device may further include a gate electrode that overlaps the semiconductor substrate. The semiconductor device may further include a channel region that overlaps at least one of the gate electrode and the semiconductor substrate. The semiconductor device may further include a stress adjustment element that contacts the channel region and is positioned between the channel region and a surface of the semiconductor substrate in a direction perpendicular to the surface of the semiconductor substrate. A maximum width of the channel region in a direction parallel to the surface of the semiconductor substrate is greater than a maximum width of the stress adjustment element in the direction parallel to the surface of the semiconductor substrate in a cross-sectional view of the semiconductor device.

Abstract: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.

Abstract: An exemplary method includes forming a dummy gate structure over a substrate and forming a set of spacers adjacent to the dummy gate structure. The set of spacers includes spacer liners disposed on sidewalls of the dummy gate structure and main spacers disposed on the spacer liners. The spacer liners include silicon and carbon. The method further includes forming source/drain epitaxy regions over the substrate. The source/drain epitaxy regions are disposed adjacent to the set of spacers, such that the dummy gate structure is disposed between the source/drain epitaxy regions. The method further includes removing the main spacers after forming the source/drain epitaxy regions. The method further includes replacing the dummy gate structure with a gate structure, where the replacing includes removing the dummy gate structure to form a trench defined by the spacers liners, such that the gate structure is formed in the trench.

Abstract: A hybrid transistor circuit is disclosed for use in III-Nitride (III-N) semiconductor devices, comprising a Silicon (Si)-based Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a Group III-Nitride (III-N)-based Field-Effect Transistor (FET), and a driver unit. A source terminal of the III-N-based FET is connected to a drain terminal of the Si-based MOSFET. The driver unit has at least one input terminal, and two output terminals connected to the gate terminals of the transistors respectively. The hybrid transistor circuit is turned on through the driver unit by switching on the Silicon-based MOSFET first before switching on the III-N-based FET, and is turned off through the driver unit by switching off the III-N-based FET before switching off the Silicon-based MOSFET. Also disclosed are integrated circuit packages and semiconductor structures for forming such hybrid transistor circuits. The resulting hybrid circuit provides power-efficient and robust use of III-Nitride semiconductor devices.

Abstract: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.

Abstract: There is provided a method of manufacturing a Fin Field Effect Transistor (FinFET). The method may include: forming a fin on a semiconductor substrate; forming a dummy device including a dummy gate on the fin; forming an interlayer dielectric layer to cover regions except for the dummy gate; removing the dummy gate to form an opening; implanting ions to form a Punch-Through-Stop Layer (PTSL) in a portion of the fin directly under the opening, while forming reflection doped layers in portions of the fin on inner sides of source/drain regions; and forming a replacement gate in the opening.

Abstract: A fin field effect transistor (finFET) device and a method of fabricating a finFET are described. The method includes forming a replacement gate stack on a substrate between inside walls of sidewall spacers, epitaxially growing a raised source drain (RSD) on the substrate adjacent to outside walls of the sidewall spacers, and forming a silicide above the RSD and along the outside walls of the sidewall spacers. The method also includes depositing and polishing a contact metal above portions of the replacement gate stack and the RSD, the contact metal contacting the silicide along the outside walls of the sidewall spacers adjacent to the portions of the replacement gate stack.

Abstract: A method for forming a semiconductor device comprises, forming a fin on a semiconductor substrate, forming spacers adjacent to the fin, etching to remove exposed portions of the semiconductor substrate adjacent to the spacers to form a trench adjacent to the spacers, removing the spacers, implanting dopants in the semiconductor substrate adjacent to the fin and in the trench, and performing an annealing process to diffuse the dopants in the semiconductor substrate and form a punch through stopper region below the fin that includes the dopants.

Abstract: A memory device having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and wherein at least a portion of the channel region first portion is of the second conductivity type.

Abstract: One illustrative device disclosed includes, among other things, first and second active regions that are separated by an isolation region, first and second replacement gate structures positioned above the first and second active regions, respectively, and a gate registration structure positioned above the isolation region, wherein the gate registration structure comprises a layer of insulating material positioned above the isolation region and a polish-stop layer and wherein a first end surface of the first replacement gate structure abuts and engages a first side surface of the gate registration structure and a second end surface of the second replacement gate structure abuts and engages a second side surface of the gate registration structure.

Abstract: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.

Abstract: According to one embodiment, a semiconductor device includes first electrode and second electrodes, first, second, third, fifth, and fourth semiconductor regions, a third electrode, and a second insulating film. The first semiconductor region is provided between the first and second electrodes. The second semiconductor region is provided between the first semiconductor region and the first electrode. The third semiconductor region is provided between the first semiconductor region and the second electrode. The fifth semiconductor region is provided between the first semiconductor region and the second electrode. The fourth semiconductor region is provided between the third semiconductor region and the second electrode and between the fifth semiconductor region and the second electrode. The third electrode contacts the first, third, and fourth semiconductor regions via a first insulating film. The second insulating film contacts the first, fifth, and fourth semiconductor regions.

Abstract: Methods for forming gates without spacers and the resulting devices are disclosed. Embodiments may include forming a channel layer on a substrate; forming a dummy gate on the channel layer; forming an interlayer dielectric (ILD) on the channel layer and surrounding the dummy gate; forming a trench within the ILD and the channel layer by removing the dummy gate and the channel layer below the dummy gate; forming an un-doped channel region at the bottom of the trench; and forming a gate above the un-doped channel region within the trench.

Abstract: A method includes forming a dummy gate stack over a semiconductor substrate, removing the dummy gate stack to form a recess, and implanting a portion of the semiconductor substrate through the recess. During the implantation, an amorphous region is formed from the portion of the semiconductor substrate. The method further includes forming a strained capping layer, wherein the strained capping layer extends into the recess. An annealing is performed on the amorphous region to re-crystallize the amorphous region. The strained capping layer is then removed.

Abstract: One-transistor volatile memory devices and manufacturing methods thereof are provided. The device includes a substrate having top and bottom surfaces and an isolation well disposed below the top substrate surface. An area of the substrate between the isolation buffer layer and the top substrate surface serves as a body region of a transistor. The isolation well isolates the body region from the substrate. The device includes a band engineered (BE) floating body disposed over the isolation well and within the body region. The device also includes a transistor disposed over the substrate. The transistor includes a gate disposed on the top substrate surface, and first and second diffusion regions disposed in the body region adjacent to first and second sides of the gate.

Abstract: A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.

Abstract: A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough.

Abstract: One-transistor (1T) volatile memory devices and manufacturing methods thereof are provided. The device includes a substrate having top and bottom surfaces and an isolation buffer layer disposed below the top substrate surface. The isolation buffer layer is an amorphized portion of the substrate. An area of the substrate between the isolation buffer layer and the top substrate surface serves as a body region of a transistor. The device also includes a transistor disposed over the substrate. The transistor includes a gate disposed on the top substrate surface, and first and second diffusion regions disposed in the body region adjacent to first and second sides of the gate.

Abstract: An integrated circuit containing an analog MOS transistor has an implant mask for a well which blocks well dopants from two diluted regions at edges of the gate, but exposes a channel region to the well dopants. A thermal drive step diffuses the implanted well dopants across the two diluted regions to form a continuous well with lower doping densities in the two diluted regions. Source/drain regions are formed adjacent to and underlapping the gate by implanting source/drain dopants into the substrate adjacent to the gate using the gate as a blocking layer and subsequently annealing the substrate so that the implanted source/drain dopants provide a desired extent of underlap of the source/drain regions under the gate. Drain extension dopants and halo dopants are not implanted into the substrate adjacent to the gate.

Abstract: One embodiment of the present invention relates to a memory cell. The memory cell comprises a substrate and a stacked gate structure disposed on the substrate, wherein the stacked gate structure comprises a charge trapping dielectric layer that is adapted to store at least one bit of data. The memory cell further includes a source and drain in the substrate, wherein the source and drain are disposed at opposite sides of the stacked gate structure. A barrier region is disposed substantially beneath the source or the drain and comprises an inert species. Other embodiments are also disclosed.

Abstract: A MOS transistor including, above a gate insulator, a conductive gate stack having a height, a length, and a width, this stack having a lower portion close to the gate insulator and an upper portion, wherein the stack has a first length in its lower portion, and a second length shorter than the first length in its upper portion.

Abstract: A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth around a gate structure on the semiconductor layer, forming a disposable spacer around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth greater than the first depth. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region. A replacement gate structure can be formed after deposition and planarization of a planarization dielectric layer and subsequent removal of the gate structure and laterally expand the gate cavity over epitaxial source and drain extension regions. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein.

Abstract: A disposable gate structure straddling a semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask. A planarization dielectric layer is formed such that a top surface of the planarization dielectric layer is coplanar with the disposable gate structure. A gate cavity is formed by removing the disposable gate structure. An epitaxial cap layer is deposited on physically exposed semiconductor surfaces of the semiconductor fin by selective epitaxy. A gate dielectric layer is formed on the epitaxial cap layer, and a gate electrode can be formed by filling the gate cavity. The epitaxial cap layer can include a material that reduces the density of interfacial defects at an interface with the gate dielectric layer.

Abstract: A method for manufacturing a semiconductor device, includes forming a first gate oxide film in each of a first region and a second region by thermally oxidizing a silicon substrate, forming a CVD oxide film on the first gate oxide film, implanting fluorine into each of the first region and the second region through the CVD oxide film and the first gate oxide film, removing the CVD oxide film from the first gate oxide film in the second region, removing the first gate oxide film from the second region, and forming a second gate oxide film in the second region by thermally oxidizing the silicon substrate.

Abstract: Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching.

Abstract: A surface channel transistor is provided in a semiconductive device. The surface channel transistor is either a PMOS or an NMOS device. Epitaxial layers are disposed above the surface channel transistor to cause an increased bandgap phenomenon nearer the surface of the device. A process of forming the surface channel transistor includes grading the epitaxial layers.

Abstract: The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a plurality of gate stacks formed on the semiconductor substrate and configured as an alignment mark; doped features formed in the semiconductor substrate and disposed on sides of each of the plurality of gate stacks; and channel regions underlying the plurality of gate stacks and free of channel dopant.

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided herein. In an embodiment, a semiconductor device includes a semiconductor substrate. A source region and a drain region are disposed in the semiconductor substrate. A channel region is defined in the semiconductor substrate between the source region and the drain region. A gate dielectric layer overlies the channel region of the semiconductor substrate, and a gate electrode overlies the gate dielectric layer. The channel region includes a first carbon-containing layer, a doped layer overlying the first carbon-containing layer, a second carbon-containing layer overlying the doped layer, and an intrinsic semiconductor layer overlying the second carbon-containing layer. The doped layer includes a dopant that is different than carbon.

Abstract: Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel.

Abstract: Provided are methods for making metal gates suitable for FinFET structures. The methods described herein generally involve forming a high-k dielectric material on a semiconductor substrate; depositing a high-k dielectric cap layer over the high-k dielectric material; depositing a PMOS work function layer having a positive work function value; depositing an NMOS work function layer; depositing an NMOS work function cap layer over the NMOS work function layer; removing at least a portion of the PMOS work function layer or at least a portion of the NMOS work function layer; and depositing a fill layer. Depositing a high-k dielectric cap layer, depositing a PMOS work function layer or depositing a NMOS work function cap layer may comprise atomic layer deposition of TiN, TiSiN, or TiAlN. Either PMOS or NMOS may be deposited first.

Abstract: A liquid crystal display device and method for manufacturing the same are provided. A liquid crystal display (LCD) with a touch function includes: a pixel thin film transistor (TFT) in a display area, and a buffer TFT of a gate driver in a non-display area, wherein a lightly-doped drain (LDD) length of the buffer TFT is shorter than a lightly doped drain (LDD) length of the pixel TFT.