Doping Of Semiconductive Channel Region Beneath Gate Insulator (e.g., Adjusting Threshold Voltage, Etc.) Patents (Class 438/289)
  • Patent number: 10355112
    Abstract: In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI) core formed on the buried oxide layer, a compressive strained quantum well (QW) layer wrapped around the SOI core, and a tensile strained silicon layer wrapped around the QW layer. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 16, 2019
    Assignee: Intel Corporation
    Inventors: Chi On Chui, Prashant Majhi, Wilman Tsai, Jack T. Kavalieros
  • Patent number: 10290731
    Abstract: A semiconductor device of an embodiment includes a nitride semiconductor layer, a first electrode provided on the nitride semiconductor layer, a second electrode provided on the nitride semiconductor layer, a third electrode provided above the nitride semiconductor layer, the third electrode provided between the first electrode and the second electrode, the third electrode containing a polycrystalline nitride semiconductor containing a p-type impurity, and a first insulating layer provided between the nitride semiconductor layer and the third electrode.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: May 14, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisashi Saito, Tatsuo Shimizu
  • Patent number: 10211289
    Abstract: A semiconductor device may include a semiconductor substrate. The semiconductor device may further include a gate electrode that overlaps the semiconductor substrate. The semiconductor device may further include a channel region that overlaps at least one of the gate electrode and the semiconductor substrate. The semiconductor device may further include a stress adjustment element that contacts the channel region and is positioned between the channel region and a surface of the semiconductor substrate in a direction perpendicular to the surface of the semiconductor substrate. A maximum width of the channel region in a direction parallel to the surface of the semiconductor substrate is greater than a maximum width of the stress adjustment element in the direction parallel to the surface of the semiconductor substrate in a cross-sectional view of the semiconductor device.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: February 19, 2019
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Meng Zhao
  • Patent number: 10177249
    Abstract: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Benjamin Chu-Kung, Mantu K. Hudait, Marko Radosavljevic, Jack T. Kavalieros, Willy Rachmady, Niloy Mukherjee, Robert S. Chau
  • Patent number: 10164093
    Abstract: An exemplary method includes forming a dummy gate structure over a substrate and forming a set of spacers adjacent to the dummy gate structure. The set of spacers includes spacer liners disposed on sidewalls of the dummy gate structure and main spacers disposed on the spacer liners. The spacer liners include silicon and carbon. The method further includes forming source/drain epitaxy regions over the substrate. The source/drain epitaxy regions are disposed adjacent to the set of spacers, such that the dummy gate structure is disposed between the source/drain epitaxy regions. The method further includes removing the main spacers after forming the source/drain epitaxy regions. The method further includes replacing the dummy gate structure with a gate structure, where the replacing includes removing the dummy gate structure to form a trench defined by the spacers liners, such that the gate structure is formed in the trench.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
  • Patent number: 9754937
    Abstract: A hybrid transistor circuit is disclosed for use in III-Nitride (III-N) semiconductor devices, comprising a Silicon (Si)-based Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a Group III-Nitride (III-N)-based Field-Effect Transistor (FET), and a driver unit. A source terminal of the III-N-based FET is connected to a drain terminal of the Si-based MOSFET. The driver unit has at least one input terminal, and two output terminals connected to the gate terminals of the transistors respectively. The hybrid transistor circuit is turned on through the driver unit by switching on the Silicon-based MOSFET first before switching on the III-N-based FET, and is turned off through the driver unit by switching off the III-N-based FET before switching off the Silicon-based MOSFET. Also disclosed are integrated circuit packages and semiconductor structures for forming such hybrid transistor circuits. The resulting hybrid circuit provides power-efficient and robust use of III-Nitride semiconductor devices.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: September 5, 2017
    Assignee: Cambridge Electronics, Inc.
    Inventors: Bin Lu, Ling Xia
  • Patent number: 9704981
    Abstract: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: July 11, 2017
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Benjamin Chu-Kung, Mantu K. Hudait, Marko Radosavljevic, Jack T. Kavalieros, Willy Rachmady, Niloy Mukherjee, Robert S. Chau
  • Patent number: 9679962
    Abstract: There is provided a method of manufacturing a Fin Field Effect Transistor (FinFET). The method may include: forming a fin on a semiconductor substrate; forming a dummy device including a dummy gate on the fin; forming an interlayer dielectric layer to cover regions except for the dummy gate; removing the dummy gate to form an opening; implanting ions to form a Punch-Through-Stop Layer (PTSL) in a portion of the fin directly under the opening, while forming reflection doped layers in portions of the fin on inner sides of source/drain regions; and forming a replacement gate in the opening.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: June 13, 2017
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Miao Xu, Huilong Zhu, Lichuan Zhao
  • Patent number: 9577096
    Abstract: A fin field effect transistor (finFET) device and a method of fabricating a finFET are described. The method includes forming a replacement gate stack on a substrate between inside walls of sidewall spacers, epitaxially growing a raised source drain (RSD) on the substrate adjacent to outside walls of the sidewall spacers, and forming a silicide above the RSD and along the outside walls of the sidewall spacers. The method also includes depositing and polishing a contact metal above portions of the replacement gate stack and the RSD, the contact metal contacting the silicide along the outside walls of the sidewall spacers adjacent to the portions of the replacement gate stack.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: February 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Effendi Leobandung, Soon-Cheon Seo, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 9508833
    Abstract: A method for forming a semiconductor device comprises, forming a fin on a semiconductor substrate, forming spacers adjacent to the fin, etching to remove exposed portions of the semiconductor substrate adjacent to the spacers to form a trench adjacent to the spacers, removing the spacers, implanting dopants in the semiconductor substrate adjacent to the fin and in the trench, and performing an annealing process to diffuse the dopants in the semiconductor substrate and form a punch through stopper region below the fin that includes the dopants.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: November 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Effendi Leobandung, Tenko Yamashita
  • Patent number: 9466732
    Abstract: A memory device having a substrate of semiconductor material of a first conductivity type, first and second spaced-apart regions in the substrate of a second conductivity type, with a channel region in the substrate therebetween, a conductive floating gate over and insulated from the substrate, wherein the floating gate is disposed at least partially over the first region and a first portion of the channel region, a conductive second gate laterally adjacent to and insulated from the floating gate, wherein the second gate is disposed at least partially over and insulated from a second portion of the channel region, and wherein at least a portion of the channel region first portion is of the second conductivity type.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: October 11, 2016
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventor: Yuri Tkachev
  • Patent number: 9412740
    Abstract: One illustrative device disclosed includes, among other things, first and second active regions that are separated by an isolation region, first and second replacement gate structures positioned above the first and second active regions, respectively, and a gate registration structure positioned above the isolation region, wherein the gate registration structure comprises a layer of insulating material positioned above the isolation region and a polish-stop layer and wherein a first end surface of the first replacement gate structure abuts and engages a first side surface of the gate registration structure and a second end surface of the second replacement gate structure abuts and engages a second side surface of the gate registration structure.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: August 9, 2016
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Ruilong Xie, Michael Wedlake, Xiuyu Cai, Ali Khakifirooz, Kangguo Cheng
  • Patent number: 9356099
    Abstract: Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: May 31, 2016
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Benjamin Chu-Kung, Mantu K. Hudait, Marko Radosavljevic, Jack T. Kavalieros, Willy Rachmady, Niloy Mukherjee, Robert S. Chau
  • Patent number: 9349853
    Abstract: According to one embodiment, a semiconductor device includes first electrode and second electrodes, first, second, third, fifth, and fourth semiconductor regions, a third electrode, and a second insulating film. The first semiconductor region is provided between the first and second electrodes. The second semiconductor region is provided between the first semiconductor region and the first electrode. The third semiconductor region is provided between the first semiconductor region and the second electrode. The fifth semiconductor region is provided between the first semiconductor region and the second electrode. The fourth semiconductor region is provided between the third semiconductor region and the second electrode and between the fifth semiconductor region and the second electrode. The third electrode contacts the first, third, and fourth semiconductor regions via a first insulating film. The second insulating film contacts the first, fifth, and fourth semiconductor regions.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: May 24, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kohei Morizuka
  • Patent number: 9324831
    Abstract: Methods for forming gates without spacers and the resulting devices are disclosed. Embodiments may include forming a channel layer on a substrate; forming a dummy gate on the channel layer; forming an interlayer dielectric (ILD) on the channel layer and surrounding the dummy gate; forming a trench within the ILD and the channel layer by removing the dummy gate and the channel layer below the dummy gate; forming an un-doped channel region at the bottom of the trench; and forming a gate above the un-doped channel region within the trench.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: April 26, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Gerd Zschätzsch, Stefan Flachowsky, Jan Hoentschel
  • Patent number: 9287269
    Abstract: One-transistor volatile memory devices and manufacturing methods thereof are provided. The device includes a substrate having top and bottom surfaces and an isolation well disposed below the top substrate surface. An area of the substrate between the isolation buffer layer and the top substrate surface serves as a body region of a transistor. The isolation well isolates the body region from the substrate. The device includes a band engineered (BE) floating body disposed over the isolation well and within the body region. The device also includes a transistor disposed over the substrate. The transistor includes a gate disposed on the top substrate surface, and first and second diffusion regions disposed in the body region adjacent to first and second sides of the gate.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: March 15, 2016
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Eng Huat Toh, Danny Pak-Chum Shum, Shyue Seng Tan
  • Patent number: 9287139
    Abstract: A method includes forming a dummy gate stack over a semiconductor substrate, removing the dummy gate stack to form a recess, and implanting a portion of the semiconductor substrate through the recess. During the implantation, an amorphous region is formed from the portion of the semiconductor substrate. The method further includes forming a strained capping layer, wherein the strained capping layer extends into the recess. An annealing is performed on the amorphous region to re-crystallize the amorphous region. The strained capping layer is then removed.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Shang Hsiao, Cing-Yao Chan, Chun-Ying Wang, Jen-Pan Wang
  • Patent number: 9263346
    Abstract: A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: February 16, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Takaaki Tsunomura, Toshiaki Iwamatsu
  • Patent number: 9240354
    Abstract: A semiconductor-on-insulator (SOI) substrate comprises a bulk semiconductor substrate, a buried insulator layer formed on the bulk substrate and an active semiconductor layer formed on the buried insulator layer. Impurities are implanted near the interface of the buried insulator layer and the active semiconductor layer. A diffusion barrier layer is formed between the impurities and an upper surface of the active semiconductor layer. The diffusion barrier layer prevents the impurities from diffusing therethrough.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: January 19, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Gregory G. Freeman, Kam Leung Lee, Chengwen Pei, Geng Wang, Yanli Zhang
  • Patent number: 9184165
    Abstract: One-transistor (1T) volatile memory devices and manufacturing methods thereof are provided. The device includes a substrate having top and bottom surfaces and an isolation buffer layer disposed below the top substrate surface. The isolation buffer layer is an amorphized portion of the substrate. An area of the substrate between the isolation buffer layer and the top substrate surface serves as a body region of a transistor. The device also includes a transistor disposed over the substrate. The transistor includes a gate disposed on the top substrate surface, and first and second diffusion regions disposed in the body region adjacent to first and second sides of the gate.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: November 10, 2015
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Danny Pak-Chum Shum, Shyue Seng Tan
  • Patent number: 9184163
    Abstract: An integrated circuit containing an analog MOS transistor has an implant mask for a well which blocks well dopants from two diluted regions at edges of the gate, but exposes a channel region to the well dopants. A thermal drive step diffuses the implanted well dopants across the two diluted regions to form a continuous well with lower doping densities in the two diluted regions. Source/drain regions are formed adjacent to and underlapping the gate by implanting source/drain dopants into the substrate adjacent to the gate using the gate as a blocking layer and subsequently annealing the substrate so that the implanted source/drain dopants provide a desired extent of underlap of the source/drain regions under the gate. Drain extension dopants and halo dopants are not implanted into the substrate adjacent to the gate.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: November 10, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Sameer Pendharkar
  • Patent number: 9171936
    Abstract: One embodiment of the present invention relates to a memory cell. The memory cell comprises a substrate and a stacked gate structure disposed on the substrate, wherein the stacked gate structure comprises a charge trapping dielectric layer that is adapted to store at least one bit of data. The memory cell further includes a source and drain in the substrate, wherein the source and drain are disposed at opposite sides of the stacked gate structure. A barrier region is disposed substantially beneath the source or the drain and comprises an inert species. Other embodiments are also disclosed.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: October 27, 2015
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Shankar Sinha, Yi He, Zhizheng Liu, Ming-Sang Kwan
  • Patent number: 9117805
    Abstract: A MOS transistor including, above a gate insulator, a conductive gate stack having a height, a length, and a width, this stack having a lower portion close to the gate insulator and an upper portion, wherein the stack has a first length in its lower portion, and a second length shorter than the first length in its upper portion.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: August 25, 2015
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS, Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Heimanu Niebojewski, Yves Morand, Cyrille Le Royer
  • Patent number: 9093466
    Abstract: A pair of horizontal-step-including trenches are formed in a semiconductor layer by forming a pair of first trenches having a first depth around a gate structure on the semiconductor layer, forming a disposable spacer around the gate structure to cover proximal portions of the first trenches, and by forming a pair of second trenches to a second depth greater than the first depth. The disposable spacer is removed, and selective epitaxy is performed to form an integrated epitaxial source and source extension region and an integrated epitaxial drain and drain extension region. A replacement gate structure can be formed after deposition and planarization of a planarization dielectric layer and subsequent removal of the gate structure and laterally expand the gate cavity over epitaxial source and drain extension regions. Alternately, a contact-level dielectric layer can be deposited directly on the integrated epitaxial regions and contact via structures can be formed therein.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: July 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Chengwen Pei, Geng Wang, Yanli Zhang
  • Patent number: 9070770
    Abstract: A disposable gate structure straddling a semiconductor fin is formed. A source region and a drain region are formed employing the disposable gate structure as an implantation mask. A planarization dielectric layer is formed such that a top surface of the planarization dielectric layer is coplanar with the disposable gate structure. A gate cavity is formed by removing the disposable gate structure. An epitaxial cap layer is deposited on physically exposed semiconductor surfaces of the semiconductor fin by selective epitaxy. A gate dielectric layer is formed on the epitaxial cap layer, and a gate electrode can be formed by filling the gate cavity. The epitaxial cap layer can include a material that reduces the density of interfacial defects at an interface with the gate dielectric layer.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: June 30, 2015
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Guy Cohen, Amlan Majumdar
  • Patent number: 9034702
    Abstract: Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: May 19, 2015
    Assignee: Peking University
    Inventors: Ru Huang, Jiewen Fan, Yujie Ai, Shuai Sun, Runsheng Wang, Jibin Zou, Xin Huang
  • Patent number: 9034709
    Abstract: A method for manufacturing a semiconductor device, includes forming a first gate oxide film in each of a first region and a second region by thermally oxidizing a silicon substrate, forming a CVD oxide film on the first gate oxide film, implanting fluorine into each of the first region and the second region through the CVD oxide film and the first gate oxide film, removing the CVD oxide film from the first gate oxide film in the second region, removing the first gate oxide film from the second region, and forming a second gate oxide film in the second region by thermally oxidizing the silicon substrate.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: May 19, 2015
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Shogo Katsuki, Toshiro Sakamoto
  • Publication number: 20150111358
    Abstract: A surface channel transistor is provided in a semiconductive device. The surface channel transistor is either a PMOS or an NMOS device. Epitaxial layers are disposed above the surface channel transistor to cause an increased bandgap phenomenon nearer the surface of the device. A process of forming the surface channel transistor includes grading the epitaxial layers.
    Type: Application
    Filed: September 29, 2014
    Publication date: April 23, 2015
    Inventors: Ravi PILLARISETTY, Mantu K. HUDAIT, Marko RADOSAVLJEVIC, Gilbert DEWEY, Jack T. KAVALIEROS
  • Patent number: 9000525
    Abstract: The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a plurality of gate stacks formed on the semiconductor substrate and configured as an alignment mark; doped features formed in the semiconductor substrate and disposed on sides of each of the plurality of gate stacks; and channel regions underlying the plurality of gate stacks and free of channel dopant.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chang Wen, Hsien-Cheng Wang, Chun-Kuang Chen
  • Patent number: 8994107
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided herein. In an embodiment, a semiconductor device includes a semiconductor substrate. A source region and a drain region are disposed in the semiconductor substrate. A channel region is defined in the semiconductor substrate between the source region and the drain region. A gate dielectric layer overlies the channel region of the semiconductor substrate, and a gate electrode overlies the gate dielectric layer. The channel region includes a first carbon-containing layer, a doped layer overlying the first carbon-containing layer, a second carbon-containing layer overlying the doped layer, and an intrinsic semiconductor layer overlying the second carbon-containing layer. The doped layer includes a dopant that is different than carbon.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: March 31, 2015
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: El Mehdi Bazizi, Francis Benistant
  • Patent number: 8993424
    Abstract: Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Wen Liu, Tsung-Hsing Yu, Dhanyakumar Mahaveer Sathaiya, Wei-Hao Wu, Ken-Ichi Goto, Tzer-Min Shen, Zhiqiang Wu
  • Patent number: 8987080
    Abstract: Provided are methods for making metal gates suitable for FinFET structures. The methods described herein generally involve forming a high-k dielectric material on a semiconductor substrate; depositing a high-k dielectric cap layer over the high-k dielectric material; depositing a PMOS work function layer having a positive work function value; depositing an NMOS work function layer; depositing an NMOS work function cap layer over the NMOS work function layer; removing at least a portion of the PMOS work function layer or at least a portion of the NMOS work function layer; and depositing a fill layer. Depositing a high-k dielectric cap layer, depositing a PMOS work function layer or depositing a NMOS work function cap layer may comprise atomic layer deposition of TiN, TiSiN, or TiAlN. Either PMOS or NMOS may be deposited first.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: March 24, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Xinliang Lu, Seshadri Ganguli, Atif Noori, Maitreyee Mahajani, Shih Chung Chen, Yu Lei, Xinyu Fu, Wei Tang, Srinivas Gandikota
  • Patent number: 8988626
    Abstract: A liquid crystal display device and method for manufacturing the same are provided. A liquid crystal display (LCD) with a touch function includes: a pixel thin film transistor (TFT) in a display area, and a buffer TFT of a gate driver in a non-display area, wherein a lightly-doped drain (LDD) length of the buffer TFT is shorter than a lightly doped drain (LDD) length of the pixel TFT.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: March 24, 2015
    Assignee: LG Display Co., Ltd.
    Inventor: Sangwon Lee
  • Patent number: 8981490
    Abstract: A method of fabricating a CMOS integrated circuit (IC) includes implanting a first n-type dopant at a first masking level that exposes a p-region of a substrate surface having a first gate stack thereon to form NLDD regions for forming n-source/drain extension regions for at least a portion of a plurality of n-channel MOS (NMOS) transistors on the IC. A p-type dopant is implanted at a second masking level that exposes an n-region in the substrate surface having a second gate stack thereon to form PLDD regions for at least a portion of a plurality of p-channel MOS (PMOS) transistors on the IC. A second n-type dopant is retrograde implanted including through the first gate stack to form a deep nwell (DNwell) for the portion of NMOS transistors. A depth of the DNwell is shallower below the first gate stack as compared to under the NLDD regions.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: March 17, 2015
    Assignee: Texas Instruments Incorporated
    Inventor: Mahalingam Nandakumar
  • Patent number: 8975707
    Abstract: A region for substrate potential is formed of an n-type well at a position in the direction of a channel length relative to the gate electrode and the position is between drain regions in the direction of a channel width. An n-type of a contact region with a higher concentration of n-type impurity than that of the region is provided in the region. The contact region is arranged away from the drain regions with a distance to obtain a desired breakdown voltage of PN-junction between the region and the drain region.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: March 10, 2015
    Assignee: Ricoh Company, Ltd.
    Inventor: Masaya Ohtsuka
  • Patent number: 8962426
    Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor layer of a first conductivity type and forming a semiconductor layer of a second conductivity type thereon. The method also includes forming an insulator layer on the semiconductor layer of the second conductivity type, etching a trench into at least the semiconductor layer of the second conductivity type, and forming a thermal oxide layer in the trench and on the semiconductor layer of the second conductivity type. The method further includes implanting ions into the thermal oxide layer, forming a second insulator layer, removing the second insulator layer from a portion of the trench, and forming an oxide layer in the trench and on the epitaxial layer. Moreover, the method includes forming a material in the trench, forming a second gate oxide layer over the material, and patterning the second gate oxide layer.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: February 24, 2015
    Assignee: MaxPower Semiconductor Inc.
    Inventor: Mohamed N. Darwish
  • Patent number: 8939765
    Abstract: In sophisticated semiconductor devices, the defect rate that may typically be associated with the provision of a silicon/germanium material in the active region of P-channel transistors may be significantly decreased by incorporating a carbon species prior to or during the selective epitaxial growth of the silicon/germanium material. In some embodiments, the carbon species may be incorporated during the selective growth process, while in other cases an ion implantation process may be used. In this case, superior strain conditions may also be obtained in N-channel transistors.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: January 27, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Peter Javorka, Maciej Wiatr, Roman Boschke, Christian Krueger
  • Patent number: 8941092
    Abstract: Disclosed are a method which improves the performance of a semiconductor element, and a semiconductor element with improved performance. The method for forming a semiconductor element structure includes a heterojunction forming step in which a heterojunction is formed between a strained semiconductor layer (21) in which a strained state is maintained, and relaxed semiconductor layers (23, 25). The heterojunction is formed by performing ion implantation from the surface of a substrate (50) which has a strained semiconductor layer (20) partially covered with a covering layer (30) on an insulating oxide film (40), and altering the strained semiconductor layer (20) where there is no shielding from the covering layer (30) to relaxed semiconductor layers (23, 25) by relaxing the strained state of the strained semiconductor layer (20), while maintaining the strained state of the strained semiconductor layer (21) where there is shielding from the covering layer (30).
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: January 27, 2015
    Assignee: Kanagawa University
    Inventor: Tomohisa Mizuno
  • Patent number: 8937358
    Abstract: An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The first channel region has a first channel doping concentration. The second standard cell includes a second gate electrode, and a second channel region underlying the second gate electrode. The second channel region has a second channel doping concentration. A dummy gate includes a first half and a second half in the first and the second standard cells, respectively. The first half and the second half are at the edges of the first and the second standard cells, respectively, and are abutted to each other. A dummy channel is overlapped by the dummy gate. The dummy channel has a third channel doping concentration substantially equal to a sum of the first channel doping concentration and the second channel doping concentration.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: January 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang-Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang
  • Publication number: 20150011056
    Abstract: Variation resistant metal-oxide-semiconductor field effect transistors (MOSFET) are manufactured using a high-K, metal-gate ‘channel-last’ process. Between spacers formed over a well area having separate drain and source areas, a recess in the underlying is formed using a crystallographic etch to provide [111] boundaries adjacent the source and drain regions. An ion implant step localized by the cavity results in a localized increase in well-doping directly beneath the recess. Within the recess, an active region is formed using an un-doped or lightly doped epitaxial layer, deposited at a very low temperature. A high-K dielectric stack is formed over the lightly doped epitaxial layer, over which a metal gate is formed within the cavity boundaries.
    Type: Application
    Filed: July 3, 2014
    Publication date: January 8, 2015
    Inventors: Ashok K. Kapoor, Asen Asenov
  • Publication number: 20150008448
    Abstract: A semiconductor device includes a drift layer disposed on a substrate. The drift layer has a non-planar surface having a plurality of repeating features oriented parallel to a length of a channel of the semiconductor device. Further, each the repeating features have a dopant concentration higher than a remainder of the drift layer.
    Type: Application
    Filed: July 2, 2013
    Publication date: January 8, 2015
    Inventors: Alexander Viktorovich Bolotnikov, Peter Almern Losee
  • Patent number: 8927409
    Abstract: An apparatus includes a wafer annealing tool and a plurality of electrodes coupled to the wafer annealing tool, wherein the electrodes are configured to be in physical contact with a wafer so that, when the wafer is annealed, a negative electrical bias is formed across one or more gate stacks of the wafer.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventor: Martin M. Frank
  • Publication number: 20150001640
    Abstract: One illustrative device disclosed herein includes a plurality of source/drain regions positioned in an active region on opposite sides of a gate structure, each of the source/drain regions having a lateral width in a gate length direction of the transistor and a plurality of halo regions, wherein each of the halo regions is positioned under a portion, but not all, of the lateral width of one of the plurality of source/drain regions. A method disclosed herein includes forming a plurality of halo implant regions in an active region, wherein an outer edge of each of the halo implant regions is laterally spaced apart from an adjacent inner edge of an isolation region.
    Type: Application
    Filed: June 26, 2013
    Publication date: January 1, 2015
    Inventors: Jerome Ciavatti, Johannes M. van Meer
  • Patent number: 8921181
    Abstract: Methods for forming an electronic device having a fluorine-stabilized semiconductor substrate surface are disclosed. In an exemplary embodiment, a layer of a high-? dielectric material is formed together with a layer containing fluorine on a semiconductor substrate. Subsequent annealing causes the fluorine to migrate to the surface of the semiconductor (for example, silicon, germanium, or silicon-germanium). A thin interlayer of a semiconductor oxide may also be present at the semiconductor surface. The fluorine-containing layer can comprise F-containing WSix formed by ALD from WF6 and SiH4 precursor gases. A precise amount of F can be provided, sufficient to bind to substantially all of the dangling semiconductor atoms at the surface of the semiconductor substrate and sufficient to displace substantially all of the hydrogen atoms present at the surface of the semiconductor substrate.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: December 30, 2014
    Assignee: Intermolecular, Inc.
    Inventor: Dipankar Pramanik
  • Patent number: 8921950
    Abstract: A semiconductor device includes a gate electrode formed on a nitride semiconductor layer, and a source electrode and a drain electrode provided on the nitride semiconductor layer so as to interpose the gate electrode therebetween, a first silicon nitride film that covers the gate electrode and the silicon nitride film and has a composition ratio of silicon to nitrogen equal to or larger than 0.75, the first silicon nitride film having compressive stress solely, and a second silicon nitride film that is formed on the first silicon nitride film and has a composition ratio of silicon to nitrogen equal to or larger than 0.75 solely, a whole stacked layer structure of the first and second silicon nitride films having tensile stress.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: December 30, 2014
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventors: Tsutomu Komatani, Shunsuke Kurachi
  • Patent number: 8921949
    Abstract: A MOS P-N junction diode includes a semiconductor substrate, a mask layer, a guard ring, a gate oxide layer, a polysilicon structure, a central conductive layer, a silicon nitride layer, a metal diffusion layer, a channel region, and a metal sputtering layer. For manufacturing the MOS P-N junction diode, a mask layer is formed on a semiconductor substrate. A gate oxide layer is formed on the semiconductor substrate, and a polysilicon structure is formed on the gate oxide layer. A guard ring, a central conductive layer and a channel region are formed in the semiconductor substrate. A silicon nitride layer is formed on the central conductive layer. A metal diffusion layer is formed within the guard ring and the central conductive layer. Afterwards, a metal sputtering layer is formed, and the mask layer is partially exposed.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: December 30, 2014
    Assignee: PFC Device Corp.
    Inventors: Kou-Liang Chao, Hung-Hsin Kuo, Tse-Chuan Su, Mei-Ling Chen
  • Publication number: 20140377926
    Abstract: A fin type active pattern is formed on a substrate. The fin type active pattern projects from the substrate. A diffusion film is formed on the fin type active pattern. The diffusion film includes an impurity. The impurity is diffused into a lower portion of the fin type active pattern to form a punch-through stopper diffusion layer.
    Type: Application
    Filed: June 3, 2014
    Publication date: December 25, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-Gon KIM, Jong-Hoon Kang, Eun-Young Jo, Gil-Heyun Choi, Han-Mei Choi
  • Publication number: 20140367776
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a well region disposed in a substrate, a gate disposed on the substrate, a halo region disposed in a channel region under the gate, and a source LDD region and a drain LDD region disposed on opposite sides of the halo region.
    Type: Application
    Filed: December 20, 2013
    Publication date: December 18, 2014
    Applicant: MAGNACHIP SEMICONDUCTOR, LTD.
    Inventor: Yon Sup PANG
  • Publication number: 20140361367
    Abstract: A semiconductor device includes a substrate having a first type doping. The semiconductor device further includes a first deep well in the substrate, the first deep well having a second type doping. The semiconductor device further includes a second deep well in the substrate, the second deep well having the second type doping and being separated and above the first deep well. The semiconductor device further includes a first well over the second deep well, the first well having the first type doping and a gate structure over the first well.
    Type: Application
    Filed: June 10, 2013
    Publication date: December 11, 2014
    Inventors: Hua-Chou TSENG, Chien-Chih HO
  • Publication number: 20140353732
    Abstract: A semiconductor device and method for manufacturing the same, wherein the method includes fabrication of field effect transistors (FET). The method includes growing a doped epitaxial halo region in a plurality of sigma-shaped source and drain recesses within a semiconductor substrate. An epitaxial stressor material is grown within the sigma-shaped source and drain recesses surrounded by the doped epitaxial halo forming source and drain regions with controlled current depletion towards the channel region to improve device performance. Selective growth of epitaxial regions allows for control of dopants profile and hence tailored and enhanced carrier mobility within the device.
    Type: Application
    Filed: May 31, 2013
    Publication date: December 4, 2014
    Inventors: Thomas N. Adam, Keith E. Fogel, Judson R. Holt, Balasubramanian Pranatharthiharan, Alexander Reznicek