After Formation Of Source Or Drain Regions And Gate Electrode Patents (Class 438/290)
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Publication number: 20120235213Abstract: The present invention provides a semiconductor structure with a stressed layer in the channel and method for forming the same. The semiconductor structure comprises a substrate; a gate stack, including a gate dielectric layer formed over the substrate, gate layer formed over the gate dielectric layer, a source region and a drain region formed in the substrate by both sides of the gate stack; one or more spacers formed on both sides of the gate stack; and an embedded stressed layer formed under the gate stack in the substrate. In the embodiments of the present invention, the carrier mobility can be effectively increased by the embedded stressed layer added in the channel under the gate stack, so that the driving current of transistors is improved. Moreover, the technological process for forming this embedded stressed layer in the present invention has a lower thermal budget, which therefore assists in maintaining a higher stress level in the channel region.Type: ApplicationFiled: June 24, 2010Publication date: September 20, 2012Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCESInventors: Haizhou Yin, Huilong Zhu, Zhijiong Luo
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Patent number: 8258035Abstract: A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion (215) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant (253, 254).Type: GrantFiled: May 4, 2007Date of Patent: September 4, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Leo Mathew, John J. Hackenberg, David C. Sing, Tab A. Stephens, Daniel G. Tekleab, Vishal P. Trivedi
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Publication number: 20120214286Abstract: A method for fabricating an NMOS transistor includes providing a substrate; forming a gate dielectric layer structure on the substrate and forming a gate electrode on the gate dielectric layer structure. The method further includes performing a fluorine ion implantation below the gate dielectric layer and an annealing process in an atmosphere comprising hydrogen or hydrogen plasma. The method also includes forming a source region and a drain region on both sides of the gate electrode before or after the fluorine ion implantation.Type: ApplicationFiled: June 28, 2011Publication date: August 23, 2012Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventors: YANGKUI LIN, Zhihao Chen
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Patent number: 8236641Abstract: A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film.Type: GrantFiled: June 24, 2011Date of Patent: August 7, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takayuki Ito, Kyoichi Suguro, Kouji Matsuo
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Patent number: 8216903Abstract: A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a substrate having a first concentration of a first conductivity type (P-well). A gate region (500) having a length and a width is formed on the dielectric region. Source (512) and drain (504) regions having a second conductivity type (N+) are formed in the substrate on opposite sides of the gate region. A first impurity region (508) having the first conductivity type (P+) is formed adjacent the source. The first impurity region has a second concentration greater than the first concentration.Type: GrantFiled: September 29, 2005Date of Patent: July 10, 2012
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Patent number: 8211773Abstract: A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a substrate having a first concentration of a first conductivity type (P-well). A gate region (500) having a length and a width is formed on the dielectric region. Source (512) and drain (504) regions having a second conductivity type (N+) are formed in the substrate on opposite sides of the gate region. A first impurity region (508) having the first conductivity type (P+) is formed adjacent the source. The first impurity region has a second concentration greater than the first concentration.Type: GrantFiled: July 28, 2009Date of Patent: July 3, 2012
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Publication number: 20120139051Abstract: A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3, or alternatively, less than one-quarter the dopant concentration of the source and the drain.Type: ApplicationFiled: December 3, 2010Publication date: June 7, 2012Applicant: SULVOLTA, INC.Inventors: Pushkar Ranade, Lucian Shifren, Sachin R. Sonkusale
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Patent number: 8193060Abstract: Provided is a method for manufacturing a semiconductor device. A well region formed on a semiconductor substrate includes a plurality of trench regions, and a source electrode is connected to a source region formed on a substrate surface between the trench regions. Adjacently to the source region, a high concentration region is formed, which is brought into butting contact with the source electrode together with the source region, whereby a substrate potential is fixed. A drain region is formed at a bottom portion of the trench region, whose potential is taken to the substrate surface by a drain electrode buried inside the trench region. An arbitrary voltage is applied to a gate electrode, and the drain electrode, whereby carriers flow from the source region to the drain region and the semiconductor device is in an on-state.Type: GrantFiled: November 18, 2010Date of Patent: June 5, 2012Assignee: Seiko Instruments Inc.Inventor: Tomomitsu Risaki
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Patent number: 8158482Abstract: An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor.Type: GrantFiled: September 2, 2009Date of Patent: April 17, 2012Assignee: GLOBALFOUNDRIES Inc.Inventors: Jan Hoentschel, Uwe Griebenow, Maciej Wiatr
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Publication number: 20120080752Abstract: A high voltage metal-oxide-semiconductor (HVMOS) transistor includes a gate poly, wherein a channel is formed in an area projected from the gate poly in a thickness direction when the HVMOS is activated; two carrier drain drift regions, adjacent to the area projected from the gate poly, wherein at least one of the carrier drain drift regions has a gradient doping concentration; and two carrier plus regions, respectively locate within the two carrier drain drift regions, wherein the two carrier plus regions and the two carrier drain drift regions are communicating with each other through the channel when the HVMOS is activated.Type: ApplicationFiled: October 5, 2010Publication date: April 5, 2012Inventors: Chun-Yu Chou, Chien-Liang Tung, Chi-Wei Lin
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Publication number: 20120049249Abstract: A semiconductor structure and a method for fabricating the same. A semiconductor structure includes a semiconductor substrate; a channel region formed in the semiconductor substrate; a gate including a dielectric layer and a conductive layer and formed above the channel region; source and drain regions formed at opposing sides of the gate; first shallow trench isolations embedded into the semiconductor substrate and having a length direction parallel to the length direction of the gate; and second shallow trench isolations, each of which abuts the outer sidewall of the source or the drain region and abuts the first shallow trench isolations, in which the source and drain regions include first seed crystal layers abutting the second shallow trench isolations, and the top surfaces of the second shallow trench isolations are higher than or as high as the top surfaces of the source and drain regions.Type: ApplicationFiled: September 20, 2010Publication date: March 1, 2012Applicant: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huilong Zhu, Haizhou Yin, Zhijiong Luo, Huicai Zhong
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Patent number: 8101475Abstract: A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A channel layer may be formed on a portion of the gate electrode, with source and drain regions formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions of the FET may be perpendicular to a surface of the semiconductor substrate.Type: GrantFiled: October 7, 2009Date of Patent: January 24, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Woo Oh, Dong-Gun Park, Dong-Won Kim, Dong-Uk Choi, Kyoung-Hwan Yeo
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Publication number: 20110256683Abstract: The present invention relates to a method of manufacturing a semiconductor device, wherein the method comprises: providing a substrate; forming a source region, a drain region, a dummy gate structure, and a gate dielectric layer on the substrate, wherein the dummy gate structure is between the source region and the drain region on the substrate, and the gate dielectric layer is between the substrate and the dummy gate structure; annealing the source region and the drain region; removing the dummy gate structure to form an opening; implanting dopants into the substrate from the opening to form a steep retrograded well; annealing to activate the dopants; and forming a metal gate on the gate dielectric layer by deposition.Type: ApplicationFiled: June 22, 2010Publication date: October 20, 2011Applicant: Institute of Microelectronics, Chinese Academy of SciencesInventors: Huilong Zhu, Wenwu Wang
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Publication number: 20110233623Abstract: There is provided a semiconductor device and a method of manufacturing the same.Type: ApplicationFiled: December 10, 2010Publication date: September 29, 2011Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Ki Yeol PARK, Woo Chul Jeon, Young Hwan Park, Jung Hee Lee
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Patent number: 8012836Abstract: Semiconductor devices and methods for fabricating the same are provided. An exemplary embodiment of a semiconductor device comprises a substrate with a plurality of isolation structures formed therein, defining first and second areas over the substrate. A transistor is formed on a portion of the substrate in the first and second areas, respectively, wherein the transistor in the second area is formed with merely a pocket doping region in the substrate adjacent to a drain region thereof. A first dielectric layer is formed over the substrate, covering the transistor formed in the first and second areas. A plurality of first contact plugs is formed through the first dielectric layer, electrically connecting a source region and a drain region of the transistor in the second area, respectively. A second dielectric layer is formed over the first dielectric layer with a capacitor formed therein, wherein the capacitor electrically connects one of the first contact plugs.Type: GrantFiled: September 28, 2006Date of Patent: September 6, 2011Assignee: Taiwan Semiconductor Manufacuturing Co., Ltd.Inventors: Kuo-Chyuan Tzeng, Jian-Yu Shen, Kuo-Chi Tu, Kuo-Ching Huang, Chin-Yang Chang
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Patent number: 8007727Abstract: A multiple-gate field-effect transistor includes a fluid in a top gate, two lateral gates, and a bottom gate. The multiple-gate field-effect transistor also includes a patterned depletion zone and a virtual depletion zone that has a lesser width than the patterned depletion zone. The virtual depletion zone width creates a virtual semiconductor nanowire that is lesser in width than the patterned depletion zone.Type: GrantFiled: May 30, 2008Date of Patent: August 30, 2011Assignee: Intel CorporationInventors: Gil Shalev, Amihood Doron, Ariel Cohen
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Patent number: 7988470Abstract: The present invention generally relates to thin film transistors (TFTs) and methods of making TFTs. The active channel of the TFT may comprise one or more metals selected from the group consisting of zinc, gallium, tin, indium, and cadmium. The active channel may also comprise nitrogen and oxygen. To protect the active channel during source-drain electrode patterning, an etch stop layer may be deposited over the active layer. The etch stop layer prevents the active channel from being exposed to the plasma used to define the source and drain electrodes. The etch stop layer and the source and drain electrodes may be used as a mask when wet etching the active material layer that is used for the active channel.Type: GrantFiled: September 17, 2010Date of Patent: August 2, 2011Assignee: Applied Materials, Inc.Inventor: Yan Ye
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Publication number: 20110180883Abstract: A method and structure implant a first-type impurity within a substrate to form a channel region within the substrate adjacent a top surface of the substrate; form a gate stack on the top surface of the substrate above the channel region; and implant a second-type impurity within the substrate to form source and drain regions within the substrate adjacent the top surface. The channel region is positioned between the source and drain regions. The second-type impurity has an opposite polarity with respect to the first-type impurity. The method and structure implant a greater concentration of the first-type impurity, relative to a concentration of the first-type impurity within the channel region, to form a primary body doping region within the substrate below (relative to the top surface) the channel region; and to form secondary body doping regions within the substrate below (relative to the top surface) the source and drain regions.Type: ApplicationFiled: January 28, 2010Publication date: July 28, 2011Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, FREESCALE SEMICONDUCTOR, INC.Inventors: Xiangdong Chen, Geng Wang, Da Zhang
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Patent number: 7936006Abstract: An MOS device has an embedded dielectric structure underlying an active portion of the device, such as a source extension or a drain extension. In an alternative embodiment, an embedded dielectric structure underlies the channel region of a MOS device, as well as the source and drain extensions.Type: GrantFiled: October 6, 2005Date of Patent: May 3, 2011Assignee: Xilinx, Inc.Inventors: Yuhao Luo, Deepak Kumar Nayak, Daniel Gitlin
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Patent number: 7923327Abstract: Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory device comprises: a control gate region formed by doping a semiconductor substrate with second impurities; an electron injection region formed by doping the semiconductor substrate with first impurities, where a top surface of the electron injection region includes a tip portion at an edge; a floating gate electrode covering at least a portion of the control gate region and the tip portion of the electron injection region; a first tunnel oxide layer interposed between the floating gate electrode and the control gate region; a second tunnel oxide layer interposed between the floating gate electrode and the electron injection region; a trench surrounding the electron injection region in the semiconductor substrate; and a device isolation layer pattern filled in the trench.Type: GrantFiled: June 24, 2008Date of Patent: April 12, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Sung Kun Park
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Patent number: 7915110Abstract: A MOS transistor made in monolithic form, vias contacting the gate and the source and drain regions of the transistor being formed on the other side of the channel region with respect to the gate.Type: GrantFiled: March 27, 2009Date of Patent: March 29, 2011Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat à l'Energie AtomiqueInventors: Philippe Coronel, Claire Gallon, Claire Benouillet-Beranger
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Publication number: 20110014768Abstract: According to one embodiment of the invention, a method for nickel silicidation includes providing a substrate having a source region, a gate region, and a drain region, forming a source in the source region and a drain in the drain region, annealing the source and the drain, implanting, after the annealing the source and the drain, a heavy ion in the source region and the drain region, depositing a nickel layer in each of the source and drain regions, and heating the substrate to form a nickel silicide region in each of the source and drain regions by heating the substrate.Type: ApplicationFiled: September 24, 2010Publication date: January 20, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Amitabh JAIN, Peijun CHEN, Jorge A. KITTL
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Publication number: 20110013107Abstract: A semiconductor device includes a supporting substrate; a semiconductor film on the supporting substrate; a gate insulating film on the semiconductor film; a gate electrode on the gate insulating film; and a source region and a drain region formed by introducing impurity elements to the semiconductor film. The thickness of the semiconductor film is within the range of 20 nm to 40 nm. Low-concentration regions are provided between the source region and a channel forming region, and between the drain region and the channel forming region, respectively. The low-concentration regions each have an impurity concentration smaller than that of the source region and that of the drain region, and the impurity concentration in a lower surface side region on the side of the supporting substrate is smaller than that of an upper surface side region on the opposite side.Type: ApplicationFiled: March 30, 2009Publication date: January 20, 2011Applicant: NEC LCD TECHNOLOGIES, LTD.Inventors: Shigeru Mori, Isao Shouji, Hiroshi Tanabe
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Patent number: 7843020Abstract: A high withstand voltage transistor is capable of preventing its gate oxidized film from being damaged by a surge voltage/current, and includes: a gate electrode provided in a trench formed on a semiconductor substrate; a source and a drain which are respectively formed on a side of the gate electrode and another side of the gate electrode, and which are a predetermined distance away from the gate electrode; first electric field relaxation layers one of which is formed on a wall of the trench on the side of the source and another one of which is formed on a wall of the trench on the side of the drain; and second electric field relaxation layers one of which is formed between the source and the gate electrode, and another one of which is formed between the drain and the gate electrode.Type: GrantFiled: September 24, 2007Date of Patent: November 30, 2010Assignee: Sharp Kabushiki KaishaInventor: Keiji Hayashi
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Patent number: 7838369Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) is fabricated so as to have a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material is preferably provided with a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262).Type: GrantFiled: October 31, 2007Date of Patent: November 23, 2010Assignee: National Semiconductor CorporationInventor: Constantin Bulucea
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Patent number: 7821062Abstract: A field effect transistor is provided having a source region, a drain region formed in a first well region, and a channel region. The first well region is doped with doping atoms of a first conductivity type. At least a part of the channel region which extends into the first well region is doped with doping atoms of a second conductivity type, the second conductivity type being a different conductivity type than the first conductivity type.Type: GrantFiled: May 12, 2006Date of Patent: October 26, 2010Assignee: Infineon Technologies AGInventor: Harald Gossner
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Patent number: 7811892Abstract: A method of fabricating a dielectric layer is described. A substrate is provided, and a dielectric layer is formed over the substrate. The dielectric layer is performed with a nitridation process. The dielectric layer is performed with a first annealing process. A first gas used in the first annealing process includes inert gas and oxygen. The first gas has a first partial pressure ratio of inert gas to oxygen. The dielectric layer is performed with the second annealing process. A second gas used in the second annealing includes inert gas and oxygen. The second gas has a second partial pressure ratio of inert gas to oxygen, and the second partial pressure ratio is smaller than the first partial pressure ratio. At least one annealing temperature of the two annealing processes is equal to or greater than 950° C. The invention improves uniformity of nitrogen dopants distributed in dielectric layer.Type: GrantFiled: March 31, 2006Date of Patent: October 12, 2010Assignee: United Microelectronics Corp.Inventors: Yun-Ren Wang, Ying-Wei Yen, Chien-Hua Lung, Shu-Yen Chan, Kuo-Tai Huang
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Patent number: 7785971Abstract: Fabrication of complementary first and second insulated-gate field-effect transistors (110 or 112 and 120 or 122) from a semiconductor body entails separately introducing (i) three body-material dopants into the body material (50) for the first transistor so as to reach respective maximum dopant concentrations at three different locations in the first transistor's body material and (ii) two body-material dopants into the body material (130) for the second transistor so as to reach respective maximum dopant concentrations at two different locations in the second transistor's body material. Gate electrodes (74 or 94 and 154 or 194) are subsequently defined after which source/drain zones (60, 62 or 80, 82 and 140, 142 or 160, 162) are formed in the semiconductor body. The vertical dopant profiles resulting from the body-material dopants alleviate punchthrough and reduce current leakage.Type: GrantFiled: February 6, 2007Date of Patent: August 31, 2010Assignee: National Semiconductor CorporationInventors: Constantin Bulucea, Fu-Cheng Wang, Prasad Chaparala
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Publication number: 20100207183Abstract: A method of controlling gate induced drain leakage current of a transistor is disclosed. The method includes forming a dielectric region (516) on a surface of a substrate having a first concentration of a first conductivity type (P-well). A gate region (500) having a length and a width is formed on the dielectric region. Source (512) and drain (504) regions having a second conductivity type (N+) are formed in the substrate on opposite sides of the gate region. A first impurity region (508) having the first conductivity type (P+) is formed adjacent the source. The first impurity region has a second concentration greater than the first concentration.Type: ApplicationFiled: July 28, 2009Publication date: August 19, 2010
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Patent number: 7767536Abstract: A semiconductor device and fabrication method thereof are disclosed. An example semiconductor device includes a semiconductor substrate having a device isolation area defining an active area; a gate oxide layer formed on the active area of the substrate; a gate on the gate oxide layer; a spacer provided to a sidewall of the gate; and a well region provided within the active area. The well region includes a threshold voltage adjustment doped region, a halo region, a source region, a drain region, an additional doped region, and a channel stop region, the additional doped region provided between the well region and each of the source and drain regions.Type: GrantFiled: December 28, 2004Date of Patent: August 3, 2010Assignee: Dongbu Electronics Co., Ltd.Inventor: Tae Woo Kim
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Patent number: 7759201Abstract: A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature, selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the at least one device layer using the first feature, the filler feature and the second feature as a mask.Type: GrantFiled: December 17, 2007Date of Patent: July 20, 2010Assignee: SanDisk 3D LLCInventors: Christopher J. Petti, Steven J. Radigan
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Publication number: 20100176452Abstract: A lateral MOSFET having a substrate, first and second epitaxial layers grown on the substrate and a gate electrode formed on a gate dielectric which in turn is formed on a top surface of the second epitaxial layer. The second epitaxial layer comprises a drain region which extends to a top surface of the epitaxial layer and is proximate to a first edge of the gate electrode, a source region which extends to a top surface of the second epitaxial layer and is proximate to a second edge of the gate electrode, a heavily doped body under at least a portion of the source region, and a lightly doped well under the gate dielectric located near the transition region of the first and second epitaxial layers. A PN junction between the heavily doped body and the first epitaxial region under the heavily doped body has an avalanche breakdown voltage that is substantially dependent on the doping concentration in the upper portion of the first epitaxial layer that is beneath the heavily doped body.Type: ApplicationFiled: January 12, 2009Publication date: July 15, 2010Inventors: Bruce D. Marchant, Dean Probst
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Patent number: 7705400Abstract: A semiconductor device provided with a filled tetrahedral semiconductor is formed by introducing impurity atoms S for substituting the component atoms of sites of lattice points and impurity atoms I to be inserted into interstitial sites of a host semiconductor where component atoms are bonded to form a tetrahedral bonding structure. Such a semiconductor device is made to show a high mobility level and a high current drive force as a semiconductor substance where impurity atoms S are made to have a valance electron agreeing with that of the component atoms of the host semiconductor as a result of charge transfer between impurity atoms S and impurity atoms I and impurity atoms I are bonded in a state of showing an electronic arrangement of a closed shell structure is used as channel material.Type: GrantFiled: August 13, 2007Date of Patent: April 27, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Kazushige Yamamoto
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Publication number: 20100096695Abstract: A semiconductor device that includes a substrate having an active region prepared with a transistor is presented. The semiconductor device includes a stress structure adjacent to the substrate. The stress structure includes a dielectric layer having nanocrystals embedded therein. The nanocrystals induce a first or a second stress on a channel region of the transistor which improves carrier mobility of the transistor.Type: ApplicationFiled: October 16, 2008Publication date: April 22, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.Inventors: Han Guan Chew, Jinping Liu, Alex Kh See, Mei Sheng Zhou
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Patent number: 7687356Abstract: A method of forming a silicon germanium conduction channel under a gate stack of a semiconductor device, the gate stack being formed on a silicon layer on an insulating layer, the method including growing a silicon germanium layer over said silicon layer and heating the device such that germanium condenses in the silicon layer such that a silicon germanium channel is formed between the gate stack and the insulating layer.Type: GrantFiled: March 5, 2007Date of Patent: March 30, 2010Assignee: STMicroelectronics Crolles 2 SASInventors: Philippe Coronel, Arnaud Pouydebasque
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Patent number: 7683364Abstract: A gated resonant tunneling diode (GRTD) is disclosed including a metal oxide semiconductor (MOS) gate over a gate dielectric layer which is biased to form an inversion layer between two barrier regions, resulting in a quantum well less than 15 nanometers wide. Source and drain regions adjacent to the barrier regions control current flow in and out of the quantum well. The GRTD may be integrated in CMOS ICs as a quantum dot or a quantum wire device. The GRTD may be operated in a negative conductance mode, in a charge pump mode and in a radiative emission mode.Type: GrantFiled: September 4, 2008Date of Patent: March 23, 2010Assignee: Texas Instruments IncorporatedInventors: Henry Litzmann Edwards, Chris Bowen, Tathagata Chatterjee
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Publication number: 20100025756Abstract: A dual current path LDMOSFET transistor (40) is provided which includes a substrate (400), a graded buried layer (401), an epitaxial drift region (404) in which a drain region (416) is formed, a first well region (406) in which a source region (412) is formed, a gate electrode (420) formed adjacent to the source region (412) to define a first channel region (107), and a current routing structure that includes a buried RESURF layer (408) in ohmic contact with a second well region (414) formed in a predetermined upper region of the epitaxial layer (404) so as to be completely covered by the gate electrode (420), the current routing structure being spaced apart from the first well region (406) and from the drain region (416) on at least a side of the drain region to delineate separate current paths from the source region and through the epitaxial layer.Type: ApplicationFiled: July 30, 2008Publication date: February 4, 2010Inventors: Yue Fu, Ronghua Zhu, Vishnu K. Khemka, Amitava Bose, Todd C. Roggenbauer
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Patent number: 7645674Abstract: A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A second isolation is formed on the semiconductor substrate, and a second element region is isolated via the second isolation. A second gate insulating film is formed on the second element region, and a second gate electrode is formed on the second gate insulating film. A first oxide film is formed between the first isolation and the first element region. A second oxide film is formed between the second isolation and the second element region. The first isolation has a width narrower than the second isolation, and the first oxide film has a thickness thinner than the second oxide film.Type: GrantFiled: August 7, 2007Date of Patent: January 12, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Toshitake Yaegashi, Junichi Shiozawa
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Patent number: 7645665Abstract: A method for manufacturing a semiconductor device has the steps of: (a) implanting boron (B) ions into a semiconductor substrate; (b) implanting fluorine (F) or nitrogen (N) ions into the semiconductor device; (c) after the steps (a) and (b) are performed, executing first annealing with a heating time of 100 msec or shorter relative to a region of the semiconductor substrate into which ions were implanted; and (d) after the step (c) is performed, executing second annealing with a heating time longer than the heating time of the first annealing, relative to the region of the semiconductor substrate into which ions were implanted. The method for manufacturing a semiconductor device is provided which can dope boron (B) shallowly and at a high concentration.Type: GrantFiled: December 4, 2006Date of Patent: January 12, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Tomohiro Kubo, Kenichi Okabe, Tomonari Yamamoto
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Patent number: 7642603Abstract: In one embodiment of the invention, a non-planar transistor includes a gate electrode and multiple fins. A trench contact is coupled to the fins. The contact bottom is formed above the substrate and does not directly contact the substrate. The contact bottom is higher than the gate top.Type: GrantFiled: June 29, 2007Date of Patent: January 5, 2010Assignee: Intel CorporationInventors: Suman Datta, Titash Rakshit, Jack T. Kavalieros, Brian S. Doyle
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Publication number: 20090294872Abstract: A method of reducing junction capacitance and leakage and a structure having reduced junction capacitance and leakage wherein germanium or xenon is implanted in the source and drain regions to at least partially deactivate the dopants in the source and drain regions.Type: ApplicationFiled: May 29, 2008Publication date: December 3, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xiangdong Chen, Zhijiong Luo, Thomas Anthony Wallner
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Patent number: 7598146Abstract: A semiconductor structure comprises a silicon substrate of a first conductivity type including wells of a second conductivity type formed on a surface thereof. The wells may be laterally isolated by shallow trench isolation. Transistors are formed in the wells by first forming several chemically distinct layers. Anisotropic etching then forms openings in a top one of the layers. A blanket dielectric layer is formed in the openings and on the layers. Anisotropic etching removes portions of the blanket dielectric layer from planar surfaces of the substrate but not from sidewalls of the openings to form dielectric spacers separated by gaps within the openings. Gate oxides are formed by oxidation of exposed areas of the substrate. Ion implantation forms channels beneath the gate oxides. Polysilicon deposition followed by chemical-mechanical polishing defines gates in the gaps. The chemically distinct layers are then stripped without removing the dielectric spacers.Type: GrantFiled: August 31, 2006Date of Patent: October 6, 2009Assignee: STMicroelectronics, Inc.Inventor: Robert Louis Hodges
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Patent number: 7595244Abstract: Fabrication of two differently configured like-polarity insulated-gate field-effect transistors (40 or 42 and 240 or 242) entails introducing multiple body-material semiconductor dopants of the same conductivity type into a semiconductor body. Gate electrodes (74 or 94) are defined such that each body-material dopant reaches a maximum concentration below the channel surface depletion regions, below all gate-electrode material overlying the channel zones (64 or 84), and at a different depth than each other body-material dopant. The transistors are provided with source/drain zones (60 or 80) of opposite conductivity type to, and with halo pocket portions of the same conductivity type as, the body-material dopants. One pocket portion (100/102 or 104) extends along both source/drain zones of one of the transistors. Another pocket portion (244 or 246) extends largely along only one of the source/drain zones of the other transistor so that it is asymmetrical.Type: GrantFiled: October 16, 2007Date of Patent: September 29, 2009Assignee: National Semiconductor CorporationInventors: Constantin Bulucea, Fu-Cheng Wang, Prasad Chaparala
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Publication number: 20090191682Abstract: A fabrication method of a semiconductor device includes: forming a gate insulating film and a gate electrode on an N type well; forming first source/drain regions by implanting a first element in regions of the N type well on both sides of the gate electrode, the first element being larger than silicon and exhibiting P type conductivity; forming second source/drain regions by implanting a second element in the regions of the N type well on the both sides of the gate electrode, the second element being smaller than silicon and exhibiting P type conductivity; and forming a metal silicide layer on the source/drain regions.Type: ApplicationFiled: January 29, 2009Publication date: July 30, 2009Inventor: Hiroyuki KAMADA
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Patent number: 7560324Abstract: Drain extended MOS transistors (52) and fabrication methods (100) therefor are presented, in which a voltage drop region (80) is provided in a well (82) of a second conductivity type between a channel (78) of a first conductivity type and a drain (74) to inhibit channel hot carrier or direct tunneling degradation of the transistor gate dielectric (64) for high voltage operation. The voltage drop region (80) has more dopants of the first conductivity type and/or fewer dopants of the second conductivity type than does the well (82) so as to shift the high fields away from the transistor gate dielectric (64).Type: GrantFiled: July 8, 2004Date of Patent: July 14, 2009Assignee: Texas Instruments IncorporatedInventor: Pr Chidambaram
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Patent number: 7557049Abstract: A producing method of a wired circuit board includes the step of preparing a wired circuit board including an insulating layer and a conductive pattern having a wire covered with the insulating layer and a terminal portion exposed from the insulating layer; and the step of forming a semiconductive layer on a surface of the insulating layer by dipping the wired circuit board in a polymeric liquid of a conductive polymer in which an electrode is provided, and applying a voltage so that the electrode becomes an anode and the conductive pattern becomes a cathode.Type: GrantFiled: October 23, 2007Date of Patent: July 7, 2009Assignee: Nitto Denko CorporationInventors: Jun Ishii, Yasunari Ooyabu, Hiroyuki Kurai
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Publication number: 20090134476Abstract: An accumulation mode field effect transistor includes a substrate, an insulated gate on the substrate, source and drain regions on the substrate on opposite sides of the insulated gate, a channel region that is doped a first conductivity type at a first doping concentration, and that extends into the substrate beneath the insulated gate to a channel region depth, and a counter-doped region (for example, a portion of the substrate, a tub in the substrate or a well in the substrate) beneath the channel region that is doped a second conductivity type at a second doping concentration to define a semiconductor junction therebetween at the channel region depth.Type: ApplicationFiled: November 11, 2008Publication date: May 28, 2009Inventor: William R. Richards, JR.
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Patent number: 7504292Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a gate stack on the semiconductor substrate, and epitaxially growing a lightly-doped source/drain (LDD) region adjacent the gate stack, wherein carbon is simultaneously doped into the LDD region.Type: GrantFiled: December 5, 2006Date of Patent: March 17, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Keh-Chiang Ku, Pang-Yen Tsai, Chun-Feng Nieh, Li-Ting Wang
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Publication number: 20090057651Abstract: A gated resonant tunneling diode (GRTD) is disclosed including a metal oxide semiconductor (MOS) gate over a gate dielectric layer which is biased to form an inversion layer between two barrier regions, resulting in a quantum well less than 15 nanometers wide. Source and drain regions adjacent to the barrier regions control current flow in and out of the quantum well. The GRTD may be integrated in CMOS ICs as a quantum dot or a quantum wire device. The GRTD may be operated in a negative conductance mode, in a charge pump mode and in a radiative emission mode.Type: ApplicationFiled: September 4, 2008Publication date: March 5, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Henry Litzmann Edwards, Chris Bowen, Tathagata Chatterjee
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Patent number: 7491613Abstract: An element capable of manufacturing various devices of any shape having plasticity or flexibility without being limited by shape and a method for manufacturing thereof are provided. An element characterized by that a circuit element is formed continuously or intermittently in the longitudinal direction. An element characterized by that a cross section having a plurality of areas forming a circuit is formed continuously or intermittently in the longitudinal direction.Type: GrantFiled: May 2, 2003Date of Patent: February 17, 2009Assignee: Ideal Star Inc.Inventors: Yasuhiko Kasama, Satoshi Fujimoto, Kenji Omote