Using Channel Conductivity Dopant Of Opposite Type As That Of Source And Drain Patents (Class 438/291)
  • Patent number: 11309413
    Abstract: A semiconductor device includes a substrate, a drift layer, a well region, and a source region. The substrate has a first conductivity type. The drift layer has the first conductivity type and is on the substrate. The well region has a second conductivity type opposite the first conductivity type and provides a channel region. The source region is in the well region and has the first conductivity type. A doping concentration of the well region along a surface of the drift layer opposite the substrate is variable such that the well region includes a region of increased doping concentration at a distance from a junction between the source region and the well region.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: April 19, 2022
    Assignee: WOLFSPEED, INC.
    Inventor: Sei-Hyung Ryu
  • Patent number: 10727345
    Abstract: A method for forming a semiconductor structure includes forming at least one fin on a semiconductor substrate. The least one fin includes a semiconducting material. A gate is formed over and in contact with the at least one fin. A germanium comprising layer is formed over and in contact with the at least one fin. Germanium from the germanium comprising layer is diffused into the semiconducting material of the at least one fin.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: July 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Xin Miao
  • Patent number: 10714474
    Abstract: An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a mid voltage range, may also include a high-voltage MOS transistor which operates in a third voltage range significantly higher than the low and mid voltage ranges, for example 20 to 30 volts. The high-voltage MOS transistor has a closed loop configuration, in which a drain region is surrounded by a gate, which is in turn surrounded by a source region, so that the gate does not overlap field oxide. The integrated circuit may include an n-channel version of the high-voltage MOS transistor and/or a p-channel version of the high-voltage MOS transistor. Implanted regions of the n-channel version and the p-channel version are formed concurrently with implanted regions in the first and second pluralities of MOS transistors.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: July 14, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Pinghai Hao, Sameer Pendharkar, Seetharaman Sridhar, Jarvis Jacobs
  • Patent number: 10374091
    Abstract: A method for forming a semiconductor structure includes forming at least one fin on a semiconductor substrate. The least one fin includes a semiconducting material. A gate is formed over and in contact with the at least one fin. A germanium comprising layer is formed over and in contact with the at least one fin. Germanium from the germanium comprising layer is diffused into the semiconducting material of the at least one fin.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Xin Miao
  • Patent number: 10084083
    Abstract: A semiconductor structure and a manufacturing method of a semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate, a gate, a first diffusion region and a second diffusion region. The gate is disposed on the semiconductor substrate and extends along a first direction. The first diffusion region is formed in the semiconductor substrate, and the second diffusion region is formed in the first diffusion region. The first diffusion region has a first portion located underneath the gate and a second portion protruded from a lateral side of the gate, the first portion has a first length parallel to the first direction, the second portion has a second length parallel to the first direction, and the first length is larger than the second length.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: September 25, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shin-Hung Li, Kuan-Chuan Chen, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Patent number: 9653358
    Abstract: The present invention presents a method for manufacturing a semiconductor device structure as well as the semiconductor device structure. Said method comprises: providing a semiconductor substrate; forming a first insulating layer on the semiconductor substrate; forming a shallow trench isolation embedded in the first insulating layer and the semiconductor substrate; forming a channel region embedded in the semiconductor substrate; and forming a gate stack stripe on the channel region. Said method further comprises, before forming the channel region, performing a source/drain implantation on the semiconductor substrate. By means of forming the source/drain regions in a self-aligned manner before forming the channel region and the gate stack, said method achieves the advantageous effects of the replacement gate process without using a dummy gate, thereby simplifying the process and reducing the cost.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: May 16, 2017
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Huicai Zhong, Qingqing Liang
  • Patent number: 9559203
    Abstract: In one example implementation, the present disclosure provides a modular approach to reducing flicker noise in metal-oxide semiconductor field-effect transistors (MOSFETs) in a device. First, a circuit designer may select one or more surface channel MOSFETs in a device. Then, the one or more surface channel MOSFETs are converted to one or more buried channel MOSFETs to reduce flicker noise. One or more masks may be applied to the channel(s) of the one or more surface channel MOSFETs. The technique maybe used at the input(s) of operational amplifiers, and more particularly, rail-to-rail operational amplifiers, as well as other analog and digital circuits such a mixers, ring oscillators, current mirrors, etc.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: January 31, 2017
    Assignee: ANALOG DEVICES, INC.
    Inventors: Ali Eshraghi, Alfredo Tomasini
  • Patent number: 9559176
    Abstract: A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET; forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode; implanting a first dopant into the fin of the second polarity FET; etching a cavity in the fin of the second polarity FET on each side of the gate electrode; removing the first mask; performing rapid thermal anneal (RTA); epitaxially growing a source/drain region of the second polarity FET in each cavity; forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and implanting a second dopant in the source/drain regions of the second polarity FET.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: January 31, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Peijie Feng, Yanxiang Liu, Shesh Mani Pandey, Jianwei Peng, Francis Benistant
  • Patent number: 9461151
    Abstract: An embodiment of the present invention is directed to a memory cell. The memory cell includes a first charge storage element and a second charge storage element, wherein the first and second charge storage elements include nitrides. The memory cell further includes an insulating layer formed between the first and second charge storage elements. The insulating layer provides insulation between the first and second charge storage elements.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: October 4, 2016
    Assignee: CYRESS SEMICONDUCTOR CORPORATION
    Inventors: Fred T. K. Cheung, Hiroyuki Kinoshita, Chungho Lee, Yu Sun, Chi Chang
  • Patent number: 9425252
    Abstract: A method of forming a SDB including a protective layer or bilayer and the resulting device are provided. Embodiments include forming a SDB of oxide in a Si substrate; forming a nitride layer over the Si substrate; forming a photoresist over the SDB and a portion of the nitride layer; removing the nitride layer on opposite sides of the photoresist down to the Si substrate, leaving a portion of the nitride layer only under the photoresist; forming a gate above the SBD and the portion of the nitride layer.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: August 23, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Bingwu Liu
  • Patent number: 9343328
    Abstract: A semiconductor structure having a substrate; an active device formed in an active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region between a pair of electrical contacts; and a photolithographic, thickness non-uniformity, compensation feature, disposed on the surface substrate off of the active semiconductor region. In one embodiment the feature comprises pads on the surface of the substrate and off of the active semiconductor region.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: May 17, 2016
    Assignee: RAYTHEON COMPANY
    Inventors: Paul J. Duval, Paul M. Ryan, Christopher J. MacDonald
  • Patent number: 9337307
    Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: May 10, 2016
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Robert S. Chau, Suman Datta, Mark L. Doczy, Brian S. Doyle, Jack T. Kavalieros, Amlan Majumdar, Matthew V. Metz, Marko Radosavljevic
  • Patent number: 9240454
    Abstract: An integrated circuit includes a substrate supporting a transistor having a source region and a drain region. A high dopant concentration delta-doped layer is present on the source region and drain region of the transistor. A set of contacts extend through a pre-metal dielectric layer covering the transistor. A silicide region is provided at a bottom of the set of contacts. The silicide region is formed by a salicidation reaction between a metal present at the bottom of the contact and the high dopant concentration delta-doped layer on the source region and drain region of the transistor.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: January 19, 2016
    Assignee: STMicroelectronics, Inc.
    Inventors: Qing Liu, Walter Kleemeier
  • Patent number: 9196715
    Abstract: A semiconductor device includes a channel structure formed on a substrate, the channel structure being formed of a semiconductor material. A gate structure covers at least a portion of the surface of the channel structure and is formed of a film of insulation material and a gate electrode. A source structure is connected to one end of the channel structure, and a drain structure is connected to the other end of the channel structure. The channel structure has a non-uniform composition, in a cross-sectional view, that provides a reduction of a leakage current of the semiconductor device relative to a leakage current that would result from a uniform composition.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: November 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Tomohiro Hirai, Shogo Mochizuki, Toshiharu Nagumo
  • Patent number: 9184278
    Abstract: A planar vertical DMOS transistor uses a conductive spacer structure formed on the sides of a dielectric structure as the gate of the transistor. The planar vertical DMOS transistor with a conductive spacer gate structure reduces the parasitic gate-to-bulk or gate-to-drain overlap capacitance by eliminating the conductive gate material that is formed above the bulk of the semiconductor layer. Meanwhile, the desired distance between the body regions formed on opposing sides of the conductive spacer gate structure is maintained.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: November 10, 2015
    Assignee: Micrel, Inc.
    Inventor: David Raymond Zinn
  • Patent number: 9178054
    Abstract: A planar vertical DMOS transistor includes a dielectric separation structure formed under the conductive gate and over the bulk of the semiconductor layer outside of the channel region of the transistor. The planar vertical DMOS transistor with a conductive gate formed over the dielectric structure reduces the parasitic gate-to-bulk or gate-to-drain overlap capacitance by increasing the separation between the conductive gate and the bulk of the semiconductor layer. Meanwhile, the desired distance between the body regions formed on opposing sides of the conductive gate is maintained.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: November 3, 2015
    Assignee: Micrel, Inc.
    Inventor: David Raymond Zinn
  • Patent number: 9136180
    Abstract: According to some embodiments, an electrode have a high effective work function is formed. The electrode may be the gate electrode of a transistor and may be formed on a high-k gate dielectric by depositing a first layer of conductive material, exposing that first layer to a hydrogen-containing gas, and depositing a second layer of conductive material over the first layer. The first layer may be deposited using a non-plasma process in which the substrate is not exposed to plasma or plasma-generated radicals. The hydrogen-containing gas to which the first layer is exposed may include an excited hydrogen species, which may be part of a hydrogen-containing plasma, and may be hydrogen-containing radicals. The first layer may also be exposed to oxygen before depositing the second layer. The work function of the gate electrode in the gate stack may be about 5 eV or higher in some embodiments.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: September 15, 2015
    Assignee: ASM IP HOLDING B.V.
    Inventors: Vladimir Machkaoutsan, Jan Willem Maes, Qi Xie
  • Patent number: 9117691
    Abstract: An integrated circuit containing an analog MOS transistor has an implant mask for a well which blocks well dopants from two diluted regions at edges of the gate, but exposes a channel region to the well dopants. A thermal drive step diffuses the implanted well dopants across the two diluted regions to form a continuous well with lower doping densities in the two diluted regions. Source/drain regions are formed adjacent to and underlapping the gate by implanting source/drain dopants into the substrate adjacent to the gate using the gate as a blocking layer and subsequently annealing the substrate so that the implanted source/drain dopants provide a desired extent of underlap of the source/drain regions under the gate. Drain extension dopants and halo dopants are not implanted into the substrate adjacent to the gate.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: August 25, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Sameer Pendharkar
  • Patent number: 9105650
    Abstract: A method of forming a lateral bipolar transistor includes forming a silicon on insulator (SOI) substrate having a bottom substrate layer, a buried oxide layer (BOX) on top of the substrate layer, and a silicon on insulator (SOI) layer on top of the BOX layer, forming a dummy gate and spacer on top of the silicon on insulator layer, doping the SOI layer with positive or negative ions, depositing an inter layer dielectric (ILD), using chemical mechanical planarization (CMP) to planarize the ILD, removing the dummy gate creating a gate trench which reveals the base of the dummy gate, doping the dummy gate base, depositing a layer of polysilicon on top of the SOI layer and into the gate trench, etching the layer of polysilicon so that it only covers the dummy gate base, and applying a self-aligned silicide process.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: August 11, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, Gen Pei Lauer, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 9059311
    Abstract: A disposable semiconductor material is deposited to form disposable semiconductor material portions on semiconductor fins. A first dielectric liner is deposited and patterned to form openings above a first set of disposable semiconductor material portions on a first semiconductor fin. The first set of disposable semiconductor material portions is replaced with a first set of active semiconductor regions by a combination of an etch and a selective epitaxy process that deposits a first semiconductor material. A second dielectric liner is deposited and patterned to form openings above the second set of disposable semiconductor material portions. The second set of disposable semiconductor material portions is replaced with a second set of active semiconductor regions employing another epitaxy process that deposits a second semiconductor material. The active semiconductor regions can have the same faceting profile irrespective of the semiconductor materials therein.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: June 16, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz
  • Patent number: 9029227
    Abstract: A p-channel flash memory is formed with a charge storage stack embedded in a hetero-junction layer in which a raised source/drain is formed. Embodiments include forming a dummy gate stack on a substrate, forming a layer on the substrate by selective epitaxial growth, on each side of the dummy gate stack, forming spacers on the layer, forming raised source/drains, removing the dummy gate stack, forming a cavity between the spacers, and forming a memory gate stack in the cavity. Different embodiments include forming the layer of a narrow bandgap material, a narrow bandgap layer under the spacers and a wide bandgap layer adjacent thereto, or a wide bandgap layer under the spacers, a narrow bandgap layer adjacent thereto, and a wide bandgap layer on the narrow bandgap layer.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: May 12, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Eng Huat Toh, Elgin Quek, Ying Keung Leung, Sanford Chu
  • Patent number: 9006094
    Abstract: A stratified gate dielectric stack includes a first high dielectric constant (high-k) gate dielectric comprising a first high-k dielectric material, a band-gap-disrupting dielectric comprising a dielectric material having a different band gap than the first high-k dielectric material, and a second high-k gate dielectric comprising a second high-k dielectric material. The band-gap-disrupting dielectric includes at least one contiguous atomic layer of the dielectric material. Thus, the stratified gate dielectric stack includes a first atomic interface between the first high-k gate dielectric and the band-gap-disrupting dielectric, and a second atomic interface between the second high-k gate dielectric and the band-gap-disrupting dielectric that is spaced from the first atomic interface by at least one continuous atomic layer of the dielectric material of the band-gap-disrupting dielectric.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: April 14, 2015
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, Paul C. Jamison
  • Patent number: 8994107
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided herein. In an embodiment, a semiconductor device includes a semiconductor substrate. A source region and a drain region are disposed in the semiconductor substrate. A channel region is defined in the semiconductor substrate between the source region and the drain region. A gate dielectric layer overlies the channel region of the semiconductor substrate, and a gate electrode overlies the gate dielectric layer. The channel region includes a first carbon-containing layer, a doped layer overlying the first carbon-containing layer, a second carbon-containing layer overlying the doped layer, and an intrinsic semiconductor layer overlying the second carbon-containing layer. The doped layer includes a dopant that is different than carbon.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: March 31, 2015
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: El Mehdi Bazizi, Francis Benistant
  • Patent number: 8987105
    Abstract: A method of manufacturing an SiC semiconductor device according to the present invention includes the steps of (a) by using a single mask, etching regions of an SiC semiconductor layer which serve as an impurities implantation region and a mark region, to form recesses, (b) by using the same mask as in the step (a), performing ion-implantation in the recesses of the regions which serve as the impurities implantation region and the mark region, at least from an oblique direction relative to a surface of the SiC semiconductor layer and (c) positioning another mask based on the recess of the region which serves as the impurities implantation region or the mark region, and performing well implantation in a region containing the impurities implantation region.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: March 24, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Noriaki Tsuchiya, Yoichiro Tarui
  • Patent number: 8963239
    Abstract: A superjunction device includes a substrate having first and second main surfaces and a first doping concentration of a first dopant. A first semiconductor layer having a second doping concentration of the first dopant is formed on the substrate. A second semiconductor layer is formed on the first layer and has a main surface. At least one trench extends from the main surface at least partially into the first semiconductor layer. A first region having a third doping concentration of the first dopant extends at least partially between the main surface and the first layer. A second region having a fourth doping concentration of a second dopant is disposed between the first region and a trench sidewall and extends at least partially between the main surface and the first layer. A third region having a fifth doping concentration of the first dopant is disposed proximate the main surface.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: February 24, 2015
    Assignee: Icemos Technology, Ltd.
    Inventors: Samuel Anderson, Takeshi Ishiguro, Kenji Sugiura
  • Patent number: 8853010
    Abstract: A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: October 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heung-Kyu Park, Woo-Bin Song, Nam-Kyu Kim, Su-Jin Jung, Byeong-Chan Lee, Young-Pil Kim, Sun-Ghil Lee
  • Patent number: 8841183
    Abstract: On a silicon substrate is formed a stacked body by alternately stacking a plurality of silicon oxide films and silicon films, a trench is formed in the stacked body, an alumina film, a silicon nitride film and a silicon oxide film are formed in this order on an inner surface of the trench, and a channel silicon crystalline film is formed on the silicon oxide film. Next, a silicon oxide layer is formed at an interface between the silicon oxide film and the channel silicon crystalline film by performing thermal treatment in an oxygen gas atmosphere.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: September 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshio Ozawa
  • Patent number: 8841187
    Abstract: Disclosed is a semiconductor device and a method for fabricating the semiconductor device. The method for fabricating the semiconductor device comprises steps of: forming a side cliff in a substrate in accordance with a gate mask pattern, the side cliff being substantially vertical to a substrate surface; forming a dielectric layer on the substrate that comprises the side cliff; etching the dielectric layer to have the dielectric layer left only on the side cliff, as a dielectric wall; and burying the side cliff by a substrate growth, the burying is performed up to a level higher than the upper end of the dielectric wall.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: September 23, 2014
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Meng Zhao
  • Publication number: 20140264582
    Abstract: A superjunction device includes a substrate having first and second main surfaces and a first doping concentration of a first dopant. A first semiconductor layer having a second doping concentration of the first dopant is formed on the substrate. A second semiconductor layer is formed on the first layer and has a main surface. At least one trench extends from the main surface at least partially into the first semiconductor layer. A first region having a third doping concentration of the first dopant extends at least partially between the main surface and the first layer. A second region having a fourth doping concentration of a second dopant is disposed between the first region and a trench sidewall and extends at least partially between the main surface and the first layer. A third region having a fifth doping concentration of the first dopant is disposed proximate the main surface.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 18, 2014
    Applicant: ICEMOS TECHNOLOGY LTD.
    Inventors: Samuel ANDERSON, Takeshi ISHIGURO, Kenji SUGIURA
  • Patent number: 8822294
    Abstract: The present invention provides a method for improving the write margins of the SRAM cells. The method comprises: before etching a polysilicon layer to form the polysilicon gates, performing a pre-implantation process to the polysilicon layer; wherein the polysilicon layer defines SRAM NMOSFETs regions and SRAM PMOSFETs regions; wherein the pre-implantation process comprises pre-implanting the fifth-group elements to the SRAM NMOSFETs regions and the NMOSFETs regions except to the SRAM NMOSFETs regions in the polysilicon layer, and pre-implanting the third-group elements to the PMOSFETs regions excluding the SRAM PMOSFETs regions in the polysilicon layer; wherein the process of pre-implanting the third-group elements comprises forming a pre-implantation photo mask capable of covering the SRAM PMOSFETs regions and using the pre-implantation photo mask to pre-implanting the third-group elements.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: September 2, 2014
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventor: Liujiang Yu
  • Patent number: 8822293
    Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate, wherein the semiconductor substrate and a sidewall of the gate dielectric has a joint point; forming a gate electrode over the gate dielectric; forming a mask layer over the semiconductor substrate and the gate electrode, wherein a first portion of the mask layer adjacent the joint point is at least thinner than a second portion of the mask layer away from the joint point; after the step of forming the mask layer, performing a halo/pocket implantation to introduce a halo/pocket impurity into the semiconductor substrate; and removing the mask layer after the halo/pocket implantation.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Yihang Chiu, Shu-Tine Yang, Jyh-Cherng Sheu, Chu-Yun Fu, Cheng-Tung Lin
  • Patent number: 8790981
    Abstract: A power field effect transistor (FET) is disclosed which is fabricated in as few as six photolithographic steps and which is capable of switching current with a high voltage drain potential (e.g., up to about 50 volts). In a described n-channel metal oxide semiconductor (NMOS) embodiment, a drain node includes an n-well region with a shallow junction gradient, such that the depletion region between the n-well and the substrate is wider than 1 micron. Extra photolithographic steps are avoided using blanket ion implantation for threshold adjust and lightly doped drain (LDD) implants. A modified embodiment provides an extension of the LDD region partially under the gate for a longer operating life.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: July 29, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Byron Neville Burgess, Sameer P. Pendharkar
  • Patent number: 8759916
    Abstract: Disclosed are embodiments of a metal oxide semiconductor field effect transistor (MOSFET) structure and a method of forming the structure. The structure incorporates source/drain regions and a channel region between the source/drain regions. The source/drain regions can comprise silicon, which has high diffusivity to the source/drain dopant. The channel region can comprise a silicon alloy selected for optimal charge carrier mobility and band energy and for its low source/drain dopant diffusivity. During processing, the source/drain dopant can diffuse into the edge portions of the channel region. However, due to the low diffusivity of the silicon alloy to the source/drain dopant, the dopant does not diffuse deep into channel region. Thus, the edge portions of the silicon alloy channel region can have essentially the same dopant profile as the source/drain regions, but a different dopant profile than the center portion of the silicon alloy channel region.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: June 24, 2014
    Assignee: International Business Machines Corporation
    Inventors: Andres Bryant, Edward J. Nowak
  • Patent number: 8691653
    Abstract: A semiconductor structure and a manufacturing process thereof are disclosed. The semiconductor structure includes a substrate having a first conductive type, a first well having a second conductive type formed in the substrate, a doped region having the second conductive type formed in the first well, a field oxide and a second well having the first conductive type. The doped region has a first net dopant concentration. The field oxide is formed on a surface area of the first well. The second well is disposed underneath the field oxide and connected to a side of the doped region. The second well has a second net dopant concentration smaller than the first net dopant concentration.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: April 8, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih-Chia Hsu, Yu-Hsien Chin, Yin-Fu Huang
  • Patent number: 8664067
    Abstract: An MOS transistor includes a doping profile that selectively increases the dopant concentration of the body region. The doping profile has a shallow portion that increases the dopant concentration of the body region just under the surface of the transistor under the gate, and a deep portion that increases the dopant concentration of the body region under the source and drain regions. The doping profile may be formed by implanting dopants through the gate, source region, and drain region. The dopants may be implanted in a high energy ion implant step through openings of a mask that is also used to perform another implant step. The dopants may also be implanted through openings of a dedicated mask.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: March 4, 2014
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Donald R. Disney
  • Patent number: 8664715
    Abstract: A transistor is formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: March 4, 2014
    Assignee: Advanced Analogic Technologies Incorporated
    Inventors: Donald R. Disney, Richard K. Williams
  • Patent number: 8643100
    Abstract: A FET includes a gate dielectric structure associated with a single gate electrode, the gate dielectric structure having at least two regions, each of those regions having a different effective oxide thickness, the FET further having a channel region with at least two portions each having a different doping profile. A semiconductor manufacturing process produces a FET including a gate dielectric structure associated with a single gate electrode, the gate dielectric structure having at least two regions, each of those regions having a different effective oxide thickness, the FET further having a channel region with at least two portions each having a different doping profile.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: February 4, 2014
    Assignee: Broadcom Corporation
    Inventor: Akira Ito
  • Patent number: 8633075
    Abstract: A method for manufacturing a semiconductor includes: forming an isolation region defining first, second and third active regions; implanting first impurity ions of a first conductivity type to form first, second and third wells; implanting second impurity ions of the first conductivity type to form first and second channel regions; implanting second impurity ions of a second conductivity to form a first drain region, such that a portion of the first channel region is overlapped with the first drain region; forming first, second and third gate electrodes, the first gate electrode superposing a portion of the first drain region and covering one lateral end of the first channel region; forming first insulating side wall spacers and a second insulating side wall spacer on a side wall of the first gate electrode; and implanting fourth impurity ions of the second conductivity type to form second drain/source regions.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: January 21, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Masashi Shima
  • Patent number: 8609510
    Abstract: Embodiments of the invention provide approaches for replacement metal gate (RMG) diffusion break formation. Specifically, a diffusion break is created after source/drain (S/D) formation, thereby allowing facet free and high quality S/D formation. A dummy gate body is removed selective to a sidewall section of a capping layer and a GOx layer formed over a substrate, and the opening is then extended through the GOx layer and into the substrate by etching the dummy gate body selective to the sidewall section of the capping layer. Retaining the capping layer during the dummy gate body etch enables the diffusion break to be self-aligned to the gate and eliminates device variability due to S/D volume variations. Processing then continues with RMG poly open chemical mechanical planarization (POC) and poly open planarization (POP).
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: December 17, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Srinvasa Banna, Andy C. Wei
  • Patent number: 8574991
    Abstract: An asymmetric transistor configuration is disclosed in which asymmetric extension regions and/or halo regions may be combined with an asymmetric spacer structure which may be used to further adjust the overall dopant profile of the asymmetric transistor.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: November 5, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Uwe Griebenow, Maciej Wiatr
  • Patent number: 8476684
    Abstract: Transistors having improved breakdown voltages and methods of forming the same are provided herein. In one embodiment, a method of forming a transistor comprises the steps of: forming a drain and a source by doping a semiconductor with a first dopant type to form a first type of semiconductor, the drain and source being separated from one another, wherein the drain comprises a first drain region of a first dopant concentration adjacent a second drain region, such that at least a portion of the second drain region is positioned between the first drain region and the source, and further comprising forming an intermediate region by doping the semiconductor so as to form a second type of semiconductor intermediate the drain and source, the intermediate region spaced apart from the second drain region.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: July 2, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Edward John Coyne, Paul Malachy Daly, Jagar Singh, Seamus Whiston, Patrick Martin McGuinness, William Allan Lane
  • Patent number: 8421163
    Abstract: A power module comprises: first and second terminals; first and second switching elements having a first electrode and a second electrode which is connected to the second terminal; first and second wirings respectively connecting the first electrodes of the first and second switching elements to the first terminal; and a third wiring directly connecting the first electrode of the first switching element to the first electrode of the second switching element, wherein parasitic inductances of the first and second wiring are different or switching characteristics of the first and second switching elements are different.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: April 16, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kazuaki Hiyama
  • Publication number: 20130078777
    Abstract: A method is provided for fabricating a transistor. According to the method, a doped material layer is formed on a semiconductor layer, and dopant is diffused from the doped material layer into the semiconductor layer to form a graded dopant region in the semiconductor layer. The graded dopant region has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer, with a gradual decrease in the doping concentration. The doped material layer is removed, and then a gate stack is formed on the semiconductor layer. Source and drain regions are formed adjacent to an active area that is in the semiconductor layer underneath the gate stack. The active area comprises at least a portion of the graded dopant region, and the source and drain regions and the active area have the same conductivity type.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 28, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo CHENG, Bruce B. DORIS, Ali KHAKIFIROOZ, Pranita KULKARNI, Tak H. NING
  • Patent number: 8389369
    Abstract: An electronic device can include a drain region of a transistor, a channel region of the transistor, and a doped region that is disposed under substantially all of the channel region, is not disposed under substantially all of a heavily doped portion of the drain region, and has a higher dopant concentration compared to the channel region. A process of forming an electronic device can include forming a drain region, a channel region, and a doped region, wherein the drain region has a conductivity type opposite that of the channel and doped region. After forming the drain, channel, and doped regions, the doped region is disposed under substantially all of the channel region, the doped region is not disposed under substantially all of a heavily doped portion of the drain region, and the drain region is laterally closer to the doped region than to the channel region.
    Type: Grant
    Filed: February 8, 2010
    Date of Patent: March 5, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Gary H. Loechelt
  • Patent number: 8330232
    Abstract: A multi-bit memory cell includes a substrate; a multi-bit charge-trapping cell over the substrate, the multi-bit charge-trapping cell having a first lateral side and a second lateral side; a source region in the substrate, a portion of the source region being under the first side of the multi-bit charge-trapping cell; a drain region in the substrate, a portion of the drain region being under the second side of the multi-bit charge-trapping cell; and a channel region in the substrate between the source region and the drain region. The channel region has one of a p-type doping and an n-type doping, and the doping is configured to provide a highest doping concentration near the central portion of the channel region.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: December 11, 2012
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Shao Hong Ku, Yin Jen Chen, Wenpin Lu, Tahui Wang
  • Publication number: 20120273880
    Abstract: An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 ?m deep into the body material but not more than 0.1 ?m deep into the body material. The source/drain zones (140 and 142 or 160 and 162) of a p-channel IGFET (120 or 122) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed.
    Type: Application
    Filed: October 26, 2010
    Publication date: November 1, 2012
    Inventors: Chih Sieh Teng, Constantin Bulucea, Chin-Miin Shyu, Fu-Cheng Wang, Prasad Chaparala
  • Patent number: 8294217
    Abstract: The semiconductor device includes a first transistor including a first impurity layer containing boron or phosphorus, a first epitaxial layer formed above the first impurity layer, a first gate electrode formed above the first epitaxial layer with a first gate insulating film formed therebetween and first source/drain regions, and a second transistor including a second impurity layer containing boron and carbon, or arsenic or antimony, a second epitaxial layer formed above the second impurity layer, a second gate electrode formed above the second epitaxial layer with a second gate insulating film thinner than the first gate insulating film formed therebetween, and second source/drain regions.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: October 23, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Kazushi Fujita, Junji Oh
  • Patent number: 8263466
    Abstract: A process for forming a FET (e.g., an n-FET or a p-FET), in which during formation a metal which makes up a source or drain of the transistor is stressed so that stress is induced in a semiconductor channel of the transistor.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: September 11, 2012
    Assignee: Acorn Technologies, Inc.
    Inventors: Paul Clifton, Daniel J. Connelly
  • Publication number: 20120208336
    Abstract: A method for manufacturing a semiconductor device includes forming a first gate electrode on a semiconductor substrate in a first transistor region; forming a channel dose region; and forming a first source extension region, wherein the channel dose region is formed by using a first mask as a mask and by ion-implanting a first dopant of the first conductivity type, and the first mask covering a drain side of the first gate electrode and covering a drain region, and the first source extension region is formed by using a second mask and the gate electrode as masks and by ion-implanting a second dopant of a second conductivity type that is a conductivity type opposite to the first conductivity type, the second mask covering the drain side of the first gate electrode and covering the drain region.
    Type: Application
    Filed: April 19, 2012
    Publication date: August 16, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Masashi SHIMA
  • Patent number: 8222657
    Abstract: A light emitting apparatus may include a gate metal positioned between a p-type contact and an n-type contact, a gate oxide or other dielectric stack positioned below and attached to the gate metal, a Ge or Si1-zGez channel positioned below and attached to the gate dielectric stack, a buffer, and a silicon substrate positioned below and attached to the buffer. The light emitting apparatus may alternatively include a gate metal positioned between a p-type contact and an n-type contact, a wide bandgap semiconductor positioned below and attached to the gate metal, a Ge or Si1-zGez channel positioned below and attached to the wide bandgap semiconductor, a buffer, and a silicon substrate positioned below and attached to the buffer. Embodiments of the light emitting apparatus may be configured for use in current-injected on-chip lasers, light emitting diodes or other light emitting devices.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: July 17, 2012
    Assignee: The Penn State Research Foundation
    Inventors: Jian Xu, Somasundaram Ashok