Abstract: A method for producing a semiconductor device which comprises causing a dopant present in a semiconductor substrate to segregate in the surface of said semiconductor substrate, thereby forming a thin layer which has a higher dopant concentration than said substrate. The thin layer formed by segregation prevents punch-through which occurs as the result of miniaturization of MOSFET. This method permits economical delta doping without sacrificing the device characteristics.

Abstract: A contactless acceleration switch detects a threshold acceleration value when a mass attached to a spring, moves towards a source, a drain, and a threshold adjustment channel implanted in a substrate layer. The threshold adjustment channel is located between the source and the drain. The implanted area is located between insulator posts. A spring is attached to the insulator posts. A mass is held above the implanted area by the spring. When the threshold acceleration value is detected, the mass moves towards the substrate layer. The threshold adjustment channel then inverts causing current to flow between the source and the drain, providing an electrical signal indicating that the threshold acceleration value has been reached.

Abstract: A MOS transistor having a recessed gate electrode and a fabrication method thereof are provided. The MOS transistor includes an isolation layer formed at a predetermined region of a semiconductor substrate to define an active region and double trench regions formed in the active region. The double trench region is composed of an upper trench region crossing the active region and a lower trench region located under the upper trench region. Thus, the active region is divided into two sub-active regions. Sidewalls of the upper trench region are covered with a spacer, which is used as an etching mask to form the lower trench region in the semiconductor substrate of the upper trench region. The upper and lower trench regions are then filled with a gate electrode. Also, high concentration source/drain regions are formed at the top surfaces of the sub-active regions respectively. Therefore, an effective channel length of the MOS transistor is determined according to the dimension of the lower trench region.

Abstract: Deterministically doped field-effect devices and methods of making same. One or more dopant atoms, also referred to as impurities or impurity atoms, are arranged in the channel region of a device in engineered arrays. Component atoms of an engineered array are substantially fixed by controlled placement in order to provide a barrier topology designed to control of source-drain carrier flow to realize an ultra-small device with appropriate, consistent performance characteristics. Devices can be made by placing atoms using proximity probe manipulation, ion implantation, by facilitating self-assembly of the atoms as necessary, or other techniques. These atomic placement techniques are combined in example embodiments with traditional methods of forming a substrate, insulators, gates, and any other structural elements needed in order to produce practical field-effect devices.

Abstract: A method and device for manufacturing a mask ROM integrated circuit device to reduce influences of punch through between source and channel regions that output improper program readings. The method includes forming well regions using an implant process on semiconductor substrate and forming a plurality of buried implant regions through first patterned mask. The first patterned mask is formed overlying the semiconductor substrate. Each of the buried implant regions includes a source region and a drain region for each respective memory cell region. The memory cell region is one of a plurality of memory cell regions. The method also forms pocket regions adjacent to a vicinity of each of the buried implant regions within the channel region for each of the memory cell regions. A first pocket region is defined between the channel region and source region and a second pocket region is defined between the channel region and the drain region for each memory cell region.

Abstract: An ion-implantation machine has an implantation chamber with a vent inlet; a vacuum pump is connected to the implantation chamber through a vacuum valve. A pipe connects the vent inlet of the implantation chamber to a source of a fluid containing oxygen. The fluid containing oxygen is preferably environmental air. A flow-rate control valve is arranged on the pipe and is activated only after closing the vacuum valve.

Abstract: A method for improving the channel doping profile of deep-submicron field effect transistors and MOSFETs. The method involves a highly localized halo implant formed in the channel region but not in the source/drain junction. The halo implant is performed through a gap formed by removal of a temporary spacer. The MOSFET is then further completed.

Abstract: In a method of manufacturing a semiconductor device comprising a semiconductor body 1 which is provided at a surface 2 with a transistor comprising a gate structure 21, a patterned layer 10 is applied defining the area of the gate structure 21. Subsequently, a dielectric layer 18 is applied in such a way, that the thickness of the dielectric layer 18 next to the patterned layer 10 is substantially equally large or larger than the height of the patterned layer 10, which dielectric layer 18 is removed over part of its thickness until the patterned layer 10 is exposed. Then, the patterned layer 10 is subjected to a material removing treatment, thereby forming a recess 19 in the dielectric layer 18, and a contact window 28,29 is provided in the dielectric layer.

Abstract: A method for forming an electrically programmable read-only memory(EPROM) includes forming a first p+ doped region, a second p+ doped region, and a third p+ doped region on an N-well, forming a control gate between the first p+ doped region and the second p+ doped region, and forming a p+ floating gate between the second p+ doped region and the third p+ doped region.

Abstract: A method of forming a semiconductor device is provided that comprises forming a gate conductor proximate to and insulated from an outer surface of a semiconductor substrate. The gate conductor defines a channel region disposed inwardly from the gate conductor. Source and drain regions are formed in the semiconductor substrate, each disposed adjacent one edge of the channel region. The semiconductor substrate and the source and drain regions have an associated bottom wall junction capacitance. A transient enhanced diffusion anneal is used to affect ion concentration profiles associated with the source and drain regions, resulting in an increased balance in the ion concentration profiles of the source and drain regions and an ion concentration associated with the semiconductor substrate, which results in reduction of the bottom wall junction capacitance.

Abstract: The present invention provides a thin-film transistor (TFT) and its production method which enables an arrangement restraining bipolar transistor type behavior, in order to stabilize saturation current and to provide a TFT that can improve reliability. The TFT includes a channel region facing a gate electrode through a gate insulating film, a source electrode connected to the channel region and a drain region connected to the channel region on the side opposite this source region are formed in a polycrystal semiconductor film that was patterned in island forms. In the channel region, a recombination center is formed for capturing a small number of carriers (holes) by introducing impurities, such as inert gases, metals, Group III elements, Group IV elements and Group V elements after a crystallization process is carried out on a semiconductor film 100.

Abstract: An impurity ion of a polarity opposite to that of an impurity ion forming an n-type diffusion layer is implanted into a lower portion of the n-type diffusion region in a region, in which n-channel type MISFET is to be formed, vertically with respect to a main surface of a semiconductor to form a first p-type pocket layer. Subsequently, an impurity of a p conduction type is implanted into a region between the n-type diffusion region and the first p-type pocket layer obliquely relative to the main surface of the semiconductor substrate to form a second p-type pocket layer. In this arrangement, the concentration of the impurity ion forming the second p-type pocket layer is made higher than the concentration of the impurity ion used to form the first p-type pocket layer.

Abstract: A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention reduces the cost and complexity associated with the fabrication of a semiconductor circuit that includes a depletion-mode transistor.

Abstract: In one embodiment, a buried-channel transistor is fabricated by masking a portion of an active region adjacent to a trench and implanting a dopant in an exposed portion of the active region to adjust a threshold voltage of the transistor. By masking a portion of the active region, the dopant is substantially prevented from getting in a region near an edge of the trench. Among other advantages, this results in reduced leakage current.

Abstract: The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying sub-regions. The invention also includes a semiconductor construction that has transistor constructions with insulative spacers along gate sidewalls. Each transistor construction is between a pair source/drain regions that extend beneath the spacers. A source/drain extension extends the source/drain region farther beneath the transistor constructions on only one side of each of the transistor constructions. The invention also includes methods of forming semiconductor constructions.

Abstract: A semiconductor device comprising a gate having an approximately 0.05 &mgr;m channel length, an oxide layer below the gate, a self-aligned compensation implant below the oxide layer, a halo implant surrounding the self-aligned compensation implant below the oxide layer; and gate and drain regions on opposite sides of the halo implant and below the oxide layer.

Abstract: A method of fabricating a MOS transistor is provided. According to the method, a rapid thermal anneal is applied to a semiconductor substrate having active regions doped with well impurity ions and channel impurity ions. Thus, during implantation of the well and the channel impurity ions, crystalline defects resulting from the implantation can be cured by the rapid thermal anneal.

Abstract: A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches.

Abstract: In a method for fabricating a metal oxide semiconductor (MOS) transistor, which can reduce the junction capacitance without a degradation of characteristics in a transistor even in gate line narrowing, the method comprising the steps of: forming a buffer oxide layer on a semiconductor substrate having an isolation layer; successively conducting ion implantations for well formation and field stop formation in an active region of the substrate through the buffer oxide layer; removing the buffer oxide layer; forming a sacrificial layer of the semiconductor substrate; patterning the sacrificial layer to form a trench defining a gate electrode forming region; successively conducting ion implantations for threshold voltage adjustment and punch stop formation on the semiconductor substrate area exposed by the trench; forming a gate oxide layer on the surface of the substrate under the bottom face of the trench; forming a polysilicon layer on the sacrificial layer so as to completely bury the trench; polishing the po

Abstract: A gate electrode is formed on a semiconductor substrate with a gate insulating film interposed therebetween. A channel region composed of a first-conductivity-type semiconductor layer is formed in a region of a surface portion of the semiconductor substrate located below the gate electrode. Source/drain regions each composed of a second-conductivity-type impurity layer are formed in regions of the surface portion of the semiconductor substrate located on both sides of the gate electrode. Second-conductivity-type extension regions are formed between the channel region and respective upper portion of the source/drain regions in contact relation with the source/drain regions. First-conductivity-type pocket regions are formed between the channel region and respective lower portion of the source/drain regions in contact relation with the source/drain regions and in spaced relation to the gate insulating film.

Abstract: A sub-0.05 &mgr;m channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. In accordance with the method of the present invention, at least one dummy gate region is first formed atop an SOI layer. The dummy gate region includes at least a sacrificial polysilicon region and first nitride spacers located on sidewalls of the sacrificial polysilicon region. Next, an oxide layer that is coplanar with an upper surface of the dummy gate region is formed and then the sacrificial polysilicon region is removed to expose a portion of the SOI layer. A thinned device channel region is formed in the exposed portion of the SOI layer and thereafter inner nitride spacers are formed on exposed walls of the fist nitride spacers. Next, a gate region is formed over the thinned device channel region and then the oxide layer is removed so as to expose thicker portions of the SOI layer than de device channel region.

Abstract: A semiconductor device includes a gate insulating film formed on a semiconductor substrate between first diffusion layers, a gate electrode including a first gate portion formed on the gate insulating film and a second gate portion formed on the first gate portion, a first width in a channel direction of the first gate portion being substantially equal to a width in that of the gate insulating film, and a second width in the channel direction of the second gate portion being larger than the first width, a gate side wall insulating film including a first side wall portion formed on a side surface of the first gate portion and the gate insulating film and a second side wall portion formed on a side surface of the second gate portion, and a second diffusion layer formed apart from the first diffusion layers below the gate insulating film.

Abstract: A method for processing dual threshold nMOSFETs and pMOSFETs requiring only one additional masking and implantation operation over single threshold MOSFETs is disclosed. The additional mask and implant operation both enhances the threshold voltage doping of one type of FET and compensates the threshold voltage doping of another type of FET. Where a first threshold voltage implant sets the threshold voltage for an NMOS device to a low threshold voltage, and a second threshold voltage implant sets the threshold voltage for a PMOS device to a high threshold voltage, a third implant may both enhance a NMOS device threshold implant to set the threshold voltage high while compensating a PMOS device threshold implant to set the threshold voltage low.

Abstract: Disclosed is a method for correcting a transistor of a predetermined threshold value. According to the method, after preparing a gate 13 of the transistor, depending on how well the gate is prepared, a threshold voltage Vth showing transistor characteristic is corrected by adjusting an oxygen concentration of a lamp-annealing step 21, which is to be performed subsequently. Moreover, disclosed is a method for fabricating a transistor of a predetermined threshold value. According to the method, after preparing the gate 13 of the transistor, the threshold voltage Vth showing the transistor characteristic is predicted or measured. When the threshold voltage deviates from the predetermined value, the oxygen concentration is adjusted in the lamp-annealing step 21 of the transistor that is to be fabricated subsequently and thus the threshold value is set to the predetermined value without lowered reliability due to the damage of the gate oxide film and without additional process steps.

Abstract: A method for manufacturing a semiconductor memory device is disclosed. A spacer of a material having a high etching selection ratio with respect to an interdielectric layer is formed on a sidewall of a gate electrode. A refractory metal silicide layer is formed on an upper surface of the gate electrode and on an upper surface of a substrate on which source and drain regions are formed, thereby providing a contact hole self-aligned between the gate electrodes. Also, an ion implantation process is performed on the entire active region after the contact hole is filled with metal such as tungsten, and an impurity region is formed only on a lower portion of the gate electrode.

Abstract: The present invention relates to a transistor of a semiconductor and a method of fabricating the same. In the method, the dual gate electrode may have different widths and is formed using a damascene process. The dual gate electrode is formed using a stacked upper having a first gate electrode and a second gate electrode. The second gate electrode may have a broader width than the lower first gate electrode.

Abstract: A method of producing a SOI MOSFET which includes a fully depleted channel region of a first conductivity type formed in a top semiconductor layer disposed on an insulative substrate, source/drain regions of a second conductivity type formed to sandwich the channel region and a gate electrode formed on the channel region with intervention of a gate insulating film, the method comprises: forming the channel region by setting an impurity concentration of channel edge regions of the channel region adjacent to the source/drain regions higher than an impurity concentration of a channel central region of the channel region, and setting a threshold voltage Vth0 of the channel central region and a threshold voltage Vthedge of the channel edge regions so that a change of the threshold voltage Vth0 with respect to a change of the thickness of the top semiconductor layer and a change of the threshold voltage Vthedge with respect to the change of the thickness of the top semiconductor layer are of opposite sign.

Abstract: Disclosed herein is a method of fabricating a semiconductor device using a damascene process. The method comprises the steps of: forming a dummy gate electrode on a semiconductor substrate; forming a source/drain region in the substrate; polishing and planarizing an interlayer insulating film formed on the substrate to expose the dummy gate electrode; etching the dummy gate electrode to form a groove in an exposed portion of the substrate; implanting impurity ions into the exposed portion of the substrate to form a delta-doping layer; thermally treating the semiconductor substrate to activate the implanted impurity ions; growing a silicon film on the exposed portion of the substrate by a selective epitaxial process; depositing a gate insulating film on the surface of the groove; and depositing a gate metal film on the gate insulating film in the groove, forming the gate electrode.

Abstract: A fabrication method for a read only memory provides a substrate having a memory cell region and a periphery circuit region. A memory cell region has a memory cell array and the periphery circuit region has transistors. A precise layer having a plurality of first openings is formed in the memory cell region. The first openings are above the channel region of each memory cell in the memory cell array and the critical dimension of the first openings is identical. A mask layer having second openings and third openings is formed on the substrate. The second openings locate over a pre-coding memory cell region, and the third openings locate over the transistor gates. An ion implantation is performed to code the memory cell in the pre-coding memory cell region and to adjust the threshold voltage of the transistor, using the precise layer and the mask layer as a mask.

Abstract: A sub-0.05 &mgr;m channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. The sub-0.05 &mgr;m channel length fully-depleted SOI MOSFET device includes an SOI structure which contains at least an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein the second thickness is greater than the first thickness and the source/drain regions having a salicide layer present thereon. A gate region is present also atop the SOI layer.

Abstract: A trench is formed in a substrate and a silicon oxide film which serves as a trench isolation is buried in the trench. The silicon oxide film has no shape sagging from a main surface of the substrate. A channel impurity layer to control a threshold voltage of a MOSFET is formed in the main surface of the substrate. The channel impurity layer is made of P-type layer, having an impurity concentration higher than that of the substrate. A first portion of the channel impurity layer is formed near an opening edge of the trench along a side surface of the trench in the source/drain layer, and more specifically, in the N+-type layer. A second portion of the channel impurity layer is formed deeper than the first portion. A gate insulating film and a gate electrode are formed on the main surface of the substrate.

Abstract: A gate electrode is formed in a partial area of the surface of a semiconductor substrate. Impurities of a first conductive type are implanted into the semiconductor substrate in areas on both sides of the gate electrode, by using the gate electrode as a mask. The implanted impurities are activated by applying a laser beam to the surface of the semiconductor substrate. Impurities to be used for threshold voltage control are implanted into the surface layer of the semiconductor substrate under the gate electrode, after the laser beam is applied. The impurities for threshold voltage control are activated by heating the semiconductor substrate. A semiconductor device is provided having a low parasitic resistance of source/drain regions and a desired threshold voltage hard to be lowered.

Abstract: A method for fabricating a non-volatile memory is described. A planar doped region is formed in the substrate at first. A mask layer and a patterned photoresist layer are sequentially formed on the substrate. A plurality of trenches is formed in the substrate with the patterned photoresist layer as a mask to divide the planar doped region into a plurality of bit-lines. The patterned photoresist layer is removed and then a recovering process is performed to recover the side-walls and the bottoms of the trenches from the damages caused by the trench etching step. The mask layer is removed. A dielectric layer is formed on the substrate and then a plurality of word-lines is formed on the dielectric layer.

Abstract: A method for processing dual threshold nMOSFETs and pMOSFETs requiring only one additional masking and implantation operation over single threshold MOSFETs is disclosed. The additional mask and implant operation both enhances the threshold voltage doping of one type of FET and compensates the threshold voltage doping of another type of FET. Where a first threshold voltage implant sets the threshold voltage for an NMOS device to a low threshold voltage, and a second threshold voltage implant sets the threshold voltage for a PMOS device to a high threshold voltage, a third implant may both enhance a NMOS device threshold implant to set the threshold voltage high while compensating a PMOS device threshold implant to set the threshold voltage low.

Abstract: A method of forming an MOS integrated circuit having at least two types of NFET, each type having a different threshold voltage, and at least two types of PFET, each type having a different threshold voltage, includes forming at least four active regions in a substrate, each region having a different doping profile. A conventional two threshold voltage CMOS process is modified to produce four transistor threshold voltages with only one additional masked implant operation. This additional implant raises the threshold voltage of one type of MOSFET while lowering that of the other MOSFET type.

Abstract: A method for providing low power MOS devices that include resistive paths specifically designed to provide a specified resistance between the bulk material of the device and a well tie contact. By providing a resistive path, an equivalent RC circuit is introduced to the device that allows the bulk material potential to track the gate potential, thereby advantageously lowering the threshold voltage as the device turns on and raising the threshold voltage as the device turns off. In addition, the introduction of the resistive path also allows the bulk material potential to be controlled and stabilize at an equilibrium potential between switching events.

Abstract: A transistor (30) and method for forming a transistor using an edge blocking material (24) is disclosed herein. The edge blocking material (24) may be located adjacent a gate (22) or disposable gate or may be part of a disposable gate. During an angled pocket implant, the edge blocking material (24) blocks some dopant from entering the semiconductor body (10) and the dopant (18) placed under the edge blocking material is located at a given distance below the surface of the semiconductor body (10).

Abstract: In a semiconductor device including a plurality of n-channel transistors having different threshold voltages and each having a gate electrode including an n-type polysilicon film, the impurity concentration of the n-type polysilicon film included in the gate electrode of an n-channel transistor having a relatively high threshold, is lower than the impurity concentration of the n-type polysilicon film included in the gate electrode of an n-channel transistor having a relatively low threshold. Thus, the n-channel transistor having a relatively high threshold can be realized in the semiconductor device, without various problems such as an increased leak current caused by increasing the impurity concentration of the channel region, the lowered subthreshold factor caused by using the p+ polysilicon film in the gate electrode, the deteriorated insulating performance of the gate oxide film, the increased number of fabricating steps, or the dropped reliability of the transistor.

Abstract: A technique of fabricating a nonvolatile device includes forming a low doping region to aid in the reduction of substrate hot electrons. The nonvolatile device may be a floating gate device, such as a Flash, EEPROM, or EPROM memory cell. The low doping region has a lower doping concentration than that of the substrate. By reducing substrate hot electrons, this improves the reliability and longevity of the nonvolatile device.

Abstract: A process for preparing a silicon surface for gate dielectric formation. The silicon is annealed in a hydrogen ambient prior to gate dielectric formation. The gate dielectric is then formed, along with other layers of the gate structure. The channel is then implanted with an ion implant through the gate material.

Abstract: To provide a semiconductor device and a process for manufacturing the same which is capable of suppressing short channel effect and preventing a current from leaking between a contact and a silicon substrate. The semiconductor device of the present invention comprises a silicon substrate on which a source/drain area (3 in FIG. 1), a silicon oxide layer (4 in FIG. 1) and a silicon nitride layer (5 in FIG. 1) are successively formed in this order, and a trench which extend through said layers to split the source/drain area. A columnar gate electrode (9 in FIG. 1) is formed within the trench in such a manner that it is spaced from the inner wall of the trench and a lightly doped drain (LDD) area (10 in FIG. 1) is formed at an area of the bottom of the trench in which no gate electrode is disposed. In such a structure, the short channel effect which occurs in association with reduction in the gate length is suppressed.

Abstract: A method of adjusting the threshold voltage in an ultra-thin SOI MOS transistor includes preparing a SOI substrate; thinning the SOI top silicon film to a thickness of between about 10 nm and 50 nm; forming an absorption layer on the top silicon film; and implanting ions into the top silicon film through the absorption layer.

Abstract: A fabrication method for a mask read-only memory includes forming an oxide layer on a provided substrate. A first mask layer is formed on the oxide layer, followed by performing a first ion implantation to form a plurality of equally spaced bit lines. A thermal process is further conducted to convert the oxide layer to a denser oxide layer. A plurality of word lines, which is perpendicular to the bit lines, is formed on the denser oxide layer. A second mask layer is formed on the plurality of the word lines, exposing the channel to be coded. A second ion implantation is conducted on the channel to complete the fabrication of the mask read-only memory device.

Abstract: In a method of manufacturing a semiconductor device comprising a semiconductor body (1) of a first conductivity type which is provided at a surface (2) with a transistor having a gate (28) insulated from a channel (13) provided at the surface (2) of the semiconductor body (1) by a gate dielectric (26), a structure is provided on the surface (2) comprising a dielectric layer (14) having a recess (16), which recess (16) is aligned to a source zone (11,9) and a drain zone (12,9) of a second conductivity type provided at the surface (2) of the semiconductor body (1) and has side walls (17) extending substantially perpendicularly to the surface (2) of the semiconductor body (1).

Abstract: A method for manufacturing a discrete power rectifier device having a VLSI multi-cell design employs a two spacer approach to defining a P/N junction profile having good breakdown voltage characteristics. The method provides highly repeatable device characteristics at reduced cost. The active channel regions of the device are also defined using the same two spacers. The method is a self-aligned process and channel dimensions and doping characteristics may be precisely controlled despite inevitable process variations in spacer formation. Only two masking steps are required, and additional spacers for defining the body region profile can be avoided, reducing processing costs.

Abstract: A method for making a high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first substrate of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. The first substrate is flipped over and then bonded to a second substrate of the first conductivity type. After the first substrate has been thinned, another set of implants are successively performed so as to form a second plurality of buried layers in stacked parallel relationship to the first plurality of buried layers.

Abstract: A method of fabricating a semiconductor transistor device comprising the following steps. A semiconductor structure is provided having an upper silicon layer, a pad dielectric layer over the upper silicon layer, and a well implant within a well region in the upper silicon layer. A lower SiN layer is deposited and patterned over the pad dielectric layer to define a lower gate area. The pad dielectric layer and the upper silicon layer within the lower gate area is etched to form a lower gate trench having a predetermined width. A lower gate portion is formed within the lower gate trench. An upper oxide layer is formed over the lower SiN layer. An upper SiN layer is formed over the upper oxide layer. The upper SiN layer is etched to define an upper gate trench having a predetermined width greater than the lower gate trench predetermined width. An upper gate portion is formed within the upper gate trench, wherein the lower and upper gate portions form a T-shaped gate.

Abstract: Work function control layers are provided in in-laid, metal gate electrode, Si-based MOS transistors and CMOS devices by a process which avoids deleterious dopant implantation processing resulting in damage to the thin gate insulator layer and undesirable doping of the underlying channel region. According to the invention, an amorphous Si layer is formed over the thin gate insulator layer by a low energy deposition process which does not adversely affect the gate insulator layer and subsequently doped by means of another low energy process, e.g., low sheath voltage plasma doping, which does not damage the gate insulator layer or dope the underlying channel region of the Si-based substrate. Subsequent thermal processing during device manufacture results in activation of the dopant species and conversion of the a-Si layer to a doped polycrystalline Si layer of substantially increased electrical conductivity.

Abstract: A semiconductor device which is capable of operating with a single positive power supply and has a low gate resistance, and a process for production thereof.

Abstract: Methods of fabricating a high power RF lateral diffused MOS transistor (LDMOS) having increased reliability includes fabricating an N-drift region for the drain prior to fabrication of the gate contact and other process steps in fabricating the transistor. The resulting device has reduced adverse affects from hot carrier injection including reduced threshold voltage shift over time and reduced maximum current reduction over time. Linearity of device is maximized along with increased reliability while channel length is reduced.