Abstract: Following with the formation of pad insulator layer and a stacked layer stacked, a gate insulator is formed within the defined gate insulator space. A lightly doped region is doped and the stacked layer and the pad insulator layer is removed. A semiconductor layer is formed and a gate space is defined over the gate insulator through a spacer structure. An anti punchthrough region is formed followed by the formation of a first insulator layer. A gate filling is then formed to fill within the gate space. A portion of the first insulator layer is then removed. A step of doping a plurality of junction ions is applied. A second insulator layer is formed and a thermal process is then proceeded. Finally a metalization process is employed on the semiconductor substrate.

Abstract: The present invention discloses a MOS transistor which is capable of reducing an area of a diffusion layer of a source and drain, and is capable of reducing the number of manufacturing processes while enhancing flatness of a surface of the device. A selective silicon epitaxial layer is formed in an element region which is defined by an element isolation insulating layer formed in a silicon substrate. In the element isolation insulation layer, a polysilicon layer and a selective polysilicon layer connected to the selective silicon epitaxial layer are formed as a source and drain electrode. An LDD region and a source and drain region are formed in the selective silicon epitaxial layer, and a leading electrode for the source and drain region is formed in the source and drain electrode.

Abstract: A method for fabricating a MOS transistor with an inverse T-shaped air-gap gate structure on a semiconductor substrate is disclosed. The T-shaped air-gap gate structure reduces the parasitic resistance and capacitance; hence device structure operation speed can be improved. The method comprises the following steps: firstly, a gate hollow is defined in the pad oxide/nitride layer. Next an ultra-thin nitrogen rich dielectric as a gate oxide is formed. After that, a thin .alpha.-Si is deposited, then an ion implantation is done to form a punchthrough stopping region. After forming a CVD oxide film, an anisotropic etching is followed to form oxide spacers. An undoped silicon layer then followed to refill the gate hollow region. A CMP processes or a dry etching is done to remove silicon layer until the nitride layer is exposed. Subsequently, the oxide spacers is removed to expose a dual hollow. A LDD implantation is then implanted into the substrate.

Abstract: An ultra-short channel MOSFET with the self-aligned silicided contact and the extended ultra-shallow source/drain junction is formed. An extremely short gate region can be defined without being limited with the bottleneck of the existed lithography technology. A good quality gate insulator layer forming from the regrowth of an oxynitride film is provided. A self aligned metal silicide process is performed to form the contacts. A disposable spacer structure is used to remove metal residue and thus the possible path for leakage is eliminated. An ultra shallow region is formed employing the metal silicide as a diffusion source. An extented source/drain region is provided.

Abstract: A method of fabricating a MOSFET device, in which a source and drain region has been formed, prior to the formation of an ion implanted channel region, has been developed. The early creation of source and drain region allows a high temperature anneal to be performed, removing damage resulting from the source and drain ion implantation procedures, however without redistribution of channel dopants. The method features creating an opening in an insulator layer, after the source and drain formation, and then forming the channel region in the semiconductor substrate, directly underlying the opening in the insulator layer. A polysilicon gate structure is next formed in the opening, resulting in self-alignment to the underlying channel region.

Abstract: A gate oxide layer and a polysilicon layer are formed in sequence over the major surface of a semiconductor substrate. A photoresist layer is formed on the polysilicon layer and an opening is formed in the photoresist layer. Using the photoresist layer as a mask, boron is ion implanted through the polysilicon layer and the gate oxide layer into the semiconductor substrate. Phosphorus is next ion implanted into the polysilicon layer by using the photoresist layer as a mask. Different ion species are ion implanted into the semiconductor substrate and the polysilicon layer, respectively, by using the same photoresist layer, thus decreasing the number of photoetching steps in manufacture of semiconductor devices.

Abstract: A channel region formation process in field effect transistors directed toward reducing threshold voltage sensitivity to variations in gate length resulting from manufacturing techniques. A polysilicon gate is formed over the substrate and a channel region is subsequently implanted at a large angle measured from perpendicular to the substrate. Large angle implantation results in a non-uniform doping concentration in the channel region, improving threshold voltage sensitivity. Improvement can also be seen in other parameters, including source-drain current, substrate current, leakage current, magnification factor, and hot electron channel injection efficiency.

Abstract: A fabrication method for a semiconductor memory device with a non-uniformly doped channel(hereinafter, called NUDC) formed in a semiconductor substrate with a thin central portion that becomes gradually thicker toward the edges of the substrate. The method includes forming an impurity-bearing layer on a semiconductor substrate, selectively etching the impurity containing layer in a manner such that the portion of the impurity-bearing layer serving as a gate region is formed to be thin at a central portion thereof and gradually thickens as it nears the edges thereof; forming a first conductive impurity region by driving the impurity from the impurity containing layer into the semiconductor substrate, stripping the impurity containing layer, sequentially forming a gate insulating film and a gate electrode on the semiconductor substrate, and forming a second conductive impurity region in the semiconductor substrate at the sides of the gate electrode.

Abstract: A semiconductor processing method for forming self-aligned T-gate Lightly-Doped Drain (LDD) device of recessed channel is presented. The method comprises the steps of covering a substrate with pad oxide, forming a lightly-doped layer by ion implantation, depositing a silicon nitride layer on the surface of the pad oxide, and etching the silicon nitride layer according to a predefined mask pattern to expose the silicon oxide layer and to form a gate region. A polysilicon spacer region is formed on the side-walls of the silicon nitride layer. Anisotropic etch is used to etch the polysilicon spacer region, and at the same time etch the exposed pad oxide and a portion of the substrate to form a T-shaped groove. An amorphous silicon layer is deposited in the T-shaped groove after forming a thin oxide layer, then the amorphous silicon deposited apart from the T-shaped groove region is removed. The silicon nitride layer is removed to form a T-gate.

Abstract: In forming a P.sup.- body diffused layer in a portion on the source side of an N.sup.- drain diffused layer of a DMOSFET, P-type impurity ions are implanted at a large tilt angle to reach a part of a region underlying an N.sup.+ gate electrode by using, as a mask, a resist film having an opening corresponding to a region in which the body diffused layer of the DMOSFET is to be formed and the N.sup.+ gate electrode so as to be activated. Thereafter, an N.sup.+ source diffused layer and an N.sup.+ drain diffused layer are formed in the P.sup.- body diffused layer and in the N.sup.- drain diffused layer, respectively. Since a high-temperature drive-in process need not be performed to introduce the P-type impurity ions into the region underlying the N.sup.+ gate electrode, a reduction or variations in threshold voltage and the degradation of a gate oxide film each caused by the impurity diffused from the N.sup.+ gate electrode can be prevented.

Abstract: A MOS transistor is fabricated by forming an inverse gate mask consisting of a lower silicon dioxide layer and an upper silicon nitride layer. The exposed channel region is thermally oxidized. The mask is removed to permit a source/drain implant. The oxide growth is removed so that the channel region is recessed. A differential oxide growth then serves to mask the source and the drain for channel threshold adjust and punch-through implants. A doped polysilicon gate is formed, with the thinner area of the differential oxide serving as the gate oxide. In the resulting structure, the punch-through dopant is spaced from the source and the drain, reducing parasitic capacitance and improving transistor switching speeds.

Abstract: The present invention relates to forming a narrow gate MOSFET having a local ion implantation to reduce the junction capacitance. A polysilicon layer is formed over a semiconductor substrate. An opening is formed in the polysilicon layer by using patterning and etching. Subsequently, a thermal oxidation is performed to oxidize the polysilicon layer into a polysilicon-oxide layer that is expanded in volume relative to the polysilicon layer thereby narrowing said opening. Then an ion implantation is performed by using said polysilicon-oxide layer as a mask.

Abstract: A MOSFET includes a semiconductor substrate of a first conductivity type including a field region and an active region; a gate insulating film on a portion of the active region, the gate insulating film having two edge parts and a mid-part, the two edge parts being thicker than the mid-part; a gate electrode on the gate insulating film; sidewall spacers on the sides of the gate electrode and the gate insulating film; heavily doped regions of a second conductivity type in the semiconductor substrate under the two edge parts of the gate insulating film; normally doped regions of the second conductivity type in the semiconductor substrate on both sides of the gate insulating film; lightly doped regions of the second conductivity type in the semiconductor substrate on the sides of the sidewall spacers; and doped regions of the first conductivity type below the normally doped region of the second conductivity type under the sidewall spacers.

Abstract: Single crystal aluminum is deposited on SiGe structures to form metal interconnects. Generally, a method of forming single crystal aluminum on Si.sub.(1-X) Ge.sub.X is presented, including the steps of maintaining the substrate at certain temperature (e.g. between 300.degree. C. and 400.degree. C.) and pressure conditions (e.g. below 2.times.10.sup.-9 millibar) while aluminum atoms are deposited by a vacuum evaporation technique. This is apparently the first method of depositing single crystal aluminum on SiGe surfaces. Novel structures are made possible by the invention, including epitaxial layers 34 formed on single crystal aluminum 32 which has been deposited on SiGe 30. Among the advantages made possible by the methods presented are thermal stability and resistance to electromigration.

Abstract: Methods of forming semiconductor active regions having channel-stop regions therein include the steps of forming an oxide layer and first nitride layer on a face of a semiconductor substrate and then patterning the first nitride layer to expose first portions of the oxide layer. The patterned first nitride layer is then used as a mask during implantation of dopants of second conductivity type into the substrate. A second nitride layer is then deposited on the exposed first portions of the oxide layer and on the first nitride layer. A second photoresist layer is then patterned and used as a mask to etch the second nitride layer and patterned first nitride layer, to expose second portions of the oxide layer. A third photoresist layer is then patterned to cover the first portions of the oxide layer. The patterned third photoresist layer and remaining portions of the patterned first and second nitride layers are then used as implant masks during implantation of second conductivity type dopants.

Abstract: A method of fabricating a short-channel MOS device on a substrate is provided. First, stacked pad oxide/nitride layers are formed on the substrate. Then a patterned photoresist film is formed on the planned gate region which covers the gate region and its sidewall spacers. A LPD (Liquid Phase Deposition) oxide is selectively deposited on the pad nitride layer by a liquid phase deposition process, except on the pre-formed photoresist film. After removing the photoresist layer nitride spacers leaning against the LPD oxide layer are formed by lithography and etching. The width of the nitride spacers controls the channel length of the MOS device. After forming a gate structure laterally sandwiched by the nitride spacers on the exposed substrate, a two-stage salicide process, which can form shallow junctions and self-aligned contacts on the source and the drain, is performed to complete the MOS device.

Abstract: A method is provided for forming planar, self-aligned spaced-apart wells without a high temperature oxidation step to form an ion barrier. The method comprises preparing a substrate with a silicon dioxide-polysilicon-silicon dioxide barrier layer that can be etched to expose different sublayers of the barrier at selected junctures in the production process. A single masking step defines the location of a first set of wells on the prepared substrate. The outer silicon dioxide layer is etched to expose the polysilicon layer at the selected locations, and the substrate is implanted to form the first set of wells. Following ion implantation, the substrate photo-resist is removed, and the substrate is exposed to a germanium-silicon mixture under conditions selected to preferentially deposit a germanium-silicon alloy barrier layer on the exposed polysilicon layer.

Abstract: An improved reverse self-aligned FET having subquarter-micrometer channel lengths, shallow junction depths, and silicide source/drain contacts was achieved. The method for fabricating the FET includes forming a titanium layer, an N.sup.+ doped first polysilicon layer, and a silicon nitride layer over the device areas. A photoresist mask having first openings with minimal feature size is formed over the device areas where gate electrodes are desired. Non-volatile polymer sidewall spacers are formed on the side-walls of the first openings to extend the resolution limit of the photoresist. The sidewalls and photoresist are used as a mask to etch the silicon nitride layer, the first polysilicon layer, and the titanium layer to the substrate to form second openings (FET channel openings) where the gate electrodes are to be formed. A gate oxide is grown on the substrate in the channel openings, and a threshold-voltage implant and an anti-punchthrough implant are carried out in the channel openings, and then an N.

Abstract: A process and method for producing strained and defect free semiconductor layers. In a preferred embodiment, silicon on insulator may be used as a substrate for the growth of fully relaxed SiGe buffer layers. A new strain relief mechanism operates, whereby the SiGe layer relaxes without the generation of threading dislocations within the SiGe layer. This is achieved by depositing SiGe on an SOI substrate with a superficial silicon thickness. Initially the strain in the SiGe layer becomes equalized with the thin Si layer by creating tensile strain in the Si layer. Then the strain created in the thin Si layer is relaxed by plastic deformation during an anneal. Since dislocations are formed, and glide in the thin Si layer, threading dislocations are not introduced into the upper SiGe material. A strained silicon layer for heterostructures may then be formed on the SiGe material.

Abstract: A technique for forming a high-performance sub-half micron MOS transistor is disclosed which has improved short channel characteristics without degradation of device performance. The transistor comprises a semiconductor substrate, a gate electrode, graded source and drain impurity regions, a first set of gate sidewall spacers, and a second set of gate sidewall spacers. The graded source and drain impurity regions comprise a relatively linear continuum of doped regions, ranging from lightly doped (LDD) regions, to moderately doped (MDD) regions, to heavily doped regions. Additionally, the transistor may include a punch through barrier region located within the substrate under the gate electrode. With these features, the transistor of the present invention allows for more precise control of conduction channel length without degradation of either (1) body factor and current drive, and/or (2) junction leakage, and without compromising hot carrier immunity.

Abstract: A metal oxide semiconductor field effect transistor includes source and drain regions formed between a gate. The gate comprises a first conductive layer and a second conductive layer formed on the first conductive layer, and the second conductive layer has curved sidewalls with an insulating layer formed adjacent to the sidewalls. The method of making such a transistor improves the fabrication process, since the deposition thickness is controlled rather than the amount of etching. The transistor has a shortened channel width with reduced overlap capacitance, and the LDD doping compensation phenomenon is removed.

Abstract: A semiconductor fabrication method is provided for forming transistors upon a semiconductor substrate wherein the semiconductor substrate has first, second and third substrate regions. A single mask layer is formed over the semiconductor substrate. The single mask layer has a first mask portion covering the first substrate region, a second mask portion exposing the second substrate region, and a third mask portion partially covering the third substrate region. A first type impurity dopant is differentially introduced into the first, second and third substrate regions according to the single mask layer. First, second and third transistors are formed in the first, second and third substrate regions, respectively. The first and second transistors have differing conductivity types and the first and third transistors have the same conductivity type. The first and third transistors also have differing threshold voltages according to the differential introducing of the dopant.

Abstract: A method of manufacturing a semiconductor device is disclosed. After an insulating film having an opening is formed on a first thin tungsten film, an impurity is introduced into the substrate through the opening to form a punch-through stopper between a source and a drain. Then, on the first tungsten film inside the opening, a second tungsten film is selectively deposited to form a gate electrode. With this method, it is possible to easily fabricate high-speed MOSFETs whose channel length is less than half a micron.

Abstract: A memory cell, and process for making it, having a long channel and narrow buried bit line is disclosed. The memory cell is formed in a substrate having a first dopant type. A trench is defined in the substrate. Source/drain regions of a second dopant type are formed on the surface of the substrate to each side of the trench. A gate oxide layer is formed over the substrate and a polysilicon wordline deposited over the gate oxide layer. A channel is defined along the walls of the trench. Ions are implanted in the bottom of the trench defining the channel for a cell that is selected to be in the off state. The long channel and narrow bit line of these memory cells overcome the problem of high bit line resistance and low junction breakdown voltage found in conventional memory cells.

Abstract: Low threshold voltage MOS devices having buried electrodes are disclosed herein. Such devices have source and drain regions which include tip regions and plug regions. The buried electrodes have bottom boundaries located above the bottoms of the plug regions. The buried electrode has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. The exact dopant concentrations and locations of the buried electrodes should be provided such that punch through is avoided in MOS devices.

Abstract: A method for fabricating a metal oxide semiconductor field effect transistor, capable of achieving a reduction in topology by forming a trench on a silicon substrate by use of a temporary field oxide film and forming a gate electrode in the trench and capable of eliminating occurrence of a spiking phenomenon due to a metal wiring being in direct contact with the silicon substrate by forming a silicide film on a source and a drain, and capable of obtaining an increased contact margin of the metal wiring by overlapping the silicide film with a field oxide film formed on the silicon substrate.