Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

Abstract: An integrated circuit includes a Laterally Diffused MOSFET (LD-MOSFET) located over a semiconductor substrate. The LD-MOSFET transistor includes a dielectric filled trench at a surface of the semiconductor substrate, and a doped region of the semiconductor substrate adjacent the dielectric-filled trench. The doped region and the dielectric-filled trench share an interface that has a terminus at the surface of the semiconductor substrate. An oxide layer is located over the semiconductor substrate, including along a surface of the doped region and along a surface of the dielectric-filled trench. The oxide layer has a first thickness over the dielectric-filled trench and a second greater thickness over the doped region.

Abstract: A display driver semiconductor device includes a high voltage well region formed on a substrate, a first semiconductor device, a second semiconductor device, and a third semiconductor device. The first semiconductor device is formed on the high voltage well region and includes a first gate insulating layer formed using a deposition process. The second semiconductor device is formed adjacent to the first semiconductor device and includes a second gate insulating layer formed using a thermal process. The third semiconductor device is formed adjacent to the second semiconductor device and includes a third gate insulating layer.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor portion, a gate electrode, a source electrode, a first structure body, and a first insulating portion. The semiconductor portion includes SiC and includes first to third semiconductor regions. The first semiconductor region includes first to third partial regions. The second partial region is provided between the third partial region and the first partial region. The third semiconductor region is provided between the second partial region and the second semiconductor region. The source electrode is electrically connected to the second semiconductor region. The first insulating portion includes a first insulating region and a second insulating region. The first insulating region is provided between the first partial region and the gate electrode. The second insulating region is provided between the second semiconductor region and the first structure body. The first structure body includes at least one of polysilicon or TiN.

Abstract: A semiconductor device, including an insulator formed on a top surface of a semiconductor substrate, a semiconductor layer, containing a first region of a first conductivity type, formed on the insulator layer, wherein the first region is a P+ region or an N+ region, a second region of a second conductivity type in direct contact with the first region and forming a P-N junction with the first region, wherein the P-N junction comprises a first portion parallel to the top surface of the semiconductor substrate, and the second region is the semiconductor substrate and partially covered by the semiconductor layer, a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region.

Abstract: An exemplary method of making a semiconductor device includes providing a semiconductor layer of a first conductivity type, providing a first hard mask on a surface of the semiconductor layer, patterning the first hard mask to obtain a patterned first hard mask to obtain an exposed surface of the semiconductor layer, forming a body region in the semiconductor layer by using the patterned first hard mask as mask, the body region being of a second conductivity type different from the first conductivity type, providing a second hard mask on the patterned first hard mask and the exposed surface of the semiconductor layer, patterning the second hard mask to obtain a patterned second hard mask, and forming a contact region and a sinker region by using the patterned first hard mask and the patterned second hard mask as mask.

Abstract: A method of fabricating a semiconductor device is provided. In the method, a gate structure is formed on a semiconductor substrate. A photolithography process is performed with a mask having two transparent regions to form a photoresist layer having two openings in the semiconductor substrate. A first photoresist layer of the photoresist layer between the two openings is aligned to the gate structure and formed on the gate structure. The width of the first photoresist layer is shorter than the width of the gate structure such that a first side portion and a second side portion of the gate structure are exposed from both sides of the first photoresist layer, respectively. Next, an ion implantation process is performed to form lightly doped drain regions in the semiconductor substrate which are on two opposite sides of the gate structure of the photoresist layer.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source/drain region, a source/drain contact structure, a first dielectric layer, a first spacer, and a first connection structure. The gate structure is disposed on the semiconductor substrate. The source/drain region is disposed in the semiconductor substrate and disposed at a side of the gate structure. The source/drain contact structure is disposed on the source/drain region. The first dielectric layer is disposed on the source/drain contact structure and the gate structure. The first spacer is disposed in a first contact hole penetrating the first dielectric layer on the source/drain contact structure. The first connection structure is disposed in the first contact hole. The first connection structure is surrounded by the first spacer in the first contact hole, and the first connection structure is connected with the source/drain contact structure.

Abstract: A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. The gate is disposed over the fin structure and directly on the extension part. The present invention also provides a planar field effect transistor including a substrate and a gate. The substrate includes an active area, where the active area includes a frame area and a penetrating area penetrating through the frame area. The gate is disposed over the active area, where the gate is directly disposed on the penetrating area, and the frame area at least at a side of the gate constitutes a source/drain surrounding an isolation island.

Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.

Abstract: Integrated circuits with improved contact structures and methods for fabricating integrated circuits with improved contact structures are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a device in and/or on a semiconductor substrate. Further, the method includes forming a contact structure in electrical contact with the device. The contact structure includes silicate barrier portions overlying the device, a barrier metal overlying the device and positioned between the silicate barrier portions, and a fill metal overlying the barrier metal and positioned between the silicate barrier portions.

Abstract: A transistor includes a gate dielectric over a semiconductor having a first conductivity type, a control gate over the gate dielectric, source and drain regions having a second conductivity type in the semiconductor having the first conductivity type, and strips having the second conductivity type within the semiconductor having the first conductivity type and interposed between the control gate and at least one of the source and drain regions.

Abstract: A semiconductor device includes a drift region in a first region of a semiconductor body. The drift region includes dopants of a first conductivity type. A dopant retarding region is formed at least adjacent an edge of the drift region. Dopants of a second conductivity type are implanted into the semiconductor body. The semiconductor body is annealed to form a body region so that dopants of the second conductivity type are driven into the semiconductor body at a first diffusion rate. The dopant retarding region prevents the dopants from diffusing into the drift region at the first diffusion rate.

Abstract: A vertical transistor structure includes a substrate with a protruding structure, an offset layer covering a top surface of the protruding structure, a conductive layer disposed on the offset layer, and an interlayer disposed between the offset layer and the conductive layer to serve as a contact node.

Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a source and a drain in the substrate, a gate electrode disposed over the substrate between the source and drain, and a gate dielectric layer disposed between the substrate and the gate electrode. At least a portion of the gate dielectric layer is extended beyond the gate electrode toward at least one of the source or the drain.

Abstract: Various embodiments provide transistors and methods for forming the same. In an exemplary method, a substrate can be provided. A gate structure can be formed on the substrate. A stress layer can be formed in the substrate on both sides of the gate structure. Barrier ions can be doped in the stress layer to form a barrier layer in the stress layer. The barrier layer can have a preset distance from a surface of the stress layer. An electrical contact layer can be formed using a portion of the stress layer on the barrier layer by a salicide process. The electrical contact layer can contain a first metal element. The first metal element can have a resistivity lower than a resistivity of a silicidation metal. The barrier layer can prevent atoms of the first metal element from diffusing to a bottom of the stress layer.

Abstract: A stimulated phonon emission device of an embodiment is provided with a first electroconductive type of semiconductor substrate of an indirect transition type semiconductor crystal, a second electroconductive type of well region provided in the semiconductor substrate, an element isolation region deeper than the well region, an element region surrounded by the element isolation region, and a field-effect transistor having a plurality of gate electrodes which are formed in the well region in the element region, are parallel to each other, and are arranged at a constant pitch and first electroconductive type of source region and drain region provided in the element regions on the both sides of the gate electrode.

Abstract: A semiconductor device includes a drift region in a first region of a semiconductor body. The drift region includes dopants of a first conductivity type. A dopant retarding region is formed at least adjacent an edge of the drift region. Dopants of a second conductivity type are implanted into the semiconductor body. The semiconductor body is annealed to form a body region so that dopants of the second conductivity type are driven into the semiconductor body at a first diffusion rate. The dopant retarding region prevents the dopants from diffusing into the drift region at the first diffusion rate.

Abstract: A MOS transistor for power applications is formed in a substrate of semiconductor material by a method integrated in a process for manufacturing integrated circuits which uses an STI technique for forming insulating regions. The method includes the phases of forming an insulating element on a top surface of the substrate and forming a control electrode on a free surface of the insulating element. The insulating element insulates the control electrode from the substrate. The insulating element includes a first portion and a second portion. The extension of the first portion along a first direction perpendicular to the top surface is lower than the extension of the second portion along such first direction. The phase of forming the insulating element includes generating the second portion by locally oxidizing the top surface.

Abstract: Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel.

Abstract: A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins.

Abstract: A method includes forming a metal-oxide-semiconductor field-effect transistor (MOSFET). The Method includes performing an implantation to form a pre-amorphization implantation (PAI) region adjacent to a gate electrode of the MOSFET, forming a strained capping layer over the PAI region, and performing an annealing on the strained capping layer and the PAI region to form a dislocation plane. The dislocation plane is formed as a result of the annealing, with a tilt angle of the dislocation plane being smaller than about 65 degrees.

Abstract: According to a process for manufacturing an integrated power device, projections and depressions are formed in a semiconductor body that extend in a first direction and are arranged alternated in succession in a second direction, transversely to the first direction. Further provided are a first conduction region and a second conduction region. The first conduction region and the second conduction region define a current flow direction parallel to the first direction, along the projections and the depressions. To form the projections and the depressions, portions of the semiconductor body that extend in the first direction and correspond to the depressions, are selectively oxidized.

Abstract: A manufacturing method for manufacturing a lateral semiconductor device having an SOI (Silicon on Insulator) substrate, the lateral semiconductor device comprising a semiconductor layer that includes a buried oxide layer and a drift region, the manufacturing method comprising an etching process of etching, by a predetermined depth, a LOCOS oxide that projects from a surface of the semiconductor layer by a predetermined thickness and is embedded in the semiconductor layer by a predetermined thickness, and a trench forming process of simultaneously forming a first trench extending from the drift region toward the buried oxide layer, and a second trench extending from a portion obtained by the etching in the etching process toward the buried oxide layer, at a same etching rate, and stopping forming the first trench and the second trench at a time when the second trench reaches the buried oxide layer.

Abstract: Semiconductor devices and methods for making such devices are described. The semiconductor devices are made by providing a semiconductor substrate with an active region, providing a bulk oxide layer in a non-active portion of the substrate, the bulk oxide layer having a first thickness in a protected area of the device, providing a plate oxide layer over the bulk oxide layer and over the substrate in the active region, forming a gate structure on the active region of the substrate, and forming a self-aligned silicide layer on a portion of the substrate and the gate structure, wherein the final thickness of the bulk oxide layer in the protected area after these processes remains substantially the same as the first thickness. The thickness of the bulk oxide layer can be increased without any additional processing steps or any additional processing cost. Other embodiments are described.

Abstract: A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The memory device is pre-cleaned to prepare a surface of the memory device for oxide formation thereon, where cleaning the memory device removes portions of the barrier oxide layer on opposite sides of the trench. The nitride layer is trimmed on opposite sides of the trench. A liner oxide layer is formed in the trench.

Abstract: A power field effect transistor (FET) is disclosed which is fabricated in as few as six photolithographic steps and which is capable of switching current with a high voltage drain potential (e.g., up to about 50 volts). In a described n-channel metal oxide semiconductor (NMOS) embodiment, a drain node includes an n-well region with a shallow junction gradient, such that the depletion region between the n-well and the substrate is wider than 1 micron. Extra photolithographic steps are avoided using blanket ion implantation for threshold adjust and lightly doped drain (LDD) implants. A modified embodiment provides an extension of the LDD region partially under the gate for a longer operating life.

Abstract: Oxidation methods and resulting structures including providing an oxide layer on a substrate and then reoxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.

Abstract: A semiconductor device and manufacturing method are disclosed which provide increased ESD resistance. By disposing a slit mask when forming a second p-type well layer, impurity concentration of the second p-type well layer is partially reduced. By forming a second n-type offset layer in the second p-type well layer having decreased impurity concentration, it is possible to increase thickness of the second n-type offset layer in this place compared with that heretofore known. By increasing thickness of the second n-type offset layer, a depletion layer does not reach an n-type drain layer at a low voltage when reverse bias is applied to the drain. It thus is possible to prevent thermal destruction caused by localized electrical field concentration. As a result, it is possible to increase ESD resistance. As it is sufficient to replace a photoresist mask, there is no increase in the number of processes.

Abstract: A process of integrated circuit manufacturing includes providing (32, 33) a spacer on a gate stack to provide a horizontal offset over the channel region for otherwise-direct application (34) of a PLDD implant dose in semiconductor, additionally depositing (35) a seal substance to provide a screen thickness vertically while thereby augmenting the spacer on the gate stack to provide an increased offset horizontally from the gate stack and form a horizontal screen free of etch, and subsequently providing (36) an NLDD implant dose for NLDD formation. Various integrated circuit structures, devices, and other processes of manufacture, and processes of testing are also disclosed.

Abstract: Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel.

Abstract: The present invention relates to a method of introducing strain into a channel and a device manufactured by using the method, the method comprising: providing a semiconductor substrate; forming a channel in the semiconductor substrate; forming a first gate dielectric layer on the channel; forming a polysilicon gate layer on the first gate dielectric layer; doping or implanting a first element into the polysilicon gate layer; removing a part of the first gate dielectric layer and polysilicon gate layer to thereby form a first gate structure; forming a source/drain extension region in the channel; forming spacers on both sides of the first gate structure; forming a source/drain in the channel; and performing annealing such that lattice change occurs in the polysilicon that is doped or implanted with the first element in the high-temperature crystallization process, thereby producing a first strain in the polysilicon gate layer, and introducing the first strain through the gate dielectric layer to the channel.

Abstract: A method of forming a transistor device includes forming a dummy gate stack structure over an SOI starting substrate, comprising a bulk layer, a global BOX layer over the bulk layer, and an SOI layer over the global BOX layer. Self-aligned trenches are formed completely through portions of the SOI layer and the global BOX layer at source and drain regions. Silicon is epitaxially regrown in the source and drain regions, with a local BOX layer re-established in the epitaxially regrown silicon, adjacent to the global BOX layer. A top surface of the local BOX layer is below a top surface of the global BOX layer. Embedded source and drain stressors are formed in the source and drain regions, adjacent a channel region. Silicide contacts are formed on the source and drain regions. The dummy gate stack structure is removed, and a final gate stack structure is formed.

Abstract: A semiconductor device production method includes: forming a semiconductor region including a first region, a second region connecting with the first region and having a width smaller than that of the first region, and a third region connecting with the second region and having a width smaller than that of the second region; forming a gate electrode including a first part crossing the third region and a second part extending from the first part across the first region; forming a side wall insulation film on the gate electrode to cover part of the second region while exposing the remaining part of the second region; implanting a second conductivity type impurity into the first region and the remaining part of the second region; performing heat treatment; removing part of the side wall insulation film, and forming a silicide layer on the first region and the remaining part of the second region.

Abstract: A method for forming strained epitaxial carbon-doped silicon (Si) films, for example as raised source and drain regions for electronic devices. The method includes providing a structure having an epitaxial Si surface and a patterned film, non-selectively depositing a carbon-doped Si film onto the structure, the carbon-doped Si film containing an epitaxial carbon-doped Si film deposited onto the epitaxial Si surface and a non-epitaxial carbon-doped Si film deposited onto the patterned film, and non-selectively depositing a Si film on the carbon-doped Si film, the Si film containing an epitaxial Si film deposited onto the epitaxial carbon-doped Si film and a non-epitaxial Si film deposited onto the non-epitaxial carbon-doped Si film. The method further includes dry etching away the non-epitaxial Si film, the non-epitaxial carbon-doped Si film, and less than the entire epitaxial Si film to form a strained epitaxial carbon-doped Si film on the epitaxial Si surface.

Abstract: A method of manufacturing a semiconductor device comprises forming a first insulator in the first area of a substrate and a second insulator formed in a second area of the substrate; forming an etching preventing film extending over the first device region surrounded by the first area and the second device region surrounded by the second area removing the etching preventing film from the first device region and first area forming a first gate insulating film over the first device region while the second device region and the second area are covered by the etching preventing film; removing the etching preventing film over the second device region and the second area forming a second gate insulating film over the second device region; and forming a first gate electrode on the first gate insulating film and forming a second gate electrode on the second gate insulating film.

Abstract: The present invention provides a method for forming a semiconductor substrate isolation, comprising: providing a semiconductor substrate; forming a first oxide layer and a nitride layer sequentially on the semiconductor substrate; forming openings in the nitride layer and in the first oxide layer to expose parts of the semiconductor substrate; implanting oxygen ions into the semiconductor substrate from the openings; performing annealing to form a second oxide layer on at least top portions of the exposed parts of the semiconductor substrate; and removing the nitride layer and the first oxide layer. Compared to the conventional STI process, said method enables a more simply and easy process flow and is applicable to common semiconductor substrates and SOI substrates.

Abstract: This semiconductor device includes a first device and a second device provided on a semiconductor substrate and having different breakdown voltages. More specifically, the semiconductor device includes a semiconductor substrate, a first region defined on the semiconductor substrate and having a first device formation region isolated by a device isolation portion formed by filling an insulator in a trench formed in the semiconductor substrate, a first device provided in the first device formation region, a second region defined on the semiconductor substrate separately from the first region and having a second device formation region, and a second device provided in the second device formation region and having a higher breakdown voltage than the first device, the second device having a drift drain structure in which a LOCOS oxide film thicker than a gate insulation film thereof is disposed at an edge of a gate electrode thereof.

Abstract: A method is provided to fabricate a semiconductor device, where the method includes providing a substrate comprised of crystalline silicon; implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde well (SSRW) implant doping profile; annealing implant damage using a substantially diffusionless thermal annealing to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon and, prior to performing a shallow trench isolation process, depositing a silicon cap layer over the surface of the substrate. The substrate may be a bulk Si substrate or a Si-on-insulator substrate. The method accommodates the use of an oxynitride gate stack structure or a high dielectric constant oxide/metal (high-K/metal) gate stack structure.

Abstract: Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching.

Abstract: The invention provides a method for activating impurity element added to a semiconductor and performing gettering process in shirt time, and a thermal treatment equipment enabling to perform such the heat-treating.

Abstract: A method is provided to fabricate a semiconductor device, where the method includes providing a substrate comprised of crystalline silicon; implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde well (SSRW) implant doping profile; annealing implant damage using a substantially diffusionless thermal annealing to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon and, prior to performing a shallow trench isolation process, depositing a silicon cap layer over the surface of the substrate. The substrate may be a bulk Si substrate or a Si-on-insulator substrate. The method accommodates the use of an oxynitride gate stack structure or a high dielectric constant oxide/metal (high-K/metal) gate stack structure.

Abstract: An optocoupler device facilitates on-chip galvanic isolation. In accordance with various example embodiments, an optocoupler circuit includes a silicon-on-insulator substrate having a silicon layer on a buried insulator layer, a silicon-based light-emitting diode (LED) having a silicon p-n junction in the silicon layer, and a silicon-based photodetector in the silicon layer. The LED and photodetector are respectively connected to galvanically isolated circuits in the silicon layer. A local oxidation of silicon (LOCOS) isolation material and the buried insulator layer galvanically isolate the first circuit from the second circuit to prevent charge carriers from moving between the first and second circuits. The LED and photodetector communicate optically to pass signals between the galvanically isolated circuits.

Abstract: A semiconductor device includes an isolation layer formed on and/or over a semiconductor substrate to define an isolation layer, a drift area formed in an active area separated by the isolation layer, a pad nitride layer pattern formed in a form of a plate on the drift area, and a gate electrode having step difference between lateral sides thereof due to the pad nitride layer pattern.

Abstract: A semiconductor device includes a substrate with a recess pattern, a gate electrode filling the recess pattern, a threshold voltage adjusting layer formed in the substrate under the recess pattern, a source/drain region formed in the substrate on both sides of the gate electrode and a gate insulation layer, with the recess pattern being disposed between the gate electrode and the substrate, wherein the thickness of the gate insulation layer formed in a region adjacent to the source/drain region is greater than the thickness of the gate insulation layer formed in a region adjacent to the threshold voltage adjusting layer.

Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

Abstract: A metal-oxide-semiconductor field effect transistor (MOSFET) has a body layer that follows the contour of exposed surfaces of a semiconductor substrate and contains a bottom surface of a shallow trench and adjoined sidewalls. A bottom electrode layer vertically abuts the body layer and provides an electrical bias to the body layer. A top electrode and source and drain regions are formed on the body layer. The thickness of the body layer is selected to allow full depletion of the body layer by the top electrode and a bottom electrode layer. The portion of the body layer underneath the shallow trench extends the length of a channel to enable a high voltage operation. Further, the MOSFET provides a double gate configuration and a tight control of the channel to enable a complete pinch-off of the channel and a low off-current in a compact volume.

Abstract: A method for creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness includes: measuring a thickness of a semiconductor-on-insulator (SOI) layer at a plurality of locations; determining a removal thickness at each of the plurality of locations; and implanting ions at the plurality of locations. The implanting is dynamically based on the removal thickness at each of the plurality of locations. The method further includes oxidizing the SOI layer to form an oxide layer, and removing the oxide layer.

Abstract: The present invention discloses a method of manufacturing MOS device having a lightly doped drain (LDD) structure. The method includes: providing a first conductive type substrate; forming an isolation region in the substrate to define a device area; forming a gate structure in the device area, the gate structure having a dielectric layer, a stack layer, and a spacer layer on the sidewalls of the stack layer; implanting second conductive type impurities into the substrate with a tilt angle to form an LDD structure, wherein at least some of the impurities are implanted into the substrate through the spacer to form part of the LDD structure below the spacer layer; and implanting second conductive type impurities into the substrate to form source and drain.