Abstract: A method for forming an improved etching hardmask oxide layer in a polysilicon etching process including providing a planarized semiconductor wafer process surface including adjacent first exposed polysilicon portions and exposed oxide portions; selectively etching through a thickness portion of the exposed oxide portions; thermally growing an oxide hardmask layer over the exposed polysilicon portions to form oxide hardmask portions; exposing second exposed polysilicon portions adjacent at least one oxide hardmask portion; and, etching through a thickness portion of the second exposed polysilicon portions.

Abstract: The present invention discloses semiconductor device which comprises a metal gate electrode surrounded by polysilicon layers and a gate insulating film whose edges are thicker than the center portion formed according to a reoxidation process using a thermal process before the formation of an ion implantation region in a process for forming the metal gate electrode using a replacement process and method for manufacturing the same.

Abstract: A method of forming gate electrode layer portions having differing widths comprising the following steps. A structure having a gate electrode layer and a hard mask layer thereover and including two or more active areas is provided. The hard mask layer is patterned to form two or more respective hard mask layer portions within the two or more active areas. One or more of the two or more respective hard mask layer portions is/are selectively trimmed to reduce its/their width to a second width leaving at least one the respective hard mask layer portions untrimmed. The gate electrode layer is then patterned.

Abstract: A method for forming within a silicon semiconductor substrate employed within a microelectronics fabrication a silicon oxide dielectric layer. There is provided a silicon semiconductor substrate. There is formed upon the silicon semiconductor substrate a blanket silicon oxide pad oxide layer. There is then formed upon the pad oxide layer a patterned silicon nitride masking layer delineating active regions of the silicon semiconductor substrate from isolation regions. There is formed upon the isolation regions by thermal oxidation of the semiconductor silicon substrate in a dry oxidizing environment at an elevated temperature a thick silicon oxide dielectric layer employed as a field oxide (FOX) dielectric isolation layer formed through the silicon nitride patterned masking layer.

Abstract: Embodiments of the present invention relate to a method for preventing gate oxide thinning in a recess LOCOS process. The plurality of trenches are separated by a patterned pad oxide and a patterned silicon nitride layer The patterned silicon nitride layer and the patterned pad oxide layer are removed to expose a surface of the substrate as an active area of the semiconductor device. An ion drive-in to the active area on the substrate is performed by directing a flow of oxygen and nitrogen toward the substrate at a predetermined temperature and with a sufficient amount of oxygen to at least substantially prevent silicon nitride from forming on the field oxide regions. The method further comprises forming a sacrificial oxide layer on the active area, removing the sacrificial oxide layer to expose the active area, and forming a gate oxide layer on the active area.

Abstract: An electronic circuit comprises a bipolar transistor that includes a conductive back electrode, an insulator layer over the conductive back electrode and a semiconductor layer of either an n-type or p-type material over the insulator layer. The semiconductor layer includes a doped region, used as the collector and a heavily doped region, bordering the doped region, used as a reachthrough between the insulator layer and the collector contact electrode. A majority-carrier accumulation layer is induced adjacent to the insulator in the doped region of the collector by the application of a bias voltage to the back electrode.

Abstract: Transistors are manufactured by growing germanium source and drain regions, implanting dopant impurities into the germanium, and subsequently annealing the source and drain regions so that the dopant impurities diffuse through the germanium. The process is simpler than a process wherein germanium is insitu doped with p-type or n-type impurities. The dopant impurities diffuse easily through the germanium but not easily through underlying silicon, so that an interface between the germanium and silicon acts as a diffusion barrier and ensures positioning of the dopant atoms in the regions of the device where they improve transistor performance.

Abstract: Within a method for forming an isolation region within a semiconductor substrate, there is, prior to forming the isolation region within an isolation trench formed adjoining an active region of a semiconductor substrate, implanted a dopant into a corner of the active region. The corner of the active region is uncovered by laterally etching an isolation trench mask to form a laterally etched isolation trench mask which serves as an ion implantation mask layer when implanting the dopant into the corner of the active region. The method provides for enhanced performance, and minimal affect of a semiconductor device formed within the active region of the semiconductor substrate.

Abstract: A method of forming a semiconductor device includes forming a body region of a semiconductor substrate and forming a drift region adjacent at least a portion of the body region. A dopant is used to form the drift region. The dopant may comprise phosphorous. The method also includes forming a field oxide structure adjacent a portion of the drift region and a portion of a drain region. The field oxide structure is located between a gate electrode region and the drain region and is spaced apart from the gate electrode region. Atoms of the dopant accumulate adjacent a portion of the field oxide structure, forming an intermediate-doped region adjacent a portion of the field oxide structure. The method includes forming a gate oxide adjacent a portion of the body region and forming a gate electrode adjacent a portion of the gate oxide.

Abstract: A method of forming device isolation structures in an embedded semiconductor device is disclosed. The method of forming device isolation structures comprises the steps of: providing a substrate having a first area in which ions are implanted; forming a first device isolation structure through partial oxidation in the first area; forming a first type well with deep junction by diffusing the ions in the first area; forming a second device isolation structure with a trench in a second area of the substrate; forming a first type well with shallow junction in peripheral regions of the second device isolation structure and a region between the first device isolation structure and the second device isolation structure; forming a second type well with shallow junction in peripheral regions of the first device isolation structure and a region of the second device isolation structure; and defining first and second type active regions on the substrate.

Abstract: Oxidation methods and resulting structures including providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.

Abstract: An oxynitride material is used to form shallow trench isolation regions in an integrated circuit structure. The oxynitride may be used for both the trench liner and trench fill material. The oxynitride liner is formed by nitriding an initially formed oxide trench liner. The oxynitride trench fill material is formed by directly depositing a high density plasma (HDP) oxide mixture of SiH4 and O2 and adding a controlled amount of NH3 to the plasma mixture. The resultant oxynitride structure is much more resistant to trench fill erosion by wet etch, for example, yet results in minimal stress to the surrounding silicon. To further reduce stress, the nitrogen concentration may be varied by varying the proportion of O2 to NH3 in the plasma mixture so that the nitrogen concentration is maximum at the top of the fill material.

Abstract: Disclosed is a method of forming an isolation film in semiconductor devices using a shallow trench. Trenches are formed in silicon substrates of a memory cell region and a peripheral circuit region. The inert ion is then injected into the surface of the trench in the peripheral circuit region, thus forming an amorphous layer. Thereafter, an oxidization process is implemented so that a thick oxide film is grown due to excessive oxidization at the amorphous layer, thus making thicker the trench in the peripheral circuit region than the trench in the memory cell region by a thickness of the oxide film.

Abstract: Disclosed is a method for fabricating a semiconductor device wherein boron-halo ion implantation is performed only to a bit-line contact part while masking a storage node contact part. The method comprises the steps of: performing a first ion implantation into the semiconductor substrate to control the threshold voltage Vt; forming a gate electrode on the semiconductor substrate in which the first ion implantation has been performed; performing a second ion implantation with a tilt of desired degree, using the gate electrode as a mask in order to control the threshold voltage; and performing a third ion implantation to form an LDD region in the substrate region at both sides of the gate electrode. In this method, the first ion implantation is performed at a range of below 90% of the whole doping concentration required to control the threshold voltage, and the second ion implantation is performed with a degree of below 30° and in two directions or four directions vertical to the gate electrode.

Abstract: The present invention relates to a method for fabricating a metal-oxide semiconductor (MOS) transistor having a gate electrode with a stack structure of a polysilicon layer, a tungsten nitride barrier layer and a tungsten layer. According to the present invention, a depth from a lastly deposited nitride layer to a bottom surface of a trench is shallower, and thereby decreasing incidences of a void generation. Also, the present invention provides an advantage of an elaborate manipulation of well and channel dopings by performing ion-implantations with two different approaches. Furthermore, it is possible to enhance device characteristics by decreasing gate induced drain leakage (GIDL) currents and improving a capability of driving currents. This decrease of the GIDL currents and the improved driving current capability are obtained by forming the gate oxide layer with different thicknesses.

Abstract: A semiconductor device which includes a precision high-K dielectric and formed on a semiconductor substrate and a method of forming the same. The semiconductor device includes at least one dielectric layer having a dielectric constant greater than SiO2. The at least one dielectric layer is deposited by atomic layer deposition (ALD). The ALD deposited layer has precise uniformity, thickness and abrupt atomic interfaces.

Abstract: A static random access memory cell comprising a first inverter including a first p-channel pullup transistor, and a first n-channel pulldown transistor in series with the first p-channel pullup transistor; a second inverter including a second p-channel pullup transistor, and a second n-channel pulldown transistor in series with the second n-channel pullup transistor, the first inverter being cross-coupled with the second inverter, the first and second pullup transistors sharing a common active area; a first access transistor having an active terminal connected to the first inverter; a second access transistor having an active terminal connected to the second inverter; and an isolator isolating the first pullup transistor from the second pullup transistor.

Abstract: A temperature control method is provided which is capable of performing quick, accurate, and error-free soaking control over all wafer areas to be thermally treated at a target temperature without requiring any skilled operator and which can be automated by using a computer. In the temperature control method of controlling a heating apparatus having at least two heating zones in such a manner that temperatures detected at predetermined locations equal a target temperature therefor, temperatures are detected at predetermined locations the number of which is larger than the number of the heating zones, and the heating apparatus is controlled in such a manner that the target temperature falls between a maximum value and a minimum value of a plurality of detected temperatures.

Abstract: An electronic component includes a semiconductor substrate (110), an epitaxial semiconductor layer (120, 221, 222) over the semiconductor substrate, and a semiconductor region (130, 230) in the epitaxial semiconductor layer. The epitaxial semiconductor layer has an upper surface (123). A first portion (121) of the epitaxial semiconductor layer is located below the semiconductor region, and a second portion (122) of the epitaxial semiconductor layer is located above the semiconductor region. The semiconductor substrate and the first portion of the epitaxial semiconductor layer have a first conductivity type, and the semiconductor region has a second conductivity type. At least one electrically insulating trench (140, 240) extends from the upper surface of the epitaxial semiconductor layer into at least a portion of the semiconductor region. The semiconductor substrate has a doping concentration higher than a doping concentration of the first portion of the epitaxial semiconductor layer.

Abstract: The present invention provides a narrow/short high performance MOS device structure that includes a rectangular-shaped semiconductor substrate region having a first conductivity type. A region of dielectric material is formed at the center of the substrate region. Four substrate diffusion regions, each having a second conductivity type opposite the first conductivity type, are formed in the substrate diffusion region in a respective comer of the substrate region. The four diffusion regions are spaced-apart such that a substrate channel region is defined between each adjacent pair of substrate diffusion regions. A common conductive gate electrode is formed to have four fingers, each one of the fingers extending over a corresponding substrate channel region. The fingers of the common conductive gate electrode are spaced-apart from the underlying substrate channel regions by dielectric material formed therebetween.

Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

Abstract: When an element isolation film is formed by the LOCOS technique, as an underlying buffer layer of an oxidation resisting film, a pad oxidation film and pad poly-Si film are used. When an element is formed, they are used as a gate oxide film and a part of a gate electrode to relax a level difference between the gate electrode and the wiring on the element isolation film. A first poly-Si film (pad poly-Si film) is etched to leave its certain thickness to relax the level difference more greatly. In such a process, in manufacturing a semiconductor integrated circuit using the LOCOS technique, the number of manufacturing steps can be reduced and the level difference between the gate electrode on the gate insulating film and the wiring on the element isolation film can be relaxed.

Abstract: A method for manufacturing a semiconductor memory device includes forming an isolation layer adjacent a diffusion region over a substrate that also has a stacked gate region. A gate oxide layer is formed over the gate region; a first conductive layer over the isolation and gate oxide layers and the diffusion region; a nitride layer over the first conductive layer, the nitride layer having an opening at the isolation layer; and an oxide region in the first conductive layer using the nitride layer as a mask. After removing the nitride layer and the silicon oxide region, an interelectrode dielectric layer is formed over the first conductive layer, and a second conductive layer is formed over the interelectrode dielectric layer. Then, the interelectrode dielectric layer and the first conductive layer over the diffusion portion are removed and a diffusion layer is formed in the substrate of the diffusion portion.

Abstract: A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field defect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

Abstract: A process for high resolution patterning of noble metals, such as platinum, for forming various semiconductor devices, such as capacitors or wiring patterns, is disclosed. A layer of noble metal, which will form an upper electrode of a capacitor, is formed over a dielectric layer. A mask layer is then formed over the noble metal layer and patterned to leave a portion of the noble metal layer exposed. The portion of the exposed noble metal is subsequently converted to its silicide, the noble metal silicide is then etched and the dielectric layer is removed, leaving the noble metal layer patterned in an upper electrode of an IC capacitor.

Abstract: A Silicon On Insulator (SOI) structure and method of producing an SOI structure that can prevent a short circuit between a Local Inter-Connect (LIC) and a well in the SOI structure is disclosed. The SOI structure includes a BOX layer of insulation material formed on a silicon substrate; an SOI layer formed on the BOX layer; a well formed within a device isolation area of the SOI layer such that its lower surface is in contact with the BOX layer; a field oxide film formed on a surface side within the well; a gate line formed across an active area on the SOI layer and a portion on the field oxide film; an N+ type source/drain area formed within the active area along both sides of the gate line to contact its lower surface with the BOX layer; an insulation layer formed on such resultant structure; and an opening part that is formed within the insulation layer.

Abstract: A method of manufacturing a semiconductor memory element is disclosed. The method includes arranging a mask on the upper surface of a semiconductor substrate, using the mask to conduct exposure, forming first, second, and third element-isolation regions on the semiconductor substrate surface, and forming a gate electrode. A resist film is formed on the substrate. On the mask, auxiliary patterns are made at the each central portion of first, second, and third patterns. In the exposure with the mask, first, second, and third resist patterns is formed on the resist film. The resist patterns respectively correspond to the patterns on the mask. The gate electrode extending in the second direction is formed from the upper surface of the second element-isolation region to the upper surface of the third electrode element-isolation region through an area between the second and third element-isolation regions.

Abstract: On the sides of a gate electrode, layered-film sidewalls are formed which includes a first oxide film such as an NSG film or a TEOS film and a second oxide film such as a BPSG film or a PSG film. After the layered-film sidewalls are used as a mask for forming source and drain regions of a MIS transistor, the second oxide film of the sidewalls is selectively removed. At the removal, wet etching is performed with an aqueous solution containing hydrofluoric acid, and acetic acid or isopropyl alcohol. This makes etching selectivity between oxide films higher and removes only the upper second oxide film. As a result, in the formation of two types of oxide films which differ in their etching properties, the etching selectivity can be prevented from deteriorating.

Abstract: A fabrication method for a read-only memory with a silicon nitride floating gate is provided. A first oxide layer and a silicon nitride layer are sequentially formed on a substrate. The silicon nitride layer and the first oxide layer are then patterned to form an opening, exposing a portion of the substrate. An oxidation process is then conducted to form a second oxide layer on the silicon nitride layer and concurrently to form a field oxide layer on the exposed substrate. The second oxide layer, the silicon nitride layer and the first oxide layer are then patterned to form an oxide dielectric layer, a silicon nitride floating gate layer and a tunnel oxide layer.

Abstract: A method for fabricating an NROM is described. A stacked nitride layer is formed on a substrate and then patterned to expose a portion of the substrate. An implantation is performed to form a buried bit line in the exposed substrate, and then an oxide layer is formed on the buried bit line by using wet oxidation. Thereafter, a gate oxide layer is formed in the periphery circuit region by using dry oxidation. A patterned polycide layer is formed on the substrate covering the stacked nitride layer and then patterned into a word line of the NROM cell and a gate of a periphery device.

Abstract: A method for fabricating a flash memory device having a self-aligned source includes providing a semiconductor substrate having a source region separated from a drain region by a channel region. The method also includes forming an isolation structure in the semiconductor substrate that crosses the source, drain, and channel regions of the semiconductor substrate. The method also includes forming a continuous stack structure outwardly from the channel region of the semiconductor substrate and the isolation structure. The method includes depositing a bottom anti-reflective layer over the semiconductor substrate, the isolation structure and the stack structure to substantially uniformly planarize the semiconductor substrate and the isolation structure. The method further includes depositing a photoresist layer over select portions of the bottom anti-reflective layer and the continuous stack structure to form a self-aligned source pattern using a photo mask.

Abstract: A method for forming a gate structure begins by preparing a semiconductor substrate provided with an isolation region formed therein. A thin SiO2 layer is thermally grown on top of the semiconductor device by using a wet H2/O2 or a dry O2. And then, an aluminum oxide layer is formed on top of the semiconductor substrate with doping a dopant in situ. A conductive layer is formed on top of the Al2O3 layer. Finally, the conductive layer and the Al2O3 layer are patterned into the gate structure. The dopant is a material selected from a group consisting of Si, Zr, Hf, Nb or the like.

Abstract: In a method of manufacturing a semiconductor device, there are comprised the steps of forming an oxidation preventing layer on a surface of a semiconductor substrate, forming a first window in the oxidation preventing layer, placing the semiconductor substrate in a first atmosphere in which an oxygen gas and a first amount of a chlorine gas are supplied through and then heating the semiconductor substrate at a first temperature such that a first selective oxide film is to grown by thermally oxidizing the surface of the semiconductor substrate exposed from the first window, forming a second window by patterning the oxidation preventing layer, and placing the semiconductor substrate in a second atmosphere in which the oxygen gas and a second amount, which is larger than the first amount, of the chlorine gas are supplied through and then heating the semiconductor substrate at a second temperature such that a second selective oxide film is formed and that a thickness of the first selective oxide film formed below

Abstract: A method of forming a localized oxidation having reduced bird's beak encroachment in a semiconductor device by providing an opening in the silicon substrate that has sloped sidewalls with a taper between about 10° and about 75° as measured from the vertical axis of the recess opening and then growing field oxide within the tapered recess opening for forming the localized oxidation.

Abstract: The buried oxide region has a layer added which etches selectively with respect to oxide, allowing the contacts to a gate or to a back gate to be created without overetching into the buried oxide region.

Abstract: A method of fabricating a semiconductor device in which a LOCOS profile characteristic is applied to a normal shallow trench isolation (STI) structure thereby lowering compressive stress that is concentrated on the side of the STI and preventing a thinning phenomenon by which the oxide film is formed in a relatively thin thickness at the boundary of the STI and the gate oxide film for high voltage (HV) region. The STI of a CVD oxide material including an angular bird's beak extension structure is formed in a field region, a gate oxide film is formed in a relatively thick thickness in a HV region by using a nitride film as a mask, and a gate oxide film having a relatively thin thickness is formed in a low voltage (LV) region.

Abstract: A method of manufacturing an integrated circuit which reduces damage to the underlying base layer and the created oxide structures is disclosed herein. The method includes providing a hybrid stack disposed over an underlying layer, providing an IC structure pattern over the hybrid stack, selectively removing the top layer and a portion of the bottom layer according to the IC structure pattern, leaving a protective portion of the bottom layer according to the IC structure pattern, removing the protective portion of the bottom layer, building oxide structures in the underlying layer according to the IC structure pattern, and removing remaining portions of the hybrid stack.

Abstract: A split-gate flash memory cell having improved programming and erasing speed with a tilted trench source, and also a method of forming the same are provided. This is accomplished by forming two floating gates and their respective control gates sharing a common source region. A trench is formed in the source region and the walls are sloped to have a tilt. A source implant is performed at a tilt angle and the trench is lined with a gate oxide layer. Subsequently, a lateral diffusion of the source implant is performed followed by thermal cycling. The lateral enlargement of the diffused source is found to increase the coupling ratio of the split-gate flash memory cell substantially.

Abstract: A method of selectively oxidizing a composite film. According to the present invention a substrate of having a composite film comprising of lower silicon film, a barrier layer, and upper metal film on the barrier layer is placed into a reaction chamber. An inert gas is then fed into reaction chamber to create an inert ambient in the reaction chamber. The temperature of the substrate is then raised or ramped from first temperature to a second temperature in the inert ambient. After the temperature of the substrate is raised to the second temperature the substrate is exposed to an ambient which oxidizes the silicon but which does not oxidize the metal.

Abstract: Disclosed is a MOSFET fabrication method capable of forming an ultra shallow junction while ensuring stability in controlling threshold voltage. The disclosed method relies on the use of a sacrificial gate structure to form LDD regions and the addition of side wall spacers to form source/drain regions, followed by the deposition of an interlayer insulating film. The sacrificial gate structure is then removed to form a groove in the interlayer insulating film that exposes a portion of the silicon substrate. A sacrificial oxide is grown on the exposed silicon substrate and impurity ions are implanted through the oxide to adjust the threshold voltage. The sacrificial oxide is then removed and replaced by a high quality gate insulating film. A metal gate electrode is then formed in the groove above the gate insulating film, thereby forming a MOSFET device having a metal gate.

Abstract: Embodiments include a semiconductor device including a well structure such that well areas can be formed with a higher density of integration and a plurality of high-voltage endurable transistors can be driven independently of one another with different voltages, and a method of manufacturing the semiconductor device. The semiconductor device may include a triple well comprising a first well formed in a silicon substrate and having a first conductivity type (P-type), a second well formed in adjacent relation to the first well and having a second conductivity type (N-type), and a third well formed in the second well and having the first conductivity type (P-type). A high-voltage endurable MOSFET is provided in each of the wells. Each MOSFET has an offset area in the corresponding well around a gate insulating layer. The offset area is formed of a low-density impurity layer which is provided under an offset LOCOS layer on the silicon substrate.

Abstract: An ultra-thin gate oxide layer of hafnium oxide (HfO2) and a method of formation are disclosed. The ultra-thin gate oxide layer of hafnium oxide (HfO2) is formed by a two-step process. A thin hafnium (Hf) film is first formed by thermal evaporation at a low substrate temperature, after which the thin hafnium film is radically oxidized using a krypton/oxygen (Kr/O2) high-density plasma to form the ultra-thin gate oxide layer of hafnium oxide (HfO2). The ultra-thin gate oxide layer of hafnium oxide (HfO2) formed by the method of the present invention is thermally stable in contact with silicon and is resistive to impurity diffusion at the HfO2/silicon interface. The formation of the ultra-thin gate oxide layer of hafnium oxide (HfO2) eliminates the need for a diffusion barrier layer, allows thickness uniformity of the field oxide on the isolation regions and, more importantly, preserves the atomically smooth surface of the silicon substrate.

Abstract: A field oxide film is provided in the surface of a semiconductor substrate. An interlayer insulating film is provided on the semiconductor substrate so as to cover an active layer. A contact hole exposing the surface of the active layer is provided in the interlayer insulating film. A conductor fills the contact hole so as to be electrically connected to the surface of the active layer. The end portion of the field oxide film has a surface perpendicular with respect to the surface of the semiconductor substrate. As a result, a dynamic random access memory can be obtained which is improved so that leakage current is reduced, which in turn increases a hold time of information.

Abstract: A structure and a process for manufacturing semiconductor devices with improved ESD protection for high voltage applications is described. A thick field gate oxide N channel field effect transistor (FET) device with a tunable threshold voltage (Vt) is developed at the input/output to the internal active circuits for the purpose of providing ESD protection for applications in the 9 volt and higher range. The FET threshold voltage determines the ESD protection characteristics. A N-field implant is used to provide a dopant region under the thick oxide gate element which has the effect of modifying the threshold voltage (Vt) of this device enabling the device turn-on to be “tuned” to more closely match the application requirements of the internal semiconductor circuits. The gate electrical contact is completed by using either a metal gate electrode or polysilicon gate element.

Abstract: A method of forming a fully depleted semiconductor-on-insulator (SOI) field effect transistor (FET). The method includes forming a T-shaped gate electrode formed at least in part in a recess formed in a layer of semiconductor material and over a body region that is disposed between a source and a drain. The method includes spacing the gate electrode from the body by a gate dielectric made from a high-K material.

Abstract: An EPROM structure includes a NMOS transistor integrated with a capacitor. The terminal names of the NMOS transistor follow the conventional nomenclature: drain, source, body and gate. The gate of the NMOS transistor is connected directly and exclusively to one of the capacitor plates. In this configuration, the gate is now referred to as the “floating gate”. The remaining side of the capacitor is referred to as the “control gate”.

Abstract: There is described a method for manufacturing a semiconductor device, in which an isolation oxide film having a superior dimensional accuracy and an isolation oxide film of a high withstanding voltage are manufactured in simple processes. A semiconductor device including a plurality of isolation oxide films of different thickness is manufactured. A nitride film and a resist film are grown on a silicon substrate, and openings are formed in the resist film. Openings are formed in the nitride film while the resist film is used as a mask. Isolation oxide films are formed below the openings through thermal oxidation. An opening diameter of the large opening formed in the nitride film is set to a value of more than 0.6 &mgr;m, whereas an opening diameter of the smaller opening is set a predetermined value of less than 0.6 &mgr;m. More specifically, the removal value of the smaller opening is set to a value required for imparting a desired thickness to the isolation oxide film 42.

Abstract: The tradeoff between breakdown voltage and on-resistance for LDMOS devices has been improved by having two epitaxial N− regions instead of the single epitaxial N− region that is used by devices of the prior art. The resistivities and thicknesses of these two N− regions are chosen so that their mean resistivity is similar to that of the aforementioned single N− layer. A key feature is that the lower N− layer (i.e. the one closest to the P− substrate) has a resistivity that is greater than that of the upper N− layer. If these constraints are met, as described in greater detail in the specification, improvements in breakdown voltage of up to 60% can be achieved without having to increase the on resistance. A process for manufacturing the device is also described.

Abstract: A method of manufacturing a semiconductor device is provided which, even if device dimensions decrease, prevents degradation in the operating characteristics of semiconductor elements which are isolated from each other by an element isolation region in a trench isolation structure. Implantation of ions (15) in a polycrystalline silicon layer (3) from above through a silicon nitride film (2) produces an ion-implanted polycrystalline silicon layer (16). Since the ions (15) are an ionic species of element which acts to enhance oxidation, the implantation of the ions (15) changes the polycrystalline silicon layer (3) into the ion-implanted polycrystalline silicon layer (16) having a higher oxidation rate. In subsequent formation of a thermal oxide film (21) on the inner wall of a trench (5), exposed part of the ion-implanted polycrystalline silicon layer (16) is also oxidized, forming relatively wide polycrystalline silicon oxide areas (21a).

Abstract: A novel process for forming a robust, sub-100 Å oxide is disclosed. Native oxide growth is tightly controlled by flowing pure nitrogen during wafer push and nitrogen with a small amount of oxygen during temperature ramp and stabilization. First, a dry oxidation is performed in oxygen and 13% trichloroethane. Next, a wet oxidation in pyrogenic steam is performed to produce a total oxide thickness of approximately 80 Å. The oxide layer formed is ideally suited for use as a high integrity gate oxide below 100 Å. The invention is particularly useful in devices with advanced, recessed field isolation where sharp silicon edges are difficult to oxidize. For an oxide layer of more than 100 Å, a composite oxide stack is used which comprises 40-90 Å of pad oxide formed using the above novel process, and 60-200 Å of deposited oxide.