Having Elevated Source Or Drain (e.g., Epitaxially Formed Source Or Drain, Etc.) Patents (Class 438/300)
  • Patent number: 11362005
    Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having a first region, a second region, a gate structure on the first region and a dummy gate structure on the second region, and an isolation structure in the semiconductor under the dummy gate structure. The method also includes forming source/drain openings in the semiconductor substrate at two sides of the gate structure. A sidewall surface of the source/drain opening contains an apex angle extending into the semiconductor substrate under the gate structure; and the source/drain opening exposes a sidewall surface of the isolation structure. Further; the method includes forming an initial bulk layer in the source/drain opening; performing a reshaping process to the initial bulk layer to form a bulk layer having an a substantially flat reshaped surface; and forming a protective layer on the bulk layer.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: June 14, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Zhen Yu Liu
  • Patent number: 11309404
    Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: April 19, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Benjamin Colombeau, Tushar Mandrekar, Patricia M. Liu, Suketu Arun Parikh, Matthias Bauer, Dimitri R. Kioussis, Sanjay Natarajan, Abhishek Dube
  • Patent number: 11295055
    Abstract: A transmission gate structure includes two PMOS transistors in a first active area, two NMOS transistors in a second active area, a first metal zero segment overlying the first active area, a second metal zero segment offset from the first metal zero segment by a distance, a third metal zero segment offset from the second metal zero segment by the distance, a fourth metal zero segment offset from the third metal zero segment by the distance and overlying the second active area. A first conductive segment overlies a first portion of the first active area included in one or both PMOS transistors, and a second conductive segment overlies a second portion of the second active area included in one or both NMOS transistors. The active areas and metal zero segments are perpendicular to the conductive segments, and the PMOS and NMOS transistors are coupled together through the conductive segments.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Lun Chien, Pin-Dai Sue, Li-Chun Tien, Ting-Wei Chiang, Ting Yu Chen
  • Patent number: 11270905
    Abstract: Embodiments of the present disclosure generally relate to a substrate processing chamber, and components thereof, for forming semiconductor devices. The processing chamber comprises a substrate support, and an edge ring is disposed around the substrate support. The edge ring comprises a material selected from the group consisting of quartz, silicon, cross-linked polystyrene and divinylbenzene, polyether ether ketone, Al2O3, and AlN. The material of the edge ring is selected to modulate the properties of hardmask films deposited on substrates in the processing chamber. As such, hardmask films having desired film properties can be deposited in the processing chamber without scaling up the RF power to the chamber.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: March 8, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Eswaranand Venkatasubramanian, Edward L. Haywood, Samuel E. Gottheim, Pramit Manna, Kien N. Chuc, Adam Fischbach, Abhijit B. Mallick, Timothy J. Franklin
  • Patent number: 11271107
    Abstract: A semiconductor device structure comprises at least one semiconductor fin for a vertical transport field effect transistor, a bottom source/drain layer, and an insulating layer underlying the bottom source/drain layer. A method of forming the structure comprises forming a sacrificial layer within a lower portion of a source/drain region for a vertical transport field effect transistor structure. The sacrificial layer being formed adjacent to at least one semiconductor fin and in contact with a substrate. A source/drain layer is formed within an upper portion of the source/drain region above the sacrificial layer. The sacrificial layer is removed thereby forming a cavity between the substrate and the source/drain layer. An insulating layer is formed within the cavity.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: March 8, 2022
    Assignee: International Business Machines Corporation
    Inventors: Tao Li, Tsung-Sheng Kang, Ruilong Xie, Alexander Reznicek
  • Patent number: 11264499
    Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and a source region and a drain region, each of which comprise an epi cavity with a bottom surface and a side surface. The transistor further includes an interface layer positioned on at least one of the side surface and the bottom surface of the epi cavity in each of the source/drain regions, wherein the interface layer comprises a non-semiconductor material and an epi semiconductor material positioned on at least an upper surface of the interface layer in the epi cavity in each of the source region and the drain region.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: March 1, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: John J. Pekarik, Steven M. Shank, Anthony K. Stamper, Vibhor Jain, John Ellis-Monaghan
  • Patent number: 11251131
    Abstract: A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Lin Su, Ching-Hua Hsieh, Huang-Ming Chen, Hsueh Wen Tsau
  • Patent number: 11251303
    Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: February 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Lin Lee, Chih-Hao Chang, Chih-Hsin Ko, Feng Yuan, Jeff J. Xu
  • Patent number: 11245024
    Abstract: A method of manufacturing a semiconductor device includes forming a fin structure comprising alternately stacked first semiconductor layers and second semiconductor layers over a substrate. A sacrificial gate structure is formed over the fin structure. Spacers are formed on either side of the sacrificial gate structure. The sacrificial gate structure is removed to form a trench between the spacers. The first semiconductor layers are removed from the trench, while leaving the second semiconductor layers suspended in the trench. A self-assembling monolayer is formed on sidewalls of the spacers in the trench. Interfacial layers are formed encircling the suspended second semiconductor layers, respectively. A high-k dielectric layer is deposited at a faster deposition rate on the interfacial layers than on the self-assembling monolayer. A metal gate structure is formed over the high-k dielectric layer.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: February 8, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY, NATIONAL TAIWAN NORMAL UNIVERSITY
    Inventors: Tung-Ying Lee, Tse-An Chen, Tzu-Chung Wang, Miin-Jang Chen, Yu-Tung Yin, Meng-Chien Yang
  • Patent number: 11239363
    Abstract: A semiconductor device including an active region extending in a first direction on a substrate; a gate structure intersecting the active region and extending in a second direction on the substrate; and a source/drain region on the active region and at least one side of the gate structure, wherein the source/drain region includes a plurality of first epitaxial layers spaced apart from each other in the first direction, the plurality of first epitaxial layers including first impurities of a first conductivity type; and a second epitaxial layer filling a space between the plurality of first epitaxial layers, the second epitaxial layer including second impurities of the first conductivity type.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: February 1, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Uk Jang, Ki Hwan Kim, Su Jin Jung, Bong Soo Kim, Young Dae Cho
  • Patent number: 11205713
    Abstract: An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Ching Lin, Chien-I Kuo, Wei Te Chiang, Wei Hao Lu, Li-Li Su, Chii-Horng Li
  • Patent number: 11177385
    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a channel region in a semiconductor body. The gate structure has a first side surface and a second side surface opposite the first side surface. A first source/drain region is positioned adjacent to the first side surface of the gate structure and a second source/drain region is positioned adjacent to the second side surface of the gate structure. The first source/drain region includes a first epitaxial semiconductor layer, and the second source/drain region includes a second epitaxial semiconductor layer. A first top surface of the first epitaxial semiconductor layer is positioned at a first distance from the channel region, a second top surface of the second epitaxial semiconductor layer is positioned at a second distance from the channel region, and the first distance is greater than the second distance.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: November 16, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Haiting Wang, Sipeng Gu, Jiehui Shu, Baofu Zhu
  • Patent number: 11133401
    Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate. The first and second fin structures have respective first and second vertical dimensions that are about equal to each other. The method further includes modifying the first fin structure such that the first vertical dimension of the first fin structure is smaller than the second vertical dimension of the second fin structure and depositing a dielectric layer on the modified first fin structure and the second fin structure. The method further includes forming a polysilicon structure on the dielectric layer and selectively forming a spacer on a sidewall of the polysilicon structure.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju
  • Patent number: 11094797
    Abstract: A structure includes a semiconductor substrate, a source epitaxial structure, a drain epitaxial structure, and a gate stack. The source epitaxial structure is in the semiconductor substrate. The source epitaxial structure has a top surface, and the top surface of the source epitaxial structure comprises hydrogen. The drain epitaxial structure is in the semiconductor substrate. The gate stack is over the semiconductor substrate and between the source epitaxial structure and the drain epitaxial structure.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Hsiung Tsai, Kei-Wei Chen
  • Patent number: 10868166
    Abstract: A semiconductor device is formed by a multi-step etching process that produces trench openings in a silicon substrate immediately adjacent transistor gate structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the transistor structure and forms the openings. The openings are bounded by upper surfaces that extend downwardly from the substrate surface and are substantially vertical, and lower surfaces that bulge outwardly from the upper vertical sections and undercut the transistor structure. The openings may be filled with a suitable source/drain material to produce SSD transistors with desirable Idsat characteristics.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ta-Wei Kao, Shiang-Bau Wang, Ming-Jie Huang, Chi-Hsi Wu, Shu-Yuan Ku
  • Patent number: 10714376
    Abstract: The present disclosure relates to methods for forming fill materials in trenches having different widths and related structures. A method may include: forming a first fill material in a first and second trench where the second trench has a greater width than the first trench; removing a portion of the first fill material from each trench and forming a second fill material over the first fill material; removing a portion of the first and second fill material within the second trench; and forming a third fill material in the second trench. The structure may include a first fill material in trenches having different widths wherein the upper surfaces of the first fill material in each trench are substantially co-planar. The structure may also include a second fill material on the first fill material in each trench, the second fill material having a substantially equal thickness in each trench.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 14, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chih-Chiang Chang, Haifeng Sheng, Jiehui Shu, Haigou Huang, Pei Liu, Jinping Liu, Haiting Wang, Daniel J. Jaeger
  • Patent number: 10700202
    Abstract: A semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.
    Type: Grant
    Filed: October 28, 2018
    Date of Patent: June 30, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Kai-Hsiang Wang, Chao-Nan Chen, Shi-You Liu, Chun-Wei Yu, Yu-Ren Wang
  • Patent number: 10685881
    Abstract: A method, apparatus, and manufacturing system are disclosed for a fin field effect transistor having a reduced risk of short circuits between a gate and a source/drain contact. In one embodiment, we disclose a semiconductor device including a fin structure comprising a fin body, source/drain regions, and a metal formation disposed above the source/drain regions, wherein the metal formation has a first height; and a gate structure between the source/drain regions, wherein each gate structure comprises spacers in contact with the metal formation, wherein the spacers have a second height less than the first height, a metal plug between the spacers and below the second height, and a T-shaped cap above the metal plug and having the first height.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: June 16, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Guowei Xu, Haiting Wang
  • Patent number: 10679902
    Abstract: Semiconductor device and fabrication method are provided.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: June 9, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) Corporation
    Inventors: Zhi Dong Wang, Cheng Long Zhang, Wu Tao Tu
  • Patent number: 10665608
    Abstract: A semiconductor device according to an embodiment includes a substrate. A transistor includes a source layer and a drain layer that are provided in a surface region of the substrate and contain impurities. A gate dielectric film is provided on the substrate between the source layer and the drain layer. A gate electrode is provided on the gate dielectric film. A first epitaxial layer is provided on the source layer or the drain layer. A second epitaxial layer is provided on the first epitaxial layer and contains both the impurities and carbon. A contact plug is provided on the second epitaxial layer. A memory cell array is provided above the transistor.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: May 26, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomonari Shioda, Junya Fujita, Takayuki Ito
  • Patent number: 10622457
    Abstract: A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: April 14, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBAL FOUNDRIES INC., STMICROELECTRONICS, INC.
    Inventors: Xiuyu Cai, Chun-Chen Yeh, Qing Liu, Ruilong Xie
  • Patent number: 10593780
    Abstract: A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: March 17, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC., STMICROELECTRONICS, INC.
    Inventors: Xiuyu Cai, Chun-Chen Yeh, Qing Liu, Ruilong Xie
  • Patent number: 10573563
    Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a base substrate, and forming an interlayer dielectric layer on the base substrate and having an opening exposing surface portions of the base substrate. The method also includes forming a stacked structure on a bottom and sidewall of the opening and on a top of the interlayer dielectric layer. In addition, the method includes removing at least a first portion of the stacked structure from the top of the interlayer dielectric layer. Further, the method includes performing an annealing treatment on the base substrate, and forming a gate structure by filling the opening with a metal layer.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: February 25, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li
  • Patent number: 10546943
    Abstract: Methods, apparatus, and systems for forming a semiconductor substrate comprising a well region containing a first impurity; forming a gate on the semiconductor substrate above the well region; implanting a second impurity, of a type opposite the first impurity, in the well region on each side of the gate and to a depth above a bottom of the well region, to form two second impurity regions each having a first concentration; removing an upper portion of each second impurity region, to yield two source/drain (S/D) cavities above two depletion regions; and growing epitaxially a doped S/D region in each S/D cavity, wherein each S/D region comprises the second impurity having a second concentration greater than the first concentration.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: January 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Arkadiusz Malinowski, Jagar Singh
  • Patent number: 10529803
    Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. In some embodiments, the semiconductor device includes a fin extending from a substrate and a gate structure disposed over the fin. The gate structure includes a gate dielectric formed over the fin, a gate electrode formed over the gate dielectric, and a sidewall spacer formed along a sidewall of the gate electrode. In some cases, a U-shaped recess is within the fin and adjacent to the gate structure. A first source/drain layer is conformally formed on a surface of the U-shaped recess, where the first source/drain layer extends at least partially under the adjacent gate structure. A second source/drain layer is formed over the first source/drain layer. At least one of the first and second source/drain layers includes silicon arsenide (SiAs).
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ta Yu, Sheng-Chen Wang, Wei-Yuan Lu, Chien-I Kuo, Li-Li Su, Feng-Cheng Yang, Yen-Ming Chen, Sai-Hooi Yeong
  • Patent number: 10483355
    Abstract: A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: November 19, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Matthias Bauer, Hans-Joachim L. Gossmann, Benjamin Colombeau
  • Patent number: 10424634
    Abstract: In a semiconductor device, a source and a drain layers are located in a surface region of a substrate. A source crystal layer is located in a contact region of the source layer to extend to a position higher than the substrate. A drain crystal layer is located in a contact region of the drain layer to extend to a position higher than the substrate. A source contact is located on the source crystal layer. A drain contact is located on the drain crystal layer. A gate width or a gate length extends to a crystal orientation <110> of the substrate. A long side or a major axis of the source crystal layer or a long side or a major axis of the drain crystal layer extends in a direction inclined with respect to the crystal orientation <110> in a planar layout parallel to the surface of the substrate.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: September 24, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yasunori Oshima, Takayuki Ito
  • Patent number: 10304819
    Abstract: A semiconductor device includes a cell region that includes a first active region and a second active region extending in a first direction and a separation region between the first active region and the second active region. The cell region has a first width. A first gate structure and a second gate structure are disposed on the cell region, are spaced apart from each other in the first direction, and extend in the second direction. A first metal line and a second metal line are disposed on the cell region, extend in the first direction, and are spaced apart from each other by a first pitch. Each of the first and second metal lines has a second width. A first gate contact electrically connects the first gate structure and the first metal line. At least a portion of the first gate contact overlaps the separation region. A second gate contact electrically connects the second gate structure and the second metal line. At least a portion of the second gate contact overlaps the separation region.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyo Jin Kim, Kwan Young Chun
  • Patent number: 10249731
    Abstract: VFET devices and techniques for formation thereof having well-defined, sharp source/drain-to-channel junctions are provided. In one aspect, a method of forming a VFET device includes: forming a SiGe layer on a substrate, wherein the SiGe layer as formed on the substrate is undoped; forming an Si layer on the SiGe layer, wherein the Si layer as formed on the SiGe layer is undoped; patterning fins in the Si layer; forming sacrificial spacers along sidewalls of the fins; forming recesses in the SiGe layer between the fins; growing an epitaxial material in the recesses, wherein the epitaxial material grown in the recesses includes a source and drain dopant; annealing the epitaxial material to diffuse the source drain dopant into the SiGe layer under the fins forming bottom source and drains of the VFET device; and removing the sacrificial spacers. A VFET device formed by the method is also provided.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: April 2, 2019
    Assignee: International Business Macines Corporation
    Inventors: Juntao Li, Kangguo Cheng, Peng Xu, Heng Wu
  • Patent number: 10224433
    Abstract: In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: March 5, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuji Egi, Hideomi Suzawa, Shinya Sasagawa
  • Patent number: 10217842
    Abstract: A method for making a semiconductor device, including: a) making, on a substrate, a stack comprising a first semiconductor portion able to form an active zone and arranged between two second portions of a material able to be selectively etched relative to the semiconductor of the first portion, b) making, on a part of the stack, outer spacers and a dummy gate, c) etching the second portions such that remaining parts are arranged under the dummy gate, d) partially oxidizing the remaining parts from the outer faces, forming inner spacers, e) removing the dummy gate and non-oxidized parts of the remaining parts arranged under the dummy gate, f) making a gate between the outer spacers and between the inner spacers and covering the channel.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: February 26, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand
  • Patent number: 10164024
    Abstract: Various heterostructures and methods of forming heterostructures are disclosed. A method includes removing portions of a substrate to form a temporary fin protruding above the substrate, forming a dielectric material over the substrate and over the temporary fin, removing the temporary fin to form a trench in the dielectric material, the trench exposing a portion of a first crystalline material of the substrate, forming a template material at least partially in the trench, the template material being a second crystalline material that is lattice mismatched to the first crystalline material, forming a barrier material over the template material, the barrier material being a third crystalline material, forming a device material over the barrier material, the device material being a fourth crystalline material, forming a gate stack over the device material, and forming a first source/drain region and a second source/drain region in the device material.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Martin Christopher Holland, Georgios Vellianitis, Richard Kenneth Oxland, Krishna Kumar Bhuwalka, Gerben Doornbos
  • Patent number: 10164098
    Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Min Huang, Shih-Chieh Chang, Cheng-Han Lee
  • Patent number: 10158022
    Abstract: A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The second semiconductor layer includes a recessed portion, the air gap is located in the recessed portion, and the recessed portion has an upwardly-opening acute angle in the range from about 10° to about 55°. The air gap may prevent current leakage. A FinFET device may be manufactured by first recessing and then epitaxially re-growing a source/drain fin, with the regrowth starting over a tubular air gap.
    Type: Grant
    Filed: August 20, 2017
    Date of Patent: December 18, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Sheng-Hsu Liu, Jhen-cyuan Li, Chih-Chung Chen, Man-Ling Lu, Chung-Min Tsai, Yi-Wei Chen
  • Patent number: 10083872
    Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Chia Tai Lin, Chao-Cheng Chen
  • Patent number: 10068995
    Abstract: In a method of fabricating a field effect transistor, a fin structure made of a first semiconductor material is formed so that the fin structure protrudes from an isolation insulating layer disposed over a substrate. A gate structure is formed over a part of the fin structure, thereby defining a channel region, a source region and a drain region in the fin structure. After the gate structure is formed, laser annealing is performed on the fin structure.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: September 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fang-Liang Lu, CheeWee Liu, Chi-Wen Liu, Shih-Hsien Huang, I-Hsieh Wong
  • Patent number: 10032628
    Abstract: A method for improving source/drain performance through conformal solid state doping and its resulting device are disclosed. Specifically, the doping takes place through an atomic layer deposition of a dopant layer. Embodiments of the invention may allow for an increased doping layer, improved conformality, and reduced defect formation, in comparison to alternate doping methods, such as ion implantation or epitaxial doping.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: July 24, 2018
    Assignee: ASM IP Holding B.V.
    Inventors: Qi Xie, David de Roest, Jacob Woodruff, Michael Eugene Givens, Jan Willem Maes, Timothee Blanquart
  • Patent number: 10020397
    Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: July 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eric Peng, Chao-Cheng Chen, Chii-Horng Li, Ming-Hua Yu, Shih-Hao Lo, Syun-Ming Jang, Tze-Liang Lee, Ying Hao Hsieh
  • Patent number: 9984940
    Abstract: A scaled dielectric stack interlayer, compatible with subsequent high temperature processing with good electrical transport & reliability properties is provided. A method for forming a conformal aSi:H passivation layer on a semiconductor device is described. A patterned semiconductor wafer is placed in in a process chamber with a first layer formed thereon and a second layer formed thereon, the first layer and the second layer being two different materials Next, a SixH(2x+2) based deposition up to a temperature of 400 degrees Celsius is used on the first layer and the second layer thereby forming a conformal aSi:H passivating layer is formed at a higher rate of deposition on the first layer selectively and a lower rate of deposit on the second layer.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Stephen M. Gates, Masanobu Hatanaka, Vijay Narayanan, Deborah A. Neumayer, Yohei Ogawa, John Rozen
  • Patent number: 9953979
    Abstract: A semiconductor device includes a gate stack. The semiconductor device also includes a wrap-around contact arranged around and contacting substantially all surface area of a regrown source/drain region of the semiconductor device proximate to the gate stack.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: April 24, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Jeffrey Junhao Xu, Stanley Seungchul Song, Vladimir Machkaoutsan, Mustafa Badaroglu, Junjing Bao, John Jianhong Zhu, Da Yang, Choh Fei Yeap
  • Patent number: 9947747
    Abstract: A p-type metal-oxide-semiconductor (pMOS) planar fully depleted silicon-on-insulator (FDSOI) device and a method of fabricating the pMOS FDSOI are described. The method includes processing a silicon germanium (SiGe) layer disposed on an insulator layer to form gaps on a surface opposite a surface that is disposed on the insulator layer, each of the gaps extending into the SiGe layer to a depth less than or equal to a thickness of the SiGe layer, and forming a gate conductor over a region of the SiGe layer corresponding to a channel region of the pMOS. The method also includes performing an epitaxial process on the SiGe layer at locations corresponding to source and drain regions of the pMOS planar FDSOI device.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: April 17, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Shawn P. Fetterolf, Ahmet S. Ozcan
  • Patent number: 9911656
    Abstract: A method for co-integrating wimpy and nominal devices includes growing source/drain regions on semiconductor material adjacent to a gate structure to form device structures with a non-electrically active material. Selected device structures are masked with a block mask. Unmasked device structures are selectively annealed to increase electrical activity of the non-electrically active material to adjust a threshold voltage between the selected device structures and the unmasked device structures.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Nicolas J. Loubet, Xin Miao, Alexander Reznicek
  • Patent number: 9859389
    Abstract: A method for forming a semiconductor device comprises forming a sacrificial gate stack on a substrate, spacers adjacent to the sacrificial gate stack, and a source/drain region on the substrate. A first insulator layer is formed on the source/drain region. A portion of the first insulator layer is removed to expose portions of the spacers. Exposed sidewall portions of the spacers are removed to reduce a thickness of the exposed portions of the spacers. A protective layer is deposited over the exposed sidewalls of the spacers and a second insulator layer is deposited over the protective layer. The sacrificial gate is removed to expose a channel region of the substrate. A gate stack is formed over the channel region of the substrate. Exposed portions of the first insulator layer and the second insulator layer are removed to expose the source/drain region, and a conductive is formed on the source/drain region.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 9780191
    Abstract: The invention describes a method for forming spacers (152a, 152b) of a field effect transistor gate, comprising a step of forming a protection layer (152) covering the gate of said transistor, at least a step of modifying the protection layer, executed after the step of forming the protection layer, by contacting the protection layer (152) with plasma comprising ions heavier than hydrogen and CxHy where x is the proportion of carbon and y is the proportion of hydrogen to form a modified protection layer (158) and a carbon film (271). The protection layer being nitride (N)-based and/or silicon (Si)-based and/or carbon (C)-based and shows a dielectric constant equal or less than 8.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: October 3, 2017
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventor: Nicolas Posseme
  • Patent number: 9735252
    Abstract: Some embodiments of the present disclosure relates to a method of forming a transistor device having a strained channel and an associated device. In some embodiments, the method is performed by performing a first etch of a substrate to produce a recess having a largest width at an opening along a top surface of the substrate. An etch stop layer is formed by doping a bottom surface of the recess with a dopant. A second etch of the recess is then performed to form a source/drain recess, wherein the etch stop layer resists etching of the second etch. A stress inducing material is formed within the source/drain recess onto the etch stop layer.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Hsuing Chen, Ling-Sung Wang, Chi-Yen Lin
  • Patent number: 9673196
    Abstract: A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: June 6, 2017
    Assignee: GlobalFoundries, Inc.
    Inventors: Thomas N. Adam, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9666684
    Abstract: A method including forming a III-V compound semiconductor-containing heterostructure, forming a gate dielectric having a dielectric constant greater than 4.0 positioned within a gate trench, the gate trench formed within the III-V compound semiconductor-containing heterostructure, and forming a gate conductor within the gate trench on top of the gate dielectric, the gate conductor extending above the III-V compound semiconductor heterostructure. The method further including forming a pair of sidewall spacers along opposite sides of a portion of the gate conductor extending above the III-V compound semiconductor-containing heterostructure and forming a pair of source-drain contacts self-aligned to the pair of sidewall spacers.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: May 30, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anirban Basu, Amlan Majumdar, Yanning Sun
  • Patent number: 9653584
    Abstract: Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting. The etched, thinned fins may be formed by first forming wider single crystal fins, and after depositing trench oxide material between the wider fins, etching the wider fins using a second etch to form narrower single crystal fins having undamaged top and sidewalls for epitaxially growing active channel material. The second etch may remove a thickness of between a 1 nm and 15 nm of the top surfaces and the sidewalls of the wider fins. It may remove the thickness using (1) chlorine or fluorine based chemistry using low ion energy plasma processing, or (2) low temperature thermal processing that does not damage fins via energetic ion bombardment, oxidation or by leaving behind etch residue that could disrupt the epitaxial growth quality of the second material.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Daniel B. Aubertine, Subhash M. Joshi
  • Patent number: 9576858
    Abstract: A three-dimensional stacked fin complementary metal oxide semiconductor (CMOS) device having dual work function metal gate structures is provided. The stacked fin CMOS device includes a fin stack having a first semiconductor fin over a substrate, a dielectric fin atop the first semiconductor fin and a second semiconductor fin atop the dielectric fin, and a gate sack straddling the fin stack. The gate stack includes a first metal gate portion surrounding a channel portion of the first semiconductor fin and a second metal gate portion surrounding a channel portion of the second semiconductor fin. The first metal gate portion has a first work function suitable to reduce a threshold voltage of a field effect transistor (FET) of a first conductivity type, while the second gate portion has a second work function suitable to reduce a threshold voltage of a FET of a second conductivity type opposite the first conductivity type.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: February 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9543399
    Abstract: A semiconductor device having an open profile gate electrode, and a method of manufacture, are provided. A funnel-shaped opening is formed in a dielectric layer and a gate electrode is formed in the funnel-shaped opening, thereby providing a gate electrode having an open profile. In some embodiments, first and second gate spacers are formed alongside a dummy gate electrode. The dummy gate electrode is removed and upper portions of the first and second gate spacers are removed. The first and second gate spacers may be formed of different materials having different etch rates.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: January 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Shang Hsiao, Ling-Sung Wang, Chih-Mu Huang, Yao-Tsung Chen, Ming-Tsang Tsai, Kuan-Yu Chen