Having Elevated Source Or Drain (e.g., Epitaxially Formed Source Or Drain, Etc.) Patents (Class 438/300)
  • Patent number: 10868166
    Abstract: A semiconductor device is formed by a multi-step etching process that produces trench openings in a silicon substrate immediately adjacent transistor gate structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the transistor structure and forms the openings. The openings are bounded by upper surfaces that extend downwardly from the substrate surface and are substantially vertical, and lower surfaces that bulge outwardly from the upper vertical sections and undercut the transistor structure. The openings may be filled with a suitable source/drain material to produce SSD transistors with desirable Idsat characteristics.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ta-Wei Kao, Shiang-Bau Wang, Ming-Jie Huang, Chi-Hsi Wu, Shu-Yuan Ku
  • Patent number: 10714376
    Abstract: The present disclosure relates to methods for forming fill materials in trenches having different widths and related structures. A method may include: forming a first fill material in a first and second trench where the second trench has a greater width than the first trench; removing a portion of the first fill material from each trench and forming a second fill material over the first fill material; removing a portion of the first and second fill material within the second trench; and forming a third fill material in the second trench. The structure may include a first fill material in trenches having different widths wherein the upper surfaces of the first fill material in each trench are substantially co-planar. The structure may also include a second fill material on the first fill material in each trench, the second fill material having a substantially equal thickness in each trench.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 14, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chih-Chiang Chang, Haifeng Sheng, Jiehui Shu, Haigou Huang, Pei Liu, Jinping Liu, Haiting Wang, Daniel J. Jaeger
  • Patent number: 10700202
    Abstract: A semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.
    Type: Grant
    Filed: October 28, 2018
    Date of Patent: June 30, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuang-Hsiu Chen, Sung-Yuan Tsai, Chi-Hsuan Tang, Kai-Hsiang Wang, Chao-Nan Chen, Shi-You Liu, Chun-Wei Yu, Yu-Ren Wang
  • Patent number: 10685881
    Abstract: A method, apparatus, and manufacturing system are disclosed for a fin field effect transistor having a reduced risk of short circuits between a gate and a source/drain contact. In one embodiment, we disclose a semiconductor device including a fin structure comprising a fin body, source/drain regions, and a metal formation disposed above the source/drain regions, wherein the metal formation has a first height; and a gate structure between the source/drain regions, wherein each gate structure comprises spacers in contact with the metal formation, wherein the spacers have a second height less than the first height, a metal plug between the spacers and below the second height, and a T-shaped cap above the metal plug and having the first height.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: June 16, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Guowei Xu, Haiting Wang
  • Patent number: 10679902
    Abstract: Semiconductor device and fabrication method are provided.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: June 9, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) Corporation
    Inventors: Zhi Dong Wang, Cheng Long Zhang, Wu Tao Tu
  • Patent number: 10665608
    Abstract: A semiconductor device according to an embodiment includes a substrate. A transistor includes a source layer and a drain layer that are provided in a surface region of the substrate and contain impurities. A gate dielectric film is provided on the substrate between the source layer and the drain layer. A gate electrode is provided on the gate dielectric film. A first epitaxial layer is provided on the source layer or the drain layer. A second epitaxial layer is provided on the first epitaxial layer and contains both the impurities and carbon. A contact plug is provided on the second epitaxial layer. A memory cell array is provided above the transistor.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: May 26, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomonari Shioda, Junya Fujita, Takayuki Ito
  • Patent number: 10622457
    Abstract: A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: April 14, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBAL FOUNDRIES INC., STMICROELECTRONICS, INC.
    Inventors: Xiuyu Cai, Chun-Chen Yeh, Qing Liu, Ruilong Xie
  • Patent number: 10593780
    Abstract: A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: March 17, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC., STMICROELECTRONICS, INC.
    Inventors: Xiuyu Cai, Chun-Chen Yeh, Qing Liu, Ruilong Xie
  • Patent number: 10573563
    Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a base substrate, and forming an interlayer dielectric layer on the base substrate and having an opening exposing surface portions of the base substrate. The method also includes forming a stacked structure on a bottom and sidewall of the opening and on a top of the interlayer dielectric layer. In addition, the method includes removing at least a first portion of the stacked structure from the top of the interlayer dielectric layer. Further, the method includes performing an annealing treatment on the base substrate, and forming a gate structure by filling the opening with a metal layer.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: February 25, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li
  • Patent number: 10546943
    Abstract: Methods, apparatus, and systems for forming a semiconductor substrate comprising a well region containing a first impurity; forming a gate on the semiconductor substrate above the well region; implanting a second impurity, of a type opposite the first impurity, in the well region on each side of the gate and to a depth above a bottom of the well region, to form two second impurity regions each having a first concentration; removing an upper portion of each second impurity region, to yield two source/drain (S/D) cavities above two depletion regions; and growing epitaxially a doped S/D region in each S/D cavity, wherein each S/D region comprises the second impurity having a second concentration greater than the first concentration.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: January 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Arkadiusz Malinowski, Jagar Singh
  • Patent number: 10529803
    Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. In some embodiments, the semiconductor device includes a fin extending from a substrate and a gate structure disposed over the fin. The gate structure includes a gate dielectric formed over the fin, a gate electrode formed over the gate dielectric, and a sidewall spacer formed along a sidewall of the gate electrode. In some cases, a U-shaped recess is within the fin and adjacent to the gate structure. A first source/drain layer is conformally formed on a surface of the U-shaped recess, where the first source/drain layer extends at least partially under the adjacent gate structure. A second source/drain layer is formed over the first source/drain layer. At least one of the first and second source/drain layers includes silicon arsenide (SiAs).
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ta Yu, Sheng-Chen Wang, Wei-Yuan Lu, Chien-I Kuo, Li-Li Su, Feng-Cheng Yang, Yen-Ming Chen, Sai-Hooi Yeong
  • Patent number: 10483355
    Abstract: A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: November 19, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Matthias Bauer, Hans-Joachim L. Gossmann, Benjamin Colombeau
  • Patent number: 10424634
    Abstract: In a semiconductor device, a source and a drain layers are located in a surface region of a substrate. A source crystal layer is located in a contact region of the source layer to extend to a position higher than the substrate. A drain crystal layer is located in a contact region of the drain layer to extend to a position higher than the substrate. A source contact is located on the source crystal layer. A drain contact is located on the drain crystal layer. A gate width or a gate length extends to a crystal orientation <110> of the substrate. A long side or a major axis of the source crystal layer or a long side or a major axis of the drain crystal layer extends in a direction inclined with respect to the crystal orientation <110> in a planar layout parallel to the surface of the substrate.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: September 24, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yasunori Oshima, Takayuki Ito
  • Patent number: 10304819
    Abstract: A semiconductor device includes a cell region that includes a first active region and a second active region extending in a first direction and a separation region between the first active region and the second active region. The cell region has a first width. A first gate structure and a second gate structure are disposed on the cell region, are spaced apart from each other in the first direction, and extend in the second direction. A first metal line and a second metal line are disposed on the cell region, extend in the first direction, and are spaced apart from each other by a first pitch. Each of the first and second metal lines has a second width. A first gate contact electrically connects the first gate structure and the first metal line. At least a portion of the first gate contact overlaps the separation region. A second gate contact electrically connects the second gate structure and the second metal line. At least a portion of the second gate contact overlaps the separation region.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyo Jin Kim, Kwan Young Chun
  • Patent number: 10249731
    Abstract: VFET devices and techniques for formation thereof having well-defined, sharp source/drain-to-channel junctions are provided. In one aspect, a method of forming a VFET device includes: forming a SiGe layer on a substrate, wherein the SiGe layer as formed on the substrate is undoped; forming an Si layer on the SiGe layer, wherein the Si layer as formed on the SiGe layer is undoped; patterning fins in the Si layer; forming sacrificial spacers along sidewalls of the fins; forming recesses in the SiGe layer between the fins; growing an epitaxial material in the recesses, wherein the epitaxial material grown in the recesses includes a source and drain dopant; annealing the epitaxial material to diffuse the source drain dopant into the SiGe layer under the fins forming bottom source and drains of the VFET device; and removing the sacrificial spacers. A VFET device formed by the method is also provided.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: April 2, 2019
    Assignee: International Business Macines Corporation
    Inventors: Juntao Li, Kangguo Cheng, Peng Xu, Heng Wu
  • Patent number: 10224433
    Abstract: In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: March 5, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuji Egi, Hideomi Suzawa, Shinya Sasagawa
  • Patent number: 10217842
    Abstract: A method for making a semiconductor device, including: a) making, on a substrate, a stack comprising a first semiconductor portion able to form an active zone and arranged between two second portions of a material able to be selectively etched relative to the semiconductor of the first portion, b) making, on a part of the stack, outer spacers and a dummy gate, c) etching the second portions such that remaining parts are arranged under the dummy gate, d) partially oxidizing the remaining parts from the outer faces, forming inner spacers, e) removing the dummy gate and non-oxidized parts of the remaining parts arranged under the dummy gate, f) making a gate between the outer spacers and between the inner spacers and covering the channel.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: February 26, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand
  • Patent number: 10164098
    Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Min Huang, Shih-Chieh Chang, Cheng-Han Lee
  • Patent number: 10164024
    Abstract: Various heterostructures and methods of forming heterostructures are disclosed. A method includes removing portions of a substrate to form a temporary fin protruding above the substrate, forming a dielectric material over the substrate and over the temporary fin, removing the temporary fin to form a trench in the dielectric material, the trench exposing a portion of a first crystalline material of the substrate, forming a template material at least partially in the trench, the template material being a second crystalline material that is lattice mismatched to the first crystalline material, forming a barrier material over the template material, the barrier material being a third crystalline material, forming a device material over the barrier material, the device material being a fourth crystalline material, forming a gate stack over the device material, and forming a first source/drain region and a second source/drain region in the device material.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Martin Christopher Holland, Georgios Vellianitis, Richard Kenneth Oxland, Krishna Kumar Bhuwalka, Gerben Doornbos
  • Patent number: 10158022
    Abstract: A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The second semiconductor layer includes a recessed portion, the air gap is located in the recessed portion, and the recessed portion has an upwardly-opening acute angle in the range from about 10° to about 55°. The air gap may prevent current leakage. A FinFET device may be manufactured by first recessing and then epitaxially re-growing a source/drain fin, with the regrowth starting over a tubular air gap.
    Type: Grant
    Filed: August 20, 2017
    Date of Patent: December 18, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Sheng-Hsu Liu, Jhen-cyuan Li, Chih-Chung Chen, Man-Ling Lu, Chung-Min Tsai, Yi-Wei Chen
  • Patent number: 10083872
    Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Chia Tai Lin, Chao-Cheng Chen
  • Patent number: 10068995
    Abstract: In a method of fabricating a field effect transistor, a fin structure made of a first semiconductor material is formed so that the fin structure protrudes from an isolation insulating layer disposed over a substrate. A gate structure is formed over a part of the fin structure, thereby defining a channel region, a source region and a drain region in the fin structure. After the gate structure is formed, laser annealing is performed on the fin structure.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: September 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fang-Liang Lu, CheeWee Liu, Chi-Wen Liu, Shih-Hsien Huang, I-Hsieh Wong
  • Patent number: 10032628
    Abstract: A method for improving source/drain performance through conformal solid state doping and its resulting device are disclosed. Specifically, the doping takes place through an atomic layer deposition of a dopant layer. Embodiments of the invention may allow for an increased doping layer, improved conformality, and reduced defect formation, in comparison to alternate doping methods, such as ion implantation or epitaxial doping.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: July 24, 2018
    Assignee: ASM IP Holding B.V.
    Inventors: Qi Xie, David de Roest, Jacob Woodruff, Michael Eugene Givens, Jan Willem Maes, Timothee Blanquart
  • Patent number: 10020397
    Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: July 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eric Peng, Chao-Cheng Chen, Chii-Horng Li, Ming-Hua Yu, Shih-Hao Lo, Syun-Ming Jang, Tze-Liang Lee, Ying Hao Hsieh
  • Patent number: 9984940
    Abstract: A scaled dielectric stack interlayer, compatible with subsequent high temperature processing with good electrical transport & reliability properties is provided. A method for forming a conformal aSi:H passivation layer on a semiconductor device is described. A patterned semiconductor wafer is placed in in a process chamber with a first layer formed thereon and a second layer formed thereon, the first layer and the second layer being two different materials Next, a SixH(2x+2) based deposition up to a temperature of 400 degrees Celsius is used on the first layer and the second layer thereby forming a conformal aSi:H passivating layer is formed at a higher rate of deposition on the first layer selectively and a lower rate of deposit on the second layer.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Stephen M. Gates, Masanobu Hatanaka, Vijay Narayanan, Deborah A. Neumayer, Yohei Ogawa, John Rozen
  • Patent number: 9953979
    Abstract: A semiconductor device includes a gate stack. The semiconductor device also includes a wrap-around contact arranged around and contacting substantially all surface area of a regrown source/drain region of the semiconductor device proximate to the gate stack.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: April 24, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Jeffrey Junhao Xu, Stanley Seungchul Song, Vladimir Machkaoutsan, Mustafa Badaroglu, Junjing Bao, John Jianhong Zhu, Da Yang, Choh Fei Yeap
  • Patent number: 9947747
    Abstract: A p-type metal-oxide-semiconductor (pMOS) planar fully depleted silicon-on-insulator (FDSOI) device and a method of fabricating the pMOS FDSOI are described. The method includes processing a silicon germanium (SiGe) layer disposed on an insulator layer to form gaps on a surface opposite a surface that is disposed on the insulator layer, each of the gaps extending into the SiGe layer to a depth less than or equal to a thickness of the SiGe layer, and forming a gate conductor over a region of the SiGe layer corresponding to a channel region of the pMOS. The method also includes performing an epitaxial process on the SiGe layer at locations corresponding to source and drain regions of the pMOS planar FDSOI device.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: April 17, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Shawn P. Fetterolf, Ahmet S. Ozcan
  • Patent number: 9911656
    Abstract: A method for co-integrating wimpy and nominal devices includes growing source/drain regions on semiconductor material adjacent to a gate structure to form device structures with a non-electrically active material. Selected device structures are masked with a block mask. Unmasked device structures are selectively annealed to increase electrical activity of the non-electrically active material to adjust a threshold voltage between the selected device structures and the unmasked device structures.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Nicolas J. Loubet, Xin Miao, Alexander Reznicek
  • Patent number: 9859389
    Abstract: A method for forming a semiconductor device comprises forming a sacrificial gate stack on a substrate, spacers adjacent to the sacrificial gate stack, and a source/drain region on the substrate. A first insulator layer is formed on the source/drain region. A portion of the first insulator layer is removed to expose portions of the spacers. Exposed sidewall portions of the spacers are removed to reduce a thickness of the exposed portions of the spacers. A protective layer is deposited over the exposed sidewalls of the spacers and a second insulator layer is deposited over the protective layer. The sacrificial gate is removed to expose a channel region of the substrate. A gate stack is formed over the channel region of the substrate. Exposed portions of the first insulator layer and the second insulator layer are removed to expose the source/drain region, and a conductive is formed on the source/drain region.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: January 2, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 9780191
    Abstract: The invention describes a method for forming spacers (152a, 152b) of a field effect transistor gate, comprising a step of forming a protection layer (152) covering the gate of said transistor, at least a step of modifying the protection layer, executed after the step of forming the protection layer, by contacting the protection layer (152) with plasma comprising ions heavier than hydrogen and CxHy where x is the proportion of carbon and y is the proportion of hydrogen to form a modified protection layer (158) and a carbon film (271). The protection layer being nitride (N)-based and/or silicon (Si)-based and/or carbon (C)-based and shows a dielectric constant equal or less than 8.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: October 3, 2017
    Assignee: Commissariat a l'energie atomique et aux energies alternatives
    Inventor: Nicolas Posseme
  • Patent number: 9735252
    Abstract: Some embodiments of the present disclosure relates to a method of forming a transistor device having a strained channel and an associated device. In some embodiments, the method is performed by performing a first etch of a substrate to produce a recess having a largest width at an opening along a top surface of the substrate. An etch stop layer is formed by doping a bottom surface of the recess with a dopant. A second etch of the recess is then performed to form a source/drain recess, wherein the etch stop layer resists etching of the second etch. A stress inducing material is formed within the source/drain recess onto the etch stop layer.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Hsuing Chen, Ling-Sung Wang, Chi-Yen Lin
  • Patent number: 9673196
    Abstract: A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: June 6, 2017
    Assignee: GlobalFoundries, Inc.
    Inventors: Thomas N. Adam, Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9666684
    Abstract: A method including forming a III-V compound semiconductor-containing heterostructure, forming a gate dielectric having a dielectric constant greater than 4.0 positioned within a gate trench, the gate trench formed within the III-V compound semiconductor-containing heterostructure, and forming a gate conductor within the gate trench on top of the gate dielectric, the gate conductor extending above the III-V compound semiconductor heterostructure. The method further including forming a pair of sidewall spacers along opposite sides of a portion of the gate conductor extending above the III-V compound semiconductor-containing heterostructure and forming a pair of source-drain contacts self-aligned to the pair of sidewall spacers.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: May 30, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Anirban Basu, Amlan Majumdar, Yanning Sun
  • Patent number: 9653584
    Abstract: Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting. The etched, thinned fins may be formed by first forming wider single crystal fins, and after depositing trench oxide material between the wider fins, etching the wider fins using a second etch to form narrower single crystal fins having undamaged top and sidewalls for epitaxially growing active channel material. The second etch may remove a thickness of between a 1 nm and 15 nm of the top surfaces and the sidewalls of the wider fins. It may remove the thickness using (1) chlorine or fluorine based chemistry using low ion energy plasma processing, or (2) low temperature thermal processing that does not damage fins via energetic ion bombardment, oxidation or by leaving behind etch residue that could disrupt the epitaxial growth quality of the second material.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Daniel B. Aubertine, Subhash M. Joshi
  • Patent number: 9576858
    Abstract: A three-dimensional stacked fin complementary metal oxide semiconductor (CMOS) device having dual work function metal gate structures is provided. The stacked fin CMOS device includes a fin stack having a first semiconductor fin over a substrate, a dielectric fin atop the first semiconductor fin and a second semiconductor fin atop the dielectric fin, and a gate sack straddling the fin stack. The gate stack includes a first metal gate portion surrounding a channel portion of the first semiconductor fin and a second metal gate portion surrounding a channel portion of the second semiconductor fin. The first metal gate portion has a first work function suitable to reduce a threshold voltage of a field effect transistor (FET) of a first conductivity type, while the second gate portion has a second work function suitable to reduce a threshold voltage of a FET of a second conductivity type opposite the first conductivity type.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: February 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9543399
    Abstract: A semiconductor device having an open profile gate electrode, and a method of manufacture, are provided. A funnel-shaped opening is formed in a dielectric layer and a gate electrode is formed in the funnel-shaped opening, thereby providing a gate electrode having an open profile. In some embodiments, first and second gate spacers are formed alongside a dummy gate electrode. The dummy gate electrode is removed and upper portions of the first and second gate spacers are removed. The first and second gate spacers may be formed of different materials having different etch rates.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: January 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Shang Hsiao, Ling-Sung Wang, Chih-Mu Huang, Yao-Tsung Chen, Ming-Tsang Tsai, Kuan-Yu Chen
  • Patent number: 9530886
    Abstract: A semiconductor device includes a substrate, a gate structure, a spacer, and a plurality of hyper-sigma (?) shaped epitaxial stressors. The substrate includes a first semiconductor material, and the hyper-? shaped epitaxial stressors include the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. The hyper-? shaped epitaxial stressors respectively include a first portion, a second portion and a neck physically connecting the first portion and the second portion. The first portion includes a pair of first tips pointing toward the gate structure in a cross-sectional view. The second portion includes a pair of second tips pointing toward the gate structure in the cross-sectional view. The neck includes a first slanted surface in the first portion and a second slanted surface in the second portion.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: December 27, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ying Lin, Chueh-Yang Liu, Yu-Ren Wang, Neng-Hui Yang
  • Patent number: 9515255
    Abstract: Methods of manufacturing a semiconductor device include forming a conductive layer on a substrate, forming an air gap or other cavity between the conductive layer and the substrate, and patterning the conductive layer to expose the air gap. The methods may further include forming conductive pillars between the substrate and the conductive layer. The air gap may be positioned between the conductive pillars.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: December 6, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongchul Park, Byoungjae Bae, Inho Kim, Shin Kwon, Eunsun Noh, Insun Park, Sangmin Lee
  • Patent number: 9484203
    Abstract: In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An ion implantation process is performed at an upper portion of the substrate exposed by the gate structure, so that an ion implantation region is formed to have an expanded volume. The ion implantation process uses ions that are identical to a material of the substrate.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: November 1, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun-Hee Lim, Ki-Jae Hur, Sung-Hwan Kim, Hae-In Jung, Soo-Jin Hong
  • Patent number: 9466718
    Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: October 11, 2016
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Pierre Morin, Nicolas Loubet
  • Patent number: 9466697
    Abstract: Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: October 11, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Jine Park, Bo-Un Yoon, Jeong-Nam Han, Myung-Geun Song
  • Patent number: 9460955
    Abstract: Integrated circuits with electrical components near shallow trench isolations and methods for producing such integrated circuits are provided. The method includes forming a trench is a substrate, where the trench has a trench surface. A barrier layer including silicon and germanium is formed overlying the trench surface. A shallow trench isolation is then formed with a core overlying the barrier layer, where the core includes a shallow trench isolation insulator.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: October 4, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Ran Yan, Nicolas Sassiat, Alban Zaka, Kun-Hsien Lin
  • Patent number: 9450180
    Abstract: A method of making a magnetic random access memory (MRAM) device includes depositing a spacer material on an electrode; forming a magnetic tunnel junction (MTJ) on the spacer material that includes a reference layer in contact with the spacer material, a free layer, and a tunnel barrier layer; patterning a hard mask on the free layer; etching the MTJ and the spacer material to transfer a pattern of the hard mask into the MTJ and the spacer material; forming an insulating layer along a sidewall of the hard mask, the MTJ, and the spacer material; disposing an interlayer dielectric (ILD) on and around the hard mask, MTJ, and spacer material; etching through the ILD to form a trench that extends to a surface and sidewall of the hard mask and a sidewall of a portion of the MTJ; and disposing a metal in the trench to form a contact electrode.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: September 20, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Gen P. Lauer, Nathan P. Marchack
  • Patent number: 9443735
    Abstract: There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate having an active region; forming a dielectric layer for gate insulation on the active region; forming a curing layer with a material containing germanium (Ge) on the dielectric layer; heat-treating the curing layer; and removing the curing layer. The germanium-containing material may be silicon germanium (SiGe) or germanium (Ge).
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: September 13, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Soak Kim, Gab Jin Nam, Dong Hwan Kim, Su Hwan Kim, Toshiro Nakanishi, Sung Kweon Baek, Tae Hyun An, Eun Ae Chung
  • Patent number: 9443771
    Abstract: A method of removing RMG sidewall layers, and the resulting device are provided. Embodiments include forming a TiN layer in nFET and pFET RMG trenches; forming an a-Si layer over the TiN layer; implanting O2 vertically in the a-Si layer; removing the a-Si layer and TiN layer from the side surfaces of the RMG trenches followed by the a-Si layer from the bottom surfaces; forming a TiN layer in the RMG trenches; forming a a-Si layer over the TiN layer; implanting O2 vertically in the a-Si layer; removing the a-Si layer and TiN layer from the side surfaces of the RMG trenches, the a-Si layer from the bottom surfaces, and a remainder of the TiN layer from only the nFET RMG trench; forming a Ti layer in the RMG trenches; implanting Al or C in the Ti layer vertically and annealing; and filling the RMG trenches with Al or W.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: September 13, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Yanping Shen, Min-hwa Chi, Ashish Kumar Jha, Haiting Wang
  • Patent number: 9425292
    Abstract: A method for fabricating a field effect transistor device comprises forming a fin on a substrate, forming a first dummy gate stack and a second dummy gate stack over the fin, forming spacers adjacent to the fin, the first dummy gate stack, and the second dummy gate stack, etching to remove portions of the fin and form a first cavity partially defined by the spacers, depositing an insulator material in the first cavity, patterning a mask over the first dummy gate stack and portions of the fin, etching to remove exposed portions of the insulator material, and epitaxially growing a first semiconductor material on exposed portions of the fin.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: August 23, 2016
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Xiuyu Cai, Sanjay C. Mehta, Tenko Yamashita
  • Patent number: 9419072
    Abstract: A semiconductor device and a method of fabricating the same include a semiconductor substrate, a high-k dielectric pattern and a metal-containing pattern sequentially being stacked on the semiconductor substrate, a gate pattern including poly semiconductor and disposed on the metal-containing pattern, and a protective layer disposed on the gate pattern, wherein the protective layer includes oxide, nitride and/or oxynitride of the poly semiconductor.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: August 16, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chongkwang Chang, Youngjoon Moon, Duck-nam Kim, Yeong-Jong Jeong
  • Patent number: 9412868
    Abstract: A method for fabricating a semiconductor device includes forming an isolation feature in a substrate, forming a gate stack over the substrate, forming a source/drain (S/D) recess cavity in the substrate, where the S/D recess cavity is positioned between the gate stack and the isolation feature. The method further includes forming an epitaxial (epi) material in the S/D recess cavity, where the epi material has an upper surface which including a first crystal plane. Additionally, the method includes performing a redistribution process to the epi material in the S/D recess cavity using a chlorine-containing gas, where the first crystal plane is transformed to a second crystal plane after the redistribution.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: August 9, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Ru Lee, Ming-Hua Yu, Tze-Liang Lee, Chii-Horng Li, Pang-Yen Tsai, Lilly Su, Yi-Hung Lin, Yu-Hung Cheng
  • Patent number: 9373702
    Abstract: After formation of a disposable gate structure, a raised active semiconductor region includes a vertical stack, from bottom to top, of an electrical-dopant-doped semiconductor material portion and a carbon-doped semiconductor material portion. A planarization dielectric layer is deposited over the raised active semiconductor region, and the disposable gate structure is replaced with a replacement gate structure. A contact via cavity is formed through the planarization dielectric material layer by an anisotropic etch process that employs a fluorocarbon gas as an etchant. The carbon in the carbon-doped semiconductor material portion retards the anisotropic etch process, and the carbon-doped semiconductor material portion functions as a stopping layer for the anisotropic etch process, thereby making the depth of the contact via cavity less dependent on variations on the thickness of the planarization dielectric layer or pattern factors.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: June 21, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Zhengwen Li, Qing Cao, Kangguo Cheng, Fei Liu, Zhen Zhang
  • Patent number: 9368343
    Abstract: The present invention relates generally to semiconductor devices, and more particularly, to a structure and method of reducing external resistance within fin field effect transistor (finFET) devices. A first spacer and a second spacer may be formed adjacent to a gate which may reduce capacitance in a substantial portion of a epitaxial source-drain region while also permitting a portion of the epitaxial source-drain region to be located close to a channel. By reducing capacitance from the gate on the substantial portion of the epitaxial source-drain region, resistance in the epitaxial source-drain region may be reduced which may result in increased device performance.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: June 14, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Shom S. Ponoth, Raghavasimhan Sreenivasan, Theodorus E. Standaert, Tenko Yamashita