Abstract: A FinFET including a gate stack, a semiconductor fin embedded in the gate stack, a source and a drain disposed is provided. The semiconductor fin extends along a widthwise direction of the gate stack and has a first concave and a second concave exposed at sidewalls of the gate stack respectively. The source and drain are disposed at two opposite sides of the gate stack. The source includes a first portion in contact with and embedded in the first concave. The drain includes a second portion in contact with and embedded in the second concave. The first portion and the second portion are covered by the gate stack.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure having source/drain regions; at least one isolation structure within the source/drain regions in a substrate material; and semiconductor material on a surface of the at least one isolation structure in the source/drain regions.

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin as an initial step in forming a source/drain region. The opening is formed into a parasitic channel region of the fin. Once the opening has been formed, a first semiconductor material is epitaxially grown at the bottom of the opening to a level over the top of the parasitic channel region. A second semiconductor material is epitaxially grown from the top of the first semiconductor material to fill and/or overfill the opening. The second semiconductor material is differently doped from the first semiconductor material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the nanostructures.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

Abstract: The present invention discloses a formation method, comprising: forming a hard mask layer and a photo-lithographic pattern of a fin structure on a the semiconductor substrate; patterning the hard mask layer and the semiconductor substrate to gain the fin structure with a profile of steep sidewalls; forming a protective layer on the sidewall surface of the fin structure; etching the semiconductor substrate located below the fin structure to form isolation structure trenches; performing a modified treatment on the exposed surfaces of the isolation structure trenches to form a modified layer with a certain thickness; removing the protective layer and the modified layer simultaneously; filling a dielectric layer in the isolation structure trenches till to cover the fin structure and then planarizing the dielectric layer; performing a trench etching to the dielectric layer and forming the fin structure and an isolation structure with sloped sidewalls.

Abstract: Disclosed is a method of fabricating a contact in a semiconductor device. The method includes: receiving a semiconductor structure having an opening into which the contact is to be formed; forming a metal layer in the opening; forming a bottom anti-reflective coating (BARC) layer in the opening; performing implanting operations with a dopant on the BARC layer and the metal layer, the performing implanting operations including controlling an implant energy level and controlling an implant dosage level to form a crust layer with a desired minimum depth on top of the BARC layer; removing unwanted metal layer sections using wet etching operations, wherein the crust layer and BARC layer protect remaining metal layer sections under the BARC layer from metal loss during the wet etching operations; removing the crust layer and the BARC layer; and forming the contact in the opening over the remaining metal layer sections.

Abstract: A semiconductor device may include a substrate, a first nanowire, a second nanowire, a first gate insulating layer, a second gate insulating layer, a first metal layer and a second metal layer. The first gate insulating layer may be along a periphery of the first nanowire. The second gate insulating layer may be along a periphery of the second nanowire. The first metal layer may be on a top surface of the first gate insulating layer along the periphery of the first nanowire. The first metal layer may have a first crystal grain size. The second metal layer may be on a top surface of the second gate insulating layer along the periphery of the second nanowire. The second metal layer may have a second crystal grain size different from the first crystal grain size.

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a spacer around the gate structure; and forming a buffer layer adjacent to the gate structure. Preferably, the buffer layer includes a crescent moon shape and the buffer layer includes an inner curve, an outer curve, and a planar surface connecting the inner curve and an outer curve along a top surface of the substrate, in which the planar surface directly contacts the outer curve on an outer sidewall of the spacer.

Abstract: A semiconductor device such as a fin field effect transistor and its method of manufacture are provided. In some embodiments gate spacers are formed over a semiconductor fin, and a first gate stack is formed over the fin. A first sacrificial material with a large selectivity to the gate spacers is formed over the gate stack, and a second sacrificial material with a large selectivity is formed over a source/drain contact plug. Etching processes are utilized to form openings through the first sacrificial material and through the second sacrificial material, and the openings are filled with a conductive material.

Abstract: The present invention provides a new complementary MOSFET structure with localized isolations in silicon substrate to reduce leakages and prevent latch-up. The complementary MOSFET structure comprises a semiconductor wafer substrate with a semiconductor surface, a P type MOSFET comprising a first conductive region, a N type MOSFET comprising a second conductive region, and a cross-shape localized isolation region between the P type MOSFET and the N type MOSFET. Wherein, the cross-shape localized isolation region includes a horizontally extended isolation region below the semiconductor surface, and the horizontally extended isolation region contacts to a bottom side of the first conductive region and a bottom side of the second conductive region.

Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.

Abstract: A semiconductor device includes a gate stack, an epitaxy structure, a first spacer, a second spacer, and a dielectric residue. The gate stack is over a substrate. The epitaxy structure is formed raised above the substrate. The first spacer is on a sidewall of the gate stack. The first spacer and the epitaxy structure define a void therebetween. The second spacer seals the void between the first spacer and the epitaxy structure. The dielectric residue is in the void and has an upper portion and a lower portion under the upper portion. The upper portion of the dielectric residue has a silicon-to-nitrogen atomic ratio higher than a silicon-to-nitrogen atomic ratio of the lower portion of the dielectric residue.

Abstract: A semiconductor component including: a semiconductor substrate; and a semiconductor device provided thereon, the device being a field-effect transistor that includes: a gate insulating film provided on the substrate; a gate electrode provided via the film; and a pair of source-drain regions provided to sandwich the electrode, the substrate including a patterned surface in a portion where the electrode is provided, the patterned surface of the substrate including a raised portion where the film is formed to cover a surface that lies on the same plane as a surface of the pair of source-drain regions, and the electrode is formed on a top surface of the film, and the patterned surface of the substrate including a recessed portion where the film is formed to cover surfaces of a groove formed toward the interior than the surface of the pair of source-drain regions, and the electrode is formed so as to fill the groove provided with the film.

Abstract: A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

Abstract: A method for forming source/drain regions in a semiconductor device and a semiconductor device including source/drain regions formed by the method are disclosed. In an embodiment, a method includes etching a semiconductor fin to form a first recess, the semiconductor fin defining sidewalls and a bottom surface of the first recess, the semiconductor fin extending in a first direction; forming a source/drain region in the first recess, the source/drain region including a single continuous material extending from a bottom surface of the first recess to above a top surface of the semiconductor fin, a precursor gas for forming the source/drain region including phosphine (PH3) and at least one of arsine (AsH3) or monomethylsilane (CH6Si); and forming a gate over the semiconductor fin adjacent the source/drain region, the gate extending in a second direction perpendicular the first direction.

Abstract: A semiconductor device includes a gate structure located on a substrate; and a raised source/drain region adjacent to the gate structure. An interface is between the gate structure and the substrate. The raised source/drain region includes a stressor layer providing strain to a channel under the gate structure; and a silicide layer in the stressor layer. The silicide layer extends from a top surface of the raised source/drain region and ends below the interface by a predetermined depth. The predetermined depth allows the stressor layer to maintain the strain of the channel.

Abstract: A semiconductor device according to the present disclosure includes a channel portion, a gate electrode disposed opposite the channel portion via a gate insulating film, and source/drain regions disposed at both edges of the channel portion. The source/drain regions include semiconductor layers that have a first conductivity type and that are formed inside recessed portions disposed on a base body. Impurity layers having a second conductivity type different from the first conductivity type are formed between the base body and bottom portions of the semiconductor layers.

Abstract: Disclosed herein are apparatuses and methods that include a shallow trench isolation filling structure. An example method includes: etching a semiconductor substrate to form a plurality of pillars and a trench therebetween; providing rinse solution in the trench; adding a plurality of insulating particles into the rinse solution; and removing the rinse solution such that the insulating particles and an air gap remains in the trench.

Abstract: An integrated circuit (IC) structure includes a first cell and a second cell abutting the first cell. The first cell includes a first fin-like field-effect transistor (FinFET). The first FinFET includes a first channel region in a first fin extending along a first direction, and a first gate electrode extending across the first channel region in the first fin along a second direction different from the first direction. The second FinFET includes a second channel region in a second fin aligned with the first fin along the first direction, and a second gate electrode extending across the second channel region in the second fin along the second direction. The second fin has a smaller width than the first fin.

Abstract: An integrated circuit die includes a magnetic tunnel junction as a storage element of a MRAM cell. The integrated circuit die includes a top electrode positioned on the magnetic tunnel junction. The integrated circuit die includes a first sidewall spacer laterally surrounding the top electrode. The first sidewall spacer acts as a mask for patterning the magnetic tunnel junction. The integrated circuit die includes a second sidewalls spacer positioned on a lateral surface of the magnetic tunnel junction.

Abstract: One or more active region structures each protrude vertically out of a substrate in a vertical direction and each extend horizontally in a first horizontal direction. A source/drain component is disposed over the one or more active region structures in the vertical direction. A source/drain contact is disposed over the source/drain component in the vertical direction. The source/drain contact includes a bottom portion and a top portion. A protective liner is disposed on side surfaces of the top portion of the source/drain contact but not on side surfaces of the bottom portion of the source/drain contact.

Abstract: A fin field effect transistor (FinFET) includes a fin extending from a substrate, where the fin includes a lower region, a mid region, and an upper region, the upper region having sidewalls that extend laterally beyond sidewalls of the mid region. The FinFET also includes a gate stack disposed over a channel region of the fin, the gate stack including a gate dielectric, a gate electrode, and a gate spacer on either side of the gate stack. A dielectric material is included that surrounds the lower region and the first interface. A fin spacer is included which is disposed on the sidewalls of the mid region, the fin spacer tapering from a top surface of the dielectric material to the second interface, where the fin spacer is a distinct layer from the gate spacers. The upper region may include epitaxial source/drain material.

Abstract: Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium and boron. The first and second source or drain structures have a resistivity less than or equal to 0.3 mOhm·cm.

Abstract: A semiconductor device includes a semiconductor substrate, a pair of source/drain regions on the semiconductor substrate, and a gate structure on the semiconductor substrate and between the pair of source/drain regions. The gate structure includes a first metal layer and a second metal layer in contact with the first metal layer. A sidewall of the first metal layer and a top surface of the semiconductor substrate form a first included angle, a sidewall of the second metal layer and the top surface of the semiconductor substrate form a second included angle. The second included angle is different from the first included angle.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over the fin structure, an epitaxial region formed in the fin structure and adjacent to the gate structure. The epitaxial region can embed a plurality of clusters of dopants.

Abstract: A method of manufacturing a semiconductor device including: arranging a first and a second gate strip separating in a first distance, wherein each of the first and the second gate strip is a gate terminal of a transistor; depositing a first contact via on the first gate strip; forming a first conductive strip on the first contact via, wherein the first conductive strip and the first gate strip are crisscrossed from top view; arranging a second and a third conductive strip, above the first conductive strip, separating in a second distance, wherein each of the second and the third conductive strip is free from connecting to the first conductive strip, the first and the second conductive strip are crisscrossed from top view. The first distance is twice as the second distance. A length of the first conductive strip is smaller than two and a half times as the first distance.

Abstract: A method for forming a doped layer is disclosed. The doped layer may be used in a NMOS or a silicon germanium application. The doped layer may be created using an n-type halide species in a n-type dopant application, for example.

Abstract: A method of forming a semiconductor structure includes following steps. A first isolation is formed between a pair of active regions. A gate structure is formed on the first isolation structure. The active regions are etched to form recesses with curved top surfaces. The active regions are etched again to change each of the curved top surfaces to be a top surface and a sidewall substantially perpendicular to the top surface. A pair of contacts is formed respectively on the active regions, such that each of the contacts has a bottom surface and a sidewall substantially perpendicular to the bottom surface.

Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.

Abstract: Digital-to-analog converters (DACs) having a multiple-gate (multi-gate) transistor-like structure are disclosed herein. The DAC structures have a similar structure to a transistor (e.g., a MOSFET) and include source and drain regions. However, instead of employing only one gate between the source and drain regions, multiple distinct gates are employed. Each distinct gate can represent a bit for the DAC and can include different gate lengths to enable providing different current values, and thus, unique outputs. Further, N number of inputs can be applied to N number of gates employed by the DAC. The DAC structure may be configured such that the longest gate controls the LSB of the DAC and the shortest gate controls the MSB, or vice versa. In some cases, the multi-gate DAC employs high-injection velocity materials that enable compact design and routing, such as InGaAs, InP, SiGe, and Ge, to provide some examples.

Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. A nanowire transistor may include a channel region including a nanowire above a substrate, a source electrode coupled to a first end of the nanowire through a first etch stop layer, and a drain electrode coupled to a second end of the nanowire through a second etch stop layer. A gate electrode may be above the substrate to control conductivity in at least a portion of the channel region. A first spacer may be above the substrate between the gate electrode and the source electrode, and a second spacer may be above the substrate between the gate electrode and the drain electrode. A gate dielectric layer may be between the channel region and the gate electrode. Other embodiments may be described and/or claimed.

Abstract: Disclosed are optimized contract structures and fabrication techniques thereof. At least one aspect includes a semiconductor die. The semiconductor die includes a substrate and a contact disposed within the substrate. The contact includes a first portion with a first vertical cross-section having a first cross-sectional area. The first vertical cross-section has a first width and a first height. The contact also includes a second portion with a second vertical cross-section having a second cross-sectional area less than the first cross-sectional area. The second vertical cross-section includes a lower portion having the first width and a second height less than the first height, and an upper portion disposed above the lower portion and having a second width less than the first width and having a third height less than the first height.

Abstract: An integrated circuit includes a gate structure over a substrate. The integrated circuit includes a first silicon-containing material structure in a recess. The first silicon-containing material structure includes a first layer below a top surface of the substrate and in direct contact with the substrate. The first silicon-containing material structure includes a second layer over the first layer, wherein an entirety of the second layer is above the top surface of the substrate, a first region of the second layer closer to the gate structure is thinner than a second region of the second layer farther from the gate structure. The first silicon-containing material structure includes a third layer between the first layer and the second layer, wherein at least a portion of the third layer is below the top surface of the substrate.

Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having a first region, a second region, a gate structure on the first region and a dummy gate structure on the second region, and an isolation structure in the semiconductor under the dummy gate structure. The method also includes forming source/drain openings in the semiconductor substrate at two sides of the gate structure. A sidewall surface of the source/drain opening contains an apex angle extending into the semiconductor substrate under the gate structure; and the source/drain opening exposes a sidewall surface of the isolation structure. Further; the method includes forming an initial bulk layer in the source/drain opening; performing a reshaping process to the initial bulk layer to form a bulk layer having an a substantially flat reshaped surface; and forming a protective layer on the bulk layer.

Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

Abstract: A transmission gate structure includes two PMOS transistors in a first active area, two NMOS transistors in a second active area, a first metal zero segment overlying the first active area, a second metal zero segment offset from the first metal zero segment by a distance, a third metal zero segment offset from the second metal zero segment by the distance, a fourth metal zero segment offset from the third metal zero segment by the distance and overlying the second active area. A first conductive segment overlies a first portion of the first active area included in one or both PMOS transistors, and a second conductive segment overlies a second portion of the second active area included in one or both NMOS transistors. The active areas and metal zero segments are perpendicular to the conductive segments, and the PMOS and NMOS transistors are coupled together through the conductive segments.

Abstract: Embodiments of the present disclosure generally relate to a substrate processing chamber, and components thereof, for forming semiconductor devices. The processing chamber comprises a substrate support, and an edge ring is disposed around the substrate support. The edge ring comprises a material selected from the group consisting of quartz, silicon, cross-linked polystyrene and divinylbenzene, polyether ether ketone, Al2O3, and AlN. The material of the edge ring is selected to modulate the properties of hardmask films deposited on substrates in the processing chamber. As such, hardmask films having desired film properties can be deposited in the processing chamber without scaling up the RF power to the chamber.

Abstract: A semiconductor device structure comprises at least one semiconductor fin for a vertical transport field effect transistor, a bottom source/drain layer, and an insulating layer underlying the bottom source/drain layer. A method of forming the structure comprises forming a sacrificial layer within a lower portion of a source/drain region for a vertical transport field effect transistor structure. The sacrificial layer being formed adjacent to at least one semiconductor fin and in contact with a substrate. A source/drain layer is formed within an upper portion of the source/drain region above the sacrificial layer. The sacrificial layer is removed thereby forming a cavity between the substrate and the source/drain layer. An insulating layer is formed within the cavity.

Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and a source region and a drain region, each of which comprise an epi cavity with a bottom surface and a side surface. The transistor further includes an interface layer positioned on at least one of the side surface and the bottom surface of the epi cavity in each of the source/drain regions, wherein the interface layer comprises a non-semiconductor material and an epi semiconductor material positioned on at least an upper surface of the interface layer in the epi cavity in each of the source region and the drain region.

Abstract: A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.

Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure comprising alternately stacked first semiconductor layers and second semiconductor layers over a substrate. A sacrificial gate structure is formed over the fin structure. Spacers are formed on either side of the sacrificial gate structure. The sacrificial gate structure is removed to form a trench between the spacers. The first semiconductor layers are removed from the trench, while leaving the second semiconductor layers suspended in the trench. A self-assembling monolayer is formed on sidewalls of the spacers in the trench. Interfacial layers are formed encircling the suspended second semiconductor layers, respectively. A high-k dielectric layer is deposited at a faster deposition rate on the interfacial layers than on the self-assembling monolayer. A metal gate structure is formed over the high-k dielectric layer.

Abstract: A semiconductor device including an active region extending in a first direction on a substrate; a gate structure intersecting the active region and extending in a second direction on the substrate; and a source/drain region on the active region and at least one side of the gate structure, wherein the source/drain region includes a plurality of first epitaxial layers spaced apart from each other in the first direction, the plurality of first epitaxial layers including first impurities of a first conductivity type; and a second epitaxial layer filling a space between the plurality of first epitaxial layers, the second epitaxial layer including second impurities of the first conductivity type.

Abstract: An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a channel region in a semiconductor body. The gate structure has a first side surface and a second side surface opposite the first side surface. A first source/drain region is positioned adjacent to the first side surface of the gate structure and a second source/drain region is positioned adjacent to the second side surface of the gate structure. The first source/drain region includes a first epitaxial semiconductor layer, and the second source/drain region includes a second epitaxial semiconductor layer. A first top surface of the first epitaxial semiconductor layer is positioned at a first distance from the channel region, a second top surface of the second epitaxial semiconductor layer is positioned at a second distance from the channel region, and the first distance is greater than the second distance.

Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate. The first and second fin structures have respective first and second vertical dimensions that are about equal to each other. The method further includes modifying the first fin structure such that the first vertical dimension of the first fin structure is smaller than the second vertical dimension of the second fin structure and depositing a dielectric layer on the modified first fin structure and the second fin structure. The method further includes forming a polysilicon structure on the dielectric layer and selectively forming a spacer on a sidewall of the polysilicon structure.

Abstract: A structure includes a semiconductor substrate, a source epitaxial structure, a drain epitaxial structure, and a gate stack. The source epitaxial structure is in the semiconductor substrate. The source epitaxial structure has a top surface, and the top surface of the source epitaxial structure comprises hydrogen. The drain epitaxial structure is in the semiconductor substrate. The gate stack is over the semiconductor substrate and between the source epitaxial structure and the drain epitaxial structure.

Abstract: A semiconductor device is formed by a multi-step etching process that produces trench openings in a silicon substrate immediately adjacent transistor gate structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the transistor structure and forms the openings. The openings are bounded by upper surfaces that extend downwardly from the substrate surface and are substantially vertical, and lower surfaces that bulge outwardly from the upper vertical sections and undercut the transistor structure. The openings may be filled with a suitable source/drain material to produce SSD transistors with desirable Idsat characteristics.