Abstract: Disclosed herein are apparatuses and methods that include a shallow trench isolation filling structure. An example method includes: etching a semiconductor substrate to form a plurality of pillars and a trench therebetween; providing rinse solution in the trench; adding a plurality of insulating particles into the rinse solution; and removing the rinse solution such that the insulating particles and an air gap remains in the trench.

Abstract: An integrated circuit (IC) structure includes a first cell and a second cell abutting the first cell. The first cell includes a first fin-like field-effect transistor (FinFET). The first FinFET includes a first channel region in a first fin extending along a first direction, and a first gate electrode extending across the first channel region in the first fin along a second direction different from the first direction. The second FinFET includes a second channel region in a second fin aligned with the first fin along the first direction, and a second gate electrode extending across the second channel region in the second fin along the second direction. The second fin has a smaller width than the first fin.

Abstract: An integrated circuit die includes a magnetic tunnel junction as a storage element of a MRAM cell. The integrated circuit die includes a top electrode positioned on the magnetic tunnel junction. The integrated circuit die includes a first sidewall spacer laterally surrounding the top electrode. The first sidewall spacer acts as a mask for patterning the magnetic tunnel junction. The integrated circuit die includes a second sidewalls spacer positioned on a lateral surface of the magnetic tunnel junction.

Abstract: A fin field effect transistor (FinFET) includes a fin extending from a substrate, where the fin includes a lower region, a mid region, and an upper region, the upper region having sidewalls that extend laterally beyond sidewalls of the mid region. The FinFET also includes a gate stack disposed over a channel region of the fin, the gate stack including a gate dielectric, a gate electrode, and a gate spacer on either side of the gate stack. A dielectric material is included that surrounds the lower region and the first interface. A fin spacer is included which is disposed on the sidewalls of the mid region, the fin spacer tapering from a top surface of the dielectric material to the second interface, where the fin spacer is a distinct layer from the gate spacers. The upper region may include epitaxial source/drain material.

Abstract: One or more active region structures each protrude vertically out of a substrate in a vertical direction and each extend horizontally in a first horizontal direction. A source/drain component is disposed over the one or more active region structures in the vertical direction. A source/drain contact is disposed over the source/drain component in the vertical direction. The source/drain contact includes a bottom portion and a top portion. A protective liner is disposed on side surfaces of the top portion of the source/drain contact but not on side surfaces of the bottom portion of the source/drain contact.

Abstract: Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium and boron. The first and second source or drain structures have a resistivity less than or equal to 0.3 mOhm·cm.

Abstract: A semiconductor device includes a semiconductor substrate, a pair of source/drain regions on the semiconductor substrate, and a gate structure on the semiconductor substrate and between the pair of source/drain regions. The gate structure includes a first metal layer and a second metal layer in contact with the first metal layer. A sidewall of the first metal layer and a top surface of the semiconductor substrate form a first included angle, a sidewall of the second metal layer and the top surface of the semiconductor substrate form a second included angle. The second included angle is different from the first included angle.

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over the fin structure, an epitaxial region formed in the fin structure and adjacent to the gate structure. The epitaxial region can embed a plurality of clusters of dopants.

Abstract: A method of manufacturing a semiconductor device including: arranging a first and a second gate strip separating in a first distance, wherein each of the first and the second gate strip is a gate terminal of a transistor; depositing a first contact via on the first gate strip; forming a first conductive strip on the first contact via, wherein the first conductive strip and the first gate strip are crisscrossed from top view; arranging a second and a third conductive strip, above the first conductive strip, separating in a second distance, wherein each of the second and the third conductive strip is free from connecting to the first conductive strip, the first and the second conductive strip are crisscrossed from top view. The first distance is twice as the second distance. A length of the first conductive strip is smaller than two and a half times as the first distance.

Abstract: A method for forming a doped layer is disclosed. The doped layer may be used in a NMOS or a silicon germanium application. The doped layer may be created using an n-type halide species in a n-type dopant application, for example.

Abstract: A method of forming a semiconductor structure includes following steps. A first isolation is formed between a pair of active regions. A gate structure is formed on the first isolation structure. The active regions are etched to form recesses with curved top surfaces. The active regions are etched again to change each of the curved top surfaces to be a top surface and a sidewall substantially perpendicular to the top surface. A pair of contacts is formed respectively on the active regions, such that each of the contacts has a bottom surface and a sidewall substantially perpendicular to the bottom surface.

Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.

Abstract: Digital-to-analog converters (DACs) having a multiple-gate (multi-gate) transistor-like structure are disclosed herein. The DAC structures have a similar structure to a transistor (e.g., a MOSFET) and include source and drain regions. However, instead of employing only one gate between the source and drain regions, multiple distinct gates are employed. Each distinct gate can represent a bit for the DAC and can include different gate lengths to enable providing different current values, and thus, unique outputs. Further, N number of inputs can be applied to N number of gates employed by the DAC. The DAC structure may be configured such that the longest gate controls the LSB of the DAC and the shortest gate controls the MSB, or vice versa. In some cases, the multi-gate DAC employs high-injection velocity materials that enable compact design and routing, such as InGaAs, InP, SiGe, and Ge, to provide some examples.

Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. A nanowire transistor may include a channel region including a nanowire above a substrate, a source electrode coupled to a first end of the nanowire through a first etch stop layer, and a drain electrode coupled to a second end of the nanowire through a second etch stop layer. A gate electrode may be above the substrate to control conductivity in at least a portion of the channel region. A first spacer may be above the substrate between the gate electrode and the source electrode, and a second spacer may be above the substrate between the gate electrode and the drain electrode. A gate dielectric layer may be between the channel region and the gate electrode. Other embodiments may be described and/or claimed.

Abstract: Disclosed are optimized contract structures and fabrication techniques thereof. At least one aspect includes a semiconductor die. The semiconductor die includes a substrate and a contact disposed within the substrate. The contact includes a first portion with a first vertical cross-section having a first cross-sectional area. The first vertical cross-section has a first width and a first height. The contact also includes a second portion with a second vertical cross-section having a second cross-sectional area less than the first cross-sectional area. The second vertical cross-section includes a lower portion having the first width and a second height less than the first height, and an upper portion disposed above the lower portion and having a second width less than the first width and having a third height less than the first height.

Abstract: An integrated circuit includes a gate structure over a substrate. The integrated circuit includes a first silicon-containing material structure in a recess. The first silicon-containing material structure includes a first layer below a top surface of the substrate and in direct contact with the substrate. The first silicon-containing material structure includes a second layer over the first layer, wherein an entirety of the second layer is above the top surface of the substrate, a first region of the second layer closer to the gate structure is thinner than a second region of the second layer farther from the gate structure. The first silicon-containing material structure includes a third layer between the first layer and the second layer, wherein at least a portion of the third layer is below the top surface of the substrate.

Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having a first region, a second region, a gate structure on the first region and a dummy gate structure on the second region, and an isolation structure in the semiconductor under the dummy gate structure. The method also includes forming source/drain openings in the semiconductor substrate at two sides of the gate structure. A sidewall surface of the source/drain opening contains an apex angle extending into the semiconductor substrate under the gate structure; and the source/drain opening exposes a sidewall surface of the isolation structure. Further; the method includes forming an initial bulk layer in the source/drain opening; performing a reshaping process to the initial bulk layer to form a bulk layer having an a substantially flat reshaped surface; and forming a protective layer on the bulk layer.

Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

Abstract: A transmission gate structure includes two PMOS transistors in a first active area, two NMOS transistors in a second active area, a first metal zero segment overlying the first active area, a second metal zero segment offset from the first metal zero segment by a distance, a third metal zero segment offset from the second metal zero segment by the distance, a fourth metal zero segment offset from the third metal zero segment by the distance and overlying the second active area. A first conductive segment overlies a first portion of the first active area included in one or both PMOS transistors, and a second conductive segment overlies a second portion of the second active area included in one or both NMOS transistors. The active areas and metal zero segments are perpendicular to the conductive segments, and the PMOS and NMOS transistors are coupled together through the conductive segments.

Abstract: A semiconductor device structure comprises at least one semiconductor fin for a vertical transport field effect transistor, a bottom source/drain layer, and an insulating layer underlying the bottom source/drain layer. A method of forming the structure comprises forming a sacrificial layer within a lower portion of a source/drain region for a vertical transport field effect transistor structure. The sacrificial layer being formed adjacent to at least one semiconductor fin and in contact with a substrate. A source/drain layer is formed within an upper portion of the source/drain region above the sacrificial layer. The sacrificial layer is removed thereby forming a cavity between the substrate and the source/drain layer. An insulating layer is formed within the cavity.

Abstract: Embodiments of the present disclosure generally relate to a substrate processing chamber, and components thereof, for forming semiconductor devices. The processing chamber comprises a substrate support, and an edge ring is disposed around the substrate support. The edge ring comprises a material selected from the group consisting of quartz, silicon, cross-linked polystyrene and divinylbenzene, polyether ether ketone, Al2O3, and AlN. The material of the edge ring is selected to modulate the properties of hardmask films deposited on substrates in the processing chamber. As such, hardmask films having desired film properties can be deposited in the processing chamber without scaling up the RF power to the chamber.

Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and a source region and a drain region, each of which comprise an epi cavity with a bottom surface and a side surface. The transistor further includes an interface layer positioned on at least one of the side surface and the bottom surface of the epi cavity in each of the source/drain regions, wherein the interface layer comprises a non-semiconductor material and an epi semiconductor material positioned on at least an upper surface of the interface layer in the epi cavity in each of the source region and the drain region.

Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

Abstract: A device includes a conductive layer including a bottom portion, and a sidewall portion over the bottom portion, wherein the sidewall portion is connected to an end of the bottom portion. An aluminum-containing layer overlaps the bottom portion of the conductive layer, wherein a top surface of the aluminum-containing layer is substantially level with a top edge of the sidewall portion of the conductive layer. An aluminum oxide layer is overlying the aluminum-containing layer. A copper-containing region is over the aluminum oxide layer, and is spaced apart from the aluminum-containing layer by the aluminum oxide layer. The copper-containing region is electrically coupled to the aluminum-containing layer through the top edge of the sidewall portion of the conductive layer.

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure comprising alternately stacked first semiconductor layers and second semiconductor layers over a substrate. A sacrificial gate structure is formed over the fin structure. Spacers are formed on either side of the sacrificial gate structure. The sacrificial gate structure is removed to form a trench between the spacers. The first semiconductor layers are removed from the trench, while leaving the second semiconductor layers suspended in the trench. A self-assembling monolayer is formed on sidewalls of the spacers in the trench. Interfacial layers are formed encircling the suspended second semiconductor layers, respectively. A high-k dielectric layer is deposited at a faster deposition rate on the interfacial layers than on the self-assembling monolayer. A metal gate structure is formed over the high-k dielectric layer.

Abstract: A semiconductor device including an active region extending in a first direction on a substrate; a gate structure intersecting the active region and extending in a second direction on the substrate; and a source/drain region on the active region and at least one side of the gate structure, wherein the source/drain region includes a plurality of first epitaxial layers spaced apart from each other in the first direction, the plurality of first epitaxial layers including first impurities of a first conductivity type; and a second epitaxial layer filling a space between the plurality of first epitaxial layers, the second epitaxial layer including second impurities of the first conductivity type.

Abstract: An embodiment is a method including forming a raised portion of a substrate, forming fins on the raised portion of the substrate, forming an isolation region surrounding the fins, a first portion of the isolation region being on a top surface of the raised portion of the substrate between adjacent fins, forming a gate structure over the fins, and forming source/drain regions on opposing sides of the gate structure, wherein forming the source/drain regions includes epitaxially growing a first epitaxial layer on the fin adjacent the gate structure, etching back the first epitaxial layer, epitaxially growing a second epitaxial layer on the etched first epitaxial layer, and etching back the second epitaxial layer, the etched second epitaxial layer having a non-faceted top surface, the etched first epitaxial layer and the etched second epitaxial layer forming source/drain regions.

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a channel region in a semiconductor body. The gate structure has a first side surface and a second side surface opposite the first side surface. A first source/drain region is positioned adjacent to the first side surface of the gate structure and a second source/drain region is positioned adjacent to the second side surface of the gate structure. The first source/drain region includes a first epitaxial semiconductor layer, and the second source/drain region includes a second epitaxial semiconductor layer. A first top surface of the first epitaxial semiconductor layer is positioned at a first distance from the channel region, a second top surface of the second epitaxial semiconductor layer is positioned at a second distance from the channel region, and the first distance is greater than the second distance.

Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate. The first and second fin structures have respective first and second vertical dimensions that are about equal to each other. The method further includes modifying the first fin structure such that the first vertical dimension of the first fin structure is smaller than the second vertical dimension of the second fin structure and depositing a dielectric layer on the modified first fin structure and the second fin structure. The method further includes forming a polysilicon structure on the dielectric layer and selectively forming a spacer on a sidewall of the polysilicon structure.

Abstract: A structure includes a semiconductor substrate, a source epitaxial structure, a drain epitaxial structure, and a gate stack. The source epitaxial structure is in the semiconductor substrate. The source epitaxial structure has a top surface, and the top surface of the source epitaxial structure comprises hydrogen. The drain epitaxial structure is in the semiconductor substrate. The gate stack is over the semiconductor substrate and between the source epitaxial structure and the drain epitaxial structure.

Abstract: A semiconductor device is formed by a multi-step etching process that produces trench openings in a silicon substrate immediately adjacent transistor gate structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the transistor structure and forms the openings. The openings are bounded by upper surfaces that extend downwardly from the substrate surface and are substantially vertical, and lower surfaces that bulge outwardly from the upper vertical sections and undercut the transistor structure. The openings may be filled with a suitable source/drain material to produce SSD transistors with desirable Idsat characteristics.

Abstract: The present disclosure relates to methods for forming fill materials in trenches having different widths and related structures. A method may include: forming a first fill material in a first and second trench where the second trench has a greater width than the first trench; removing a portion of the first fill material from each trench and forming a second fill material over the first fill material; removing a portion of the first and second fill material within the second trench; and forming a third fill material in the second trench. The structure may include a first fill material in trenches having different widths wherein the upper surfaces of the first fill material in each trench are substantially co-planar. The structure may also include a second fill material on the first fill material in each trench, the second fill material having a substantially equal thickness in each trench.

Abstract: A semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.

Abstract: A method, apparatus, and manufacturing system are disclosed for a fin field effect transistor having a reduced risk of short circuits between a gate and a source/drain contact. In one embodiment, we disclose a semiconductor device including a fin structure comprising a fin body, source/drain regions, and a metal formation disposed above the source/drain regions, wherein the metal formation has a first height; and a gate structure between the source/drain regions, wherein each gate structure comprises spacers in contact with the metal formation, wherein the spacers have a second height less than the first height, a metal plug between the spacers and below the second height, and a T-shaped cap above the metal plug and having the first height.

Abstract: Semiconductor device and fabrication method are provided.

Abstract: A semiconductor device according to an embodiment includes a substrate. A transistor includes a source layer and a drain layer that are provided in a surface region of the substrate and contain impurities. A gate dielectric film is provided on the substrate between the source layer and the drain layer. A gate electrode is provided on the gate dielectric film. A first epitaxial layer is provided on the source layer or the drain layer. A second epitaxial layer is provided on the first epitaxial layer and contains both the impurities and carbon. A contact plug is provided on the second epitaxial layer. A memory cell array is provided above the transistor.

Abstract: A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.

Abstract: A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes providing a base substrate, and forming an interlayer dielectric layer on the base substrate and having an opening exposing surface portions of the base substrate. The method also includes forming a stacked structure on a bottom and sidewall of the opening and on a top of the interlayer dielectric layer. In addition, the method includes removing at least a first portion of the stacked structure from the top of the interlayer dielectric layer. Further, the method includes performing an annealing treatment on the base substrate, and forming a gate structure by filling the opening with a metal layer.

Abstract: Methods, apparatus, and systems for forming a semiconductor substrate comprising a well region containing a first impurity; forming a gate on the semiconductor substrate above the well region; implanting a second impurity, of a type opposite the first impurity, in the well region on each side of the gate and to a depth above a bottom of the well region, to form two second impurity regions each having a first concentration; removing an upper portion of each second impurity region, to yield two source/drain (S/D) cavities above two depletion regions; and growing epitaxially a doped S/D region in each S/D cavity, wherein each S/D region comprises the second impurity having a second concentration greater than the first concentration.

Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. In some embodiments, the semiconductor device includes a fin extending from a substrate and a gate structure disposed over the fin. The gate structure includes a gate dielectric formed over the fin, a gate electrode formed over the gate dielectric, and a sidewall spacer formed along a sidewall of the gate electrode. In some cases, a U-shaped recess is within the fin and adjacent to the gate structure. A first source/drain layer is conformally formed on a surface of the U-shaped recess, where the first source/drain layer extends at least partially under the adjacent gate structure. A second source/drain layer is formed over the first source/drain layer. At least one of the first and second source/drain layers includes silicon arsenide (SiAs).

Abstract: A finFET device includes an n-doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped source or drain extension is disposed. The n-doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer.

Abstract: In a semiconductor device, a source and a drain layers are located in a surface region of a substrate. A source crystal layer is located in a contact region of the source layer to extend to a position higher than the substrate. A drain crystal layer is located in a contact region of the drain layer to extend to a position higher than the substrate. A source contact is located on the source crystal layer. A drain contact is located on the drain crystal layer. A gate width or a gate length extends to a crystal orientation <110> of the substrate. A long side or a major axis of the source crystal layer or a long side or a major axis of the drain crystal layer extends in a direction inclined with respect to the crystal orientation <110> in a planar layout parallel to the surface of the substrate.

Abstract: A semiconductor device includes a cell region that includes a first active region and a second active region extending in a first direction and a separation region between the first active region and the second active region. The cell region has a first width. A first gate structure and a second gate structure are disposed on the cell region, are spaced apart from each other in the first direction, and extend in the second direction. A first metal line and a second metal line are disposed on the cell region, extend in the first direction, and are spaced apart from each other by a first pitch. Each of the first and second metal lines has a second width. A first gate contact electrically connects the first gate structure and the first metal line. At least a portion of the first gate contact overlaps the separation region. A second gate contact electrically connects the second gate structure and the second metal line. At least a portion of the second gate contact overlaps the separation region.

Abstract: VFET devices and techniques for formation thereof having well-defined, sharp source/drain-to-channel junctions are provided. In one aspect, a method of forming a VFET device includes: forming a SiGe layer on a substrate, wherein the SiGe layer as formed on the substrate is undoped; forming an Si layer on the SiGe layer, wherein the Si layer as formed on the SiGe layer is undoped; patterning fins in the Si layer; forming sacrificial spacers along sidewalls of the fins; forming recesses in the SiGe layer between the fins; growing an epitaxial material in the recesses, wherein the epitaxial material grown in the recesses includes a source and drain dopant; annealing the epitaxial material to diffuse the source drain dopant into the SiGe layer under the fins forming bottom source and drains of the VFET device; and removing the sacrificial spacers. A VFET device formed by the method is also provided.

Abstract: In a semiconductor device including a transistor in which an oxide semiconductor layer, a gate insulating layer, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor layer and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive layer and an interlayer insulating layer are stacked to cover the oxide semiconductor layer, the sidewall insulating layers, and the gate electrode layer. Then, parts of the interlayer insulating layer and the conductive layer over the gate electrode layer are removed by a chemical mechanical polishing method, so that a source electrode layer and a drain electrode layer are formed. Before formation of the gate insulating layer, cleaning treatment is performed on the oxide semiconductor layer.

Abstract: A method for making a semiconductor device, including: a) making, on a substrate, a stack comprising a first semiconductor portion able to form an active zone and arranged between two second portions of a material able to be selectively etched relative to the semiconductor of the first portion, b) making, on a part of the stack, outer spacers and a dummy gate, c) etching the second portions such that remaining parts are arranged under the dummy gate, d) partially oxidizing the remaining parts from the outer faces, forming inner spacers, e) removing the dummy gate and non-oxidized parts of the remaining parts arranged under the dummy gate, f) making a gate between the outer spacers and between the inner spacers and covering the channel.

Abstract: Various heterostructures and methods of forming heterostructures are disclosed. A method includes removing portions of a substrate to form a temporary fin protruding above the substrate, forming a dielectric material over the substrate and over the temporary fin, removing the temporary fin to form a trench in the dielectric material, the trench exposing a portion of a first crystalline material of the substrate, forming a template material at least partially in the trench, the template material being a second crystalline material that is lattice mismatched to the first crystalline material, forming a barrier material over the template material, the barrier material being a third crystalline material, forming a device material over the barrier material, the device material being a fourth crystalline material, forming a gate stack over the device material, and forming a first source/drain region and a second source/drain region in the device material.

Abstract: A source/drain region of a semiconductor device is formed using an epitaxial growth process. In an embodiment a first step comprises forming a bulk region of the source/drain region using a first precursor, a second precursor, and an etching precursor. A second step comprises cleaning the bulk region with the etchant along with introducing a shaping dopant to the bulk region in order to modify the crystalline structure of the exposed surfaces. A third step comprises forming a finishing region of the source/drain region using the first precursor, the second precursor, and the etching precursor.