Having Elevated Source Or Drain (e.g., Epitaxially Formed Source Or Drain, Etc.) Patents (Class 438/300)
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Patent number: 9287382Abstract: A semiconductor device and method of forming the same is disclosed. The semiconductor device includes a substrate having first and second device regions. The first device region includes a first source/drain (S/D) region and the second device region includes a plurality of second S/D regions. The semiconductor device further includes a plurality of first recesses in the first S/D region and a plurality of second recesses, one in each of the second S/D regions. The semiconductor device further includes a first epitaxial feature having bottom portions and a top portion, wherein each of the bottom portions is in one of the first recesses and the top portion is over the first S/D region. The semiconductor device further includes a plurality of second epitaxial features each having a bottom portion in one of the second recesses. The second epitaxial features separate from each other.Type: GrantFiled: November 6, 2014Date of Patent: March 15, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Jing Lee, Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee
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Patent number: 9281308Abstract: A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.Type: GrantFiled: July 22, 2014Date of Patent: March 8, 2016Assignee: Globalfoundries Singapore Pte., Ltd.Inventors: Chunshan Yin, Guangyu Huang, Elgin Quek, Jae Gon Lee, Kian Ming Tan
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Patent number: 9281192Abstract: An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a polymer coating, CMP to form a planar surface, then plasma etching to effectuate a planar recessing of the polymer coating. The material can be recessed together with the polymer coating, or subsequently with the recessed polymer coating providing a mask. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The polymer can be a photoresist. The polymer can be provided with suitable adhesion and uniformity for the CMP process through a two-step baking process and by exhausting the baking chamber from below the substrate.Type: GrantFiled: May 13, 2014Date of Patent: March 8, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Kuei Liu, Teng-Chun Tsai, Kao-Feng Liao, Yu-Ting Yen, Yu-Chung Su
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Patent number: 9275995Abstract: An integrated circuit device includes an electrically conductive pattern on a substrate. This electrically conductive pattern may be a gate pattern of a field effect transistor. A first electrically insulating spacer is provided on a sidewall of the electrically conductive pattern. The first electrically insulating spacer includes a first lower spacer and a first upper spacer, which extends on the first lower spacer and has a side surface vertically aligned with a corresponding side surface of the first lower spacer. The first upper spacer has a greater dielectric constant relative to a dielectric constant of the first lower spacer. A pair of parallel channel regions may also be provided, which protrude from a surface of the substrate. The electrically conductive pattern may surround top and side surfaces of the pair of parallel channel regions.Type: GrantFiled: November 17, 2014Date of Patent: March 1, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Jin-Bum Kim, Bon-Young Koo, Seok-Hoon Kim, Chul Kim, Kwan-Heum Lee, Byeong-Chan Lee, Su-Jin Jung
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Patent number: 9263392Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a metal gate thereon and an interlayer dielectric (ILD) layer around the metal gate; removing part of the metal gate to form a recess; and depositing a mask layer in the recess and on the ILD layer while forming a void in the recess.Type: GrantFiled: October 30, 2014Date of Patent: February 16, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Ling Lin, Chih-Sen Huang, Ching-Wen Hung, Jia-Rong Wu, Tsung-Hung Chang, Yi-Hui Lee, Yi-Wei Chen
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Patent number: 9245972Abstract: A method for manufacturing a semiconductor device is provided. A substrate having a first gate and a second gate respectively formed in a first region and a second region is provided. An underlayer is formed on the substrate to cover the first gate in the first region and the second gate in the second region. A patterned mask with a predetermined thickness is formed on the underlayer in the first region. The underlayer corresponding to the second gate in the second region is removed by the patterned mask to expose the second gate, wherein the underlayer corresponding to the first gate in the first region is partially consumed to expose part of the first gate.Type: GrantFiled: September 3, 2013Date of Patent: January 26, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shin-Chi Chen, Chih-Yueh Li, Shui-Yen Lu, Yuan-Chi Pai, Fong-Lung Chuang
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Patent number: 9245923Abstract: Semiconductor devices include a transistor having a gate structure located close to a channel region that comprises a colossal magnetocapacitive material. The gate structure is configured to affect electrical current flow through the channel region between a source and a drain. The colossal magnetocapacitive material optionally may be disposed between two structures, one or both of which may be electrically conductive, magnetic, or both electrically conductive and magnetic. Methods of fabricating semiconductor devices include forming a colossal magnetocapacitive material close to a channel region between a source and a drain of a transistor, and configuring the colossal magnetocapacitive material to exhibit colossal magnetocapacitance for generating an electrical field in the channel region. Methods of affecting current flow through a transistor include causing a colossal magnetocapacitive material to exhibit colossal magnetocapacitance and generate an electrical field in a channel region of a transistor.Type: GrantFiled: September 26, 2013Date of Patent: January 26, 2016Assignee: Micron Technology, Inc.Inventor: Gurtej S. Sandhu
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Patent number: 9246006Abstract: A method for manufacturing a transistor is provided, including amorphization and doping, by one or more localized implantations, of given regions of source and drain blocks based on crystalline semi-conductor material disposed on an insulating layer of a semi-conductor on insulator substrate, the implantations being carried out so as to conserve at a surface of said blocks zones of crystalline semi-conductor material on regions of amorphous semi-conductor material; and recrystallization of at least one portion of said given regions.Type: GrantFiled: August 7, 2014Date of Patent: January 26, 2016Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMICROELECTRONICS SAInventors: Perrine Batude, Frederic Mazen, Benoit Sklenard, Shay Reboh
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Patent number: 9236446Abstract: An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a bottom anti-reflective coating (BARC), baking to induce cross-linking in the BARC, CMP to remove a first portion of the BARC and form a planar surface, then plasma etching to effectuate a planar recessing of the BARC. The plasma etching can have a low selectivity between the BARC and the material being recessed, whereby the BARC and the material are recessed simultaneously. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The method can be particularly effective when an abrasive used during CMP forms ester linkages with the BARC.Type: GrantFiled: March 13, 2014Date of Patent: January 12, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Kuei Liu, Teng-Chun Tsai, Kuo-Yin Lin, Shen-Nan Lee, Yu-Wei Chou, Kuo-Cheng Lien, Chang-Sheng Lin, Chih-Chang Hung, Yung-Cheng Lu
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Patent number: 9218962Abstract: A high order silane having a formula of SinH2n+2, in which n is an integer greater than 3, in combination with a germanium precursor gas is employed to deposit an epitaxial semiconductor alloy material including at least silicon and germanium on a single crystalline surface. The germanium precursor gas effectively reduces the gas phase reaction of the high order silane, thereby improving the thickness uniformity of the deposited epitaxial semiconductor alloy material. The combination of the high order silane and the germanium precursor gas provides a high deposition rate in the Frank-van der Merwe growth mode for deposition of a single crystalline semiconductor alloy material.Type: GrantFiled: October 18, 2013Date of Patent: December 22, 2015Assignees: GLOBALFOUNDRIES INC., MATHESON TRI-GAS, INC.Inventors: Paul D. Brabant, Keith Chung, Hong He, Devendra K. Sadana, Manabu Shinriki
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Patent number: 9209280Abstract: A method of doping a FinFET includes forming a semiconductor fin on a substrate, the substrate having a first device region and a second device region. The semiconductor fin is formed on a surface of the substrate in the second device region and has a top surface and sidewalls. The first device region is covered with a hard mask and the semiconductor fin and the hard mask are exposed to a deposition process to form a dopant-rich layer having an n-type or p-type dopant on the top surface and the sidewalls of the semiconductor fin. The dopant from the dopant-rich layer is diffused into the semiconductor fin by performing an annealing process in which the first device region is free of diffusion of the diffused dopant or another dopant from the hard mask.Type: GrantFiled: February 12, 2015Date of Patent: December 8, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun Hsiung Tsai, Yu-Lien Huang, De-Wei Yu
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Patent number: 9196542Abstract: A method for manufacturing a semiconductor device is provided. A first stack structure and a second stack structure are formed to respectively cover a portion of a first fin structure and a second fin structure. Subsequently, a spacer is respectively formed on the sidewalls of the fin structures through an atomic layer deposition process and the composition of the spacers includes silicon carbon nitride. Afterwards, a interlayer dielectric is formed and etched so as to expose the hard mask layers. A mask layer is formed to cover the second stack structure and a portion of the dielectric layer. Later, the hard mask layer in the first stack structure is removed under the coverage of the mask layer. Then, a dummy layer in the first stack structure is replaced with a conductive layer.Type: GrantFiled: May 22, 2013Date of Patent: November 24, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Jun-Jie Wang, Po-Chao Tsao, Chia-Jui Liang, Shih-Fang Tzou, Chien-Ting Lin
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Patent number: 9190418Abstract: After forming source/drain trenches within a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate, portions of the trenches adjacent channel regions of a semiconductor structure are covered either by sacrificial spacers formed on sidewalls of the trenches or by photoresist layer portions. The sacrificial spacers or photoresist layer portions shield portions of the top semiconductor layer underneath the trenches from subsequent ion implantation for forming junction butting. The ion implantation regions thus are confined only in un-shielded, sublayered portions of the top semiconductor layer that are away from the channel regions of the semiconductor structure. The width of the ion implantation regions are controlled such that the implanted dopants do not diffuse into the channel regions during subsequent thermal cycles so as to suppress the short channel effects.Type: GrantFiled: March 18, 2014Date of Patent: November 17, 2015Assignee: GLOBALFOUNDRIES U.S. 2 LLCInventors: Anthony I. Chou, Murshed M. Chowdhury, Arvind Kumar, Robert R. Robison
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Patent number: 9190327Abstract: A method is provided for forming CMOS transistors. The method includes providing a semiconductor substrate having at least one first region and at least one second region; and forming a first gate in the first region and a second gate in the second region. The method also includes forming first offset spacers made of nitrogen-contained material on side surfaces of the first gate and the second gate; and forming dummy spacers on the first offset spacers in the first region and a dummy spacer material layer covering the second gate and the semiconductor substrate in the second region. Further, the method includes forming SiGe stress layers in the semiconductor substrate at both sides of the first gate; and removing the first offset spacers, the dummy spacers and the dummy spacer material layer. Further, the method also includes forming second offset spacers on the first gate and the second gate.Type: GrantFiled: March 28, 2014Date of Patent: November 17, 2015Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATIONInventors: Yunqi Sui, Gezhi Liu
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Patent number: 9184061Abstract: A method of forming (and apparatus for forming) a zirconium and/or hafnium-containing layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and one or more silicon precursor compounds of the formula Si(OR)4 with one or more zirconium and/or hafnium precursor compounds of the formula M(NR?R?)4, wherein R, R?, and R? are each independently an organic group and M is zirconium or hafnium.Type: GrantFiled: July 27, 2006Date of Patent: November 10, 2015Assignee: Micron Technology, Inc.Inventor: Brian A. Vaartstra
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Patent number: 9178038Abstract: A raised source/drain MOS transistor is formed in a process that utilizes a first sidewall spacer when implanting a semiconductor region to form the heavily-doped source region and the heavily-doped drain region of the transistor, and a second different sidewall spacer when epitaxially growing the raised source region and the raised drain region of the transistor.Type: GrantFiled: January 29, 2015Date of Patent: November 3, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Seung-Chul Song, James W. Blatchford, Kwan-Yong Lim
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Patent number: 9171925Abstract: A device includes a semiconductor substrate, isolation regions in the semiconductor substrate, and a Fin Field-Effect Transistor (FinFET). The FinFET includes a channel region over the semiconductor substrate, a gate dielectric on a top surface and sidewalls of the channel region, a gate electrode over the gate dielectric, a source/drain region, and an additional semiconductor region between the source/drain region and the channel region. The channel region and the additional semiconductor region are formed of different semiconductor materials, and are at substantially level with each other.Type: GrantFiled: April 26, 2012Date of Patent: October 27, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
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Patent number: 9165928Abstract: One illustrative method disclosed herein includes forming gate insulation layers and a first metal layer for NMOS and PMOS devices from the same material, selectively forming a first metal layer only for the PMOS device, and forming different shaped metal silicide regions within the NMOS and PMOS gate cavities. A novel integrated circuit product disclosed herein includes an NMOS transistor with an NMOS gate insulation layer, an NMOS metal silicide having a generally rectangular cross-sectional configuration and an NMOS metal layer positioned on the NMOS metal silicide region. The product also includes a PMOS transistor with the same gate insulation material, a first PMOS metal and a PMOS metal silicide region, wherein the NMOS and PMOS metal silicide regions are comprised of the same metal silicide.Type: GrantFiled: June 14, 2013Date of Patent: October 20, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Ruilong Xie, Kisik Choi
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Patent number: 9153583Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example embodiments, the techniques can be used to implement the contacts of MOS transistors of a CMOS device, where an intermediate III-V semiconductor material layer is provided between the p-type and n-type source/drain regions and their respective contact metals to significantly reduce contact resistance. The intermediate III-V semiconductor material layer may have a small bandgap (e.g., lower than 0.5 eV) and/or otherwise be doped to provide the desired conductivity. The techniques can be used on numerous transistor architectures (e.g., planar, finned, and nanowire transistors), including strained and unstrained channel structures.Type: GrantFiled: December 20, 2011Date of Patent: October 6, 2015Assignee: Intel CorporationInventors: Glenn A. Glass, Anand S. Murthy, Tahir Ghani
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Patent number: 9136383Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; a Ge-containing dielectric layer over the strained material; and a metal layer over the Ge-containing dielectric layer.Type: GrantFiled: August 9, 2012Date of Patent: September 15, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Clement Hsingjen Wann, Ling-Yen Yeh, Chi-Yuan Shih, Yen-Yu Chen
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Patent number: 9136386Abstract: An SOI substrate includes a semiconductor base; a semiconductor layer formed over the semiconductor base; and a buried insulating film which is disposed between the semiconductor base and the semiconductor layer, so as to electrically isolate the semiconductor layer from the semiconductor base, where the buried insulating film contains a nitride film.Type: GrantFiled: January 31, 2012Date of Patent: September 15, 2015Assignee: LAPIS SEMICONDUCTOR CO., LTD.Inventor: Masao Okihara
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Patent number: 9136348Abstract: A semiconductor structure includes a gate structure disposed on a substrate and having an outer spacer, a recess disposed in the substrate and adjacent to the gate structure, a doped epitaxial material filling up the recess, a cap layer including an undoped epitaxial material and disposed on the doped epitaxial material, a lightly doped drain disposed below the cap layer and sandwiched between the doped epitaxial material and the cap layer, and a silicide disposed on the cap layer and covering the doped epitaxial material to cover the cap layer together with the outer spacer without directly contacting the lightly doped drain.Type: GrantFiled: March 12, 2012Date of Patent: September 15, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ming-Te Wei, Shin-Chuan Huang, Yu-Hsiang Hung, Po-Chao Tsao, Chia-Jui Liang, Ming-Tsung Chen, Chia-Wen Liang
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Patent number: 9111898Abstract: A substrate for an integrated circuit includes a device wafer having a raw carrier concentration and an epitaxial layer disposed over the device wafer. The epitaxial layer has a first carrier concentration. The first carrier concentration is higher than the raw carrier concentration.Type: GrantFiled: February 19, 2013Date of Patent: August 18, 2015Assignee: Taiwan Semiconductor Manufacturing Company. Ltd.Inventors: Long-Shih Lin, Fu-Hsiung Yang, Kun-Ming Huang, Ming-Yi Lin, Paul Chu
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Patent number: 9112015Abstract: In a semiconductor device and a method of manufacturing the same, the semiconductor device includes a gate structure crossing an active region of a silicon substrate. Spacers are provided on both sides of the gate structure, respectively. Silicon patterns fill up recessed portions of the silicon substrate and on both sides of the spacers and has a shape protruding higher than a bottom surface of the gate structure, a lower edge of the protruded portion partially makes contact with a top surface of the isolation region, a first side and a second side of each of the silicon patterns, which are opposite to each other in a channel width direction in the gate structure, are inclined toward an inside of the active region. A highly doped impurity region is provided in the silicon patterns and doped with an N type impurity. The semiconductor device represents superior threshold voltage characteristics.Type: GrantFiled: June 19, 2013Date of Patent: August 18, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Keum-Seok Park, Jung-Ho Yoo, Woo-Bin Song, Byeong-Chan Lee
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Patent number: 9105490Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; and a metal layer filling a coated opening of the dielectric layer.Type: GrantFiled: September 27, 2012Date of Patent: August 11, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Li Wang, Ding-Kang Shih, Chin-Hsiang Lin, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 9099565Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes forming laterally adjacent first and second active regions in a semiconductor layer of a silicon-on-insulator (SOI) wafer. A stress inducing layer is formed above the first active region to impart stress thereto. Trench isolation regions are formed bounding the first active region and adjacent portions of the stress inducing layer. The stress inducing layer is removed leaving the trench isolation regions to maintain stress imparted to the first active region.Type: GrantFiled: October 8, 2013Date of Patent: August 4, 2015Assignee: STMICROELECTRONICS, INC.Inventors: Qing Liu, Nicolas Loubet
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Patent number: 9099493Abstract: In a method of fabricating a semiconductor device, a silicon-on-insulator (SOI) substrate is provided. This SOI substrate comprises a buried oxide layer and an ETSOI layer between the buried oxide layer and a surface of the SOI substrate. A dummy gate is formed on the ETSOI. At least two raised source/drain regions are epitaxially formed adjacent to the dummy gate, and a protective cap is formed thereon. An etch process employing at least one acid is used to remove the dummy gate from the ETSOI. A gate dielectric layer is deposited on the protective cap and the ETSOI after removing the dummy gate. A replacement metal gate is then formed on the gate dielectric layer to replace the removed dummy gate, the gate dielectric layer is removed from the protective metal cap, and the protective cap is removed from the raised source/drain regions.Type: GrantFiled: January 21, 2015Date of Patent: August 4, 2015Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Junli Wang, Keith Kwong Hon Wong, Chih-Chao Yang
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Patent number: 9082874Abstract: A semiconductor device includes a gate pattern disposed on a semiconductor substrate, a bulk epitaxial pattern disposed in a recess region formed in the semiconductor substrate at a side of the gate pattern, an insert epitaxial pattern disposed on the bulk epitaxial pattern, and a capping epitaxial pattern disposed on the insert epitaxial pattern. The bulk epitaxial pattern has an upper inclined surface that is a {111} crystal plane, and the insert epitaxial pattern includes a specific element that promotes the growth rate of the insert epitaxial pattern on the upper inclined surface.Type: GrantFiled: December 10, 2014Date of Patent: July 14, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Dong Hyuk Kim, Dongsuk Shin, Hoi Sung Chung, Naein Lee
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Patent number: 9076734Abstract: The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described enable forming an epitaxially grown silicon-containing layer with reduced number of particles on surface of recesses. The described mechanisms also reduce the effect of the residual particles on the epitaxial growth. The mechanisms include controlled etch of a native oxide layer on the surfaces of recesses to reduce creation of particles, and pre-CDE etch to remove particles from surface. The mechanisms also include reduced etch/deposition ratio(s) of initial CDE unit cycle(s) of CDE process to reduce the effect of residual particles on the formation of the epitaxially grown silicon-containing layer. With the application of one or more of the mechanisms, the quality of the epitaxial layer is improved.Type: GrantFiled: October 3, 2014Date of Patent: July 7, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hsiung Tsai, Chien-Chang Su, Tsz-Mei Kwok
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Patent number: 9076867Abstract: The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed.Type: GrantFiled: February 24, 2014Date of Patent: July 7, 2015Assignee: Micron Technology, Inc.Inventors: Arup Bhattacharyya, Leonard Forbes, Paul A. Farrar
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Patent number: 9076857Abstract: Over a semiconductor substrate, a gate insulating film including an interfacial layer, a HfON film, and a HfSiON film is formed. Then, over the HfSiON film, an Al-containing film and a mask layer are formed. Subsequently, the mask layer and the Al-containing film are selectively removed from an n-channel MISFET formation region. Then, a rare-earth-element-containing film is formed over the HfSiON film in the n-channel MISFET formation region and over the mask layer in a p-channel MISFET formation region. Heat treatment is performed to cause a reaction between each of the HfON film and the HfSiON film and the rare-earth-element-containing film in the n-channel MISFET formation region and cause a reaction between each of the HfON film and the HfSiON film and the Al-containing film in the p-channel MISFET formation region. Thereafter, the unreacted rare-earth-element-containing film and the mask layer are removed, and then metal gate electrodes are formed.Type: GrantFiled: January 14, 2013Date of Patent: July 7, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Takahiro Tomimatsu
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Patent number: 9070788Abstract: An circuit supporting substrate includes a transistor and a capacitor. The transistor includes a first semiconductor layer and a gate stack located on the first semiconductor layer. The gate stack includes a metal layer and a first high-k dielectric layer. A gate spacer is located on sidewalls of the gate stack. The first high-k dielectric layer is located between the first semiconductor layer and the metal layer and between the gate spacer and sidewalls of the metal layer. A first silicide region is located on a first source/drain region. A second silicide region is located on a second source/drain region. The capacitor includes a first terminal that comprises a third silicide region located on a portion of the second semiconductor. A second high-k dielectric layer is located on the silicide region. A second terminal comprises a metal layer that is located on the second high-k dielectric layer.Type: GrantFiled: January 30, 2014Date of Patent: June 30, 2015Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Bruce Doris, Ali Khakifirooz, Ghavam G. Shahidi
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Patent number: 9059285Abstract: A method and structure are disclosed for increasing strain in a device, specifically an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device. Embodiments of this invention include an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device having a source region and a drain region, the NFET CMOS including: an n-type doped layer in at least one of the source region and the drain region, wherein the n-type doped layer includes substitutional carbon and has a memorized tensile stress induced by a stress memorization technique (SMT).Type: GrantFiled: February 20, 2013Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Abhishek Dube, Viorel C. Ontalus
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Patent number: 9048253Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of an integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite to the LDD region.Type: GrantFiled: September 27, 2013Date of Patent: June 2, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Feng Nieh, Ming-Huan Tsai, Wei-Han Fan, Yimin Huang, Chun-Fai Cheng, Han-Ting Tsai, Chii-Ming Wu
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Patent number: 9041009Abstract: A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers.Type: GrantFiled: February 19, 2013Date of Patent: May 26, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce B. Doris, Kangguo Cheng, Ali Khakifirooz, Pranita Kerber
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Patent number: 9040380Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure overlying a semiconductor substrate. The fin structure defines a fin axis extending in a longitudinal direction perpendicular to a lateral direction and has two fin sidewalls parallel to the fin axis. The method includes forming gate structures overlying the fin structure and transverse to the fin axis. Further, the method includes growing an epitaxial material on the fin structure and confining growth of the epitaxial material in the lateral direction.Type: GrantFiled: September 11, 2013Date of Patent: May 26, 2015Assignee: GLOBALFOUNDRIES, INC.Inventors: Xiang Hu, Jin Ping Liu, Jill Hildreth, Taejoon Han
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Publication number: 20150140769Abstract: A raised source/drain MOS transistor is formed in a process that utilizes a first sidewall spacer when implanting a semiconductor region to form the heavily-doped source region and the heavily-doped drain region of the transistor, and a second different sidewall spacer when epitaxially growing the raised source region and the raised drain region of the transistor.Type: ApplicationFiled: January 29, 2015Publication date: May 21, 2015Inventors: Seung-Chul Song, James W. Blatchford, Kwan-Yong Lim
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Publication number: 20150140768Abstract: A performance of a semiconductor device is improved. A gate electrode is formed on an SOI substrate via a gate insulating film, and a laminated film including an insulating film IL2 and an insulating film IL3 on the insulating film IL2 is formed on the SOI substrate so as to cover the gate electrode, and then, a sidewall spacer formed of the laminated film is formed on a side wall of the gate electrode by etching back the laminated film. Then, a semiconductor layer is epitaxially grown on a semiconductor layer of the SOI substrate SUB which is not covered with the gate electrode and the sidewall spacer but is exposed, and then, an oxide film is formed on a surface of the semiconductor layer by oxidizing the surface of the semiconductor layer. Then, the insulating film IL3 forming the sidewall spacer is removed.Type: ApplicationFiled: August 26, 2014Publication date: May 21, 2015Inventor: Yoshiki Yamamoto
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Patent number: 9034701Abstract: A device includes a semiconductor substrate. A gate stack on the semiconductor substrate includes a gate dielectric layer and a gate conductor layer. Low-k spacers are adjacent to the gate dielectric layer. Raised source/drain (RSD) regions are adjacent to the low-k spacers. The low-k spacers are embedded in an ILD on the RSD regions.Type: GrantFiled: January 20, 2012Date of Patent: May 19, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Bruce B Doris, Ali Khakifirooz, Douglas C La Tulipe
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Patent number: 9034706Abstract: A method includes etching a semiconductor substrate to form a recess in the semiconductor substrate, and reacting a surface layer of the semiconductor substrate to generate a reacted layer. The surface layer of the semiconductor substrate is in the recess. The reacted layer is then removed. An epitaxy is performed to grow a semiconductor material in the recess.Type: GrantFiled: April 19, 2013Date of Patent: May 19, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Eric Chih-Fang Liu, Tzu-Wei Kao, Ryan Chia-Jen Chen, Chao-Cheng Chen
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Patent number: 9034700Abstract: Integrated circuit devices including Fin field effect transistors (finFETs) and methods of forming those devices are provided. The methods may include forming a fin on a substrate and forming a gate line on the fin. The method may also include forming a first recess in the fin having a first width and a first depth and forming a second recess in the first recess having a second width that is less than the first width and having a second depth that is greater than the first depth. The method may further include forming a source/drain region in the first and second recesses.Type: GrantFiled: September 19, 2014Date of Patent: May 19, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Yeong-Jong Jeong, Jeong-Yun Lee, Shi Ii Quan, Dong-Suk Shin, Si-Hyung Lee
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Patent number: 9029226Abstract: The embodiments of mechanisms for doping lightly doped drain (LDD) regions by driving dopants from highly doped source and drain regions by annealing for finFET devices are provided. The mechanisms overcome the limitation by shadowing effects of ion implantation for advanced finFET devices. The highly doped source and drain regions are formed by epitaxial growing one or more doped silicon-containing materials from recesses formed in the fins. The dopants are then driven into the LDD regions by advanced annealing process, which can achieve targeted dopant levels and profiles in the LDD regions.Type: GrantFiled: June 7, 2013Date of Patent: May 12, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Hsiung Tsai, Tsan-Chun Wang, Su-Hao Liu
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Patent number: 9029227Abstract: A p-channel flash memory is formed with a charge storage stack embedded in a hetero-junction layer in which a raised source/drain is formed. Embodiments include forming a dummy gate stack on a substrate, forming a layer on the substrate by selective epitaxial growth, on each side of the dummy gate stack, forming spacers on the layer, forming raised source/drains, removing the dummy gate stack, forming a cavity between the spacers, and forming a memory gate stack in the cavity. Different embodiments include forming the layer of a narrow bandgap material, a narrow bandgap layer under the spacers and a wide bandgap layer adjacent thereto, or a wide bandgap layer under the spacers, a narrow bandgap layer adjacent thereto, and a wide bandgap layer on the narrow bandgap layer.Type: GrantFiled: March 1, 2011Date of Patent: May 12, 2015Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Eng Huat Toh, Elgin Quek, Ying Keung Leung, Sanford Chu
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Publication number: 20150126012Abstract: A method of forming a semiconductor device includes forming a gate structure including a polysilicon gate and forming a capping spacer on a side surface of the gate structure to prevent parasitic epitaxial growth on the side surface of the polysilicon gate.Type: ApplicationFiled: June 24, 2014Publication date: May 7, 2015Inventors: Yeong-Jong Jeong, Jeong-Yun Lee, Shi Li Quan
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Publication number: 20150118807Abstract: A method of fabricating an integrated circuit device includes forming a first gate structure in a first region of a substrate and a second gate structure in a second region of the substrate. The method includes forming a protective layer overlying the first and the second gate structures. The method includes removing a portion of the protective layer over the second gate structure. The method includes forming features adjacent to the second gate structure. The method further includes forming a spacer over at least a portion of the features adjacent to the second gate structure, wherein the features separate the spacer from the substrate adjacent to the second gate structure. The method includes removing the second portion of the protective layer. Removing the second portion of the protective layer includes forming a protector over the second gate structure; and performing an etching process using a chemical comprising hydrofluoric acid (HF).Type: ApplicationFiled: November 25, 2014Publication date: April 30, 2015Inventors: Ming-Hsi YEH, Hsien-Hsin LIN, Ying-Hsueh CHANG CHIEN, Yi-Fang PAI, Chi-Ming YANG, Chin-Hsiang LIN
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Patent number: 9012999Abstract: A semiconductor device includes a semiconductor substrate having a channel region therein, a gate structure above the channel region, and source and drain regions on opposite sides of the gate structure. A respective contact is on each of the source and drain regions. At least one of the source and drain regions has an inclined upper contact surface with the respective contact. The inclined upper contact surface has at least a 50% greater area than would a corresponding flat contact surface.Type: GrantFiled: August 21, 2012Date of Patent: April 21, 2015Assignee: STMicroelectronics, Inc.Inventors: Qing Liu, Prasanna Khare, Nicolas Loubet
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Patent number: 9006057Abstract: A method of manufacturing a semiconductor device is disclosed. In one embodiment, the method comprises: forming a gate stack on a substrate; etching the substrate on both sides of the gate stack to form C-shaped source/drain grooves; and wet-etching the C-shaped source/drain grooves to form ?-shaped source/drain grooves. With this method, it is possible to effectively increase stress applied to a channel region, to accurately control a depth of the source/drain grooves, and to reduce roughness of side walls and bottom portions of the grooves and thus reduce defects by etching the C-shaped source/drain grooves and then further wet-etching them to form the ?-shaped source/drain grooves.Type: GrantFiled: July 31, 2012Date of Patent: April 14, 2015Assignee: Institute of Microelectronics, Chinese Academy of SciencesInventors: Changliang Qin, Peizhen Hong, Huaxiang Yin
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Patent number: 9006059Abstract: The invention provides a method for fabricating a CMOS transistor and a method for fabricating an array substrate. The method for fabricating a CMOS transistor comprises a step of forming channels, which comprises: depositing an amorphous silicon layer on a substrate, and crystallizing the amorphous silicon layer into a poly-silicon layer; implanting boron atoms into the poly-silicon layer and then forming an N channel region and a P channel region by etching the poly-silicon layer implanted with the boron atoms; forming a photoresist-partially-retained region corresponding to the N channel region and a photoresist-completely-retained region corresponding to the P channel region through a single patterning process; and removing the photoresist in the photoresist-partially-retained-region and retaining a part of the photoresist in the photoresist-completely-retained region using an ashing process, implanting phosphorus atoms through ion implantation thereby forming an N channel and a P channel.Type: GrantFiled: September 6, 2013Date of Patent: April 14, 2015Assignee: Boe Technology Group Co., LtdInventor: Bing Sun
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Patent number: 9006071Abstract: A semiconductor structure and method of manufacturing the same are provided. The semiconductor structure includes a semiconductor substrate having an isolated area comprising a first region and a second region. A first raised RSD region is formed in the first region and a second RSD region is formed in the second region. The first RSD region and second RSD region is separated laterally by a portion of the isolated area. A continuous silicide interconnect structure is formed overlying the first RSD region, the second RSD region and the portion of the isolated area situated between RSD regions. A contact may be formed on the surface of the silicide interconnect.Type: GrantFiled: March 27, 2013Date of Patent: April 14, 2015Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Ghavam G. Shahidi
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Patent number: 8999799Abstract: Embodiments of present invention provide a method of forming silicide contacts of transistors. The method includes forming a first set of epitaxial source/drain regions of a first set of transistors; forming a sacrificial epitaxial layer on top of the first set of epitaxial source/drain regions; forming a second set of epitaxial source/drain regions of a second set of transistors; converting a top portion of the second set of epitaxial source/drain regions into a metal silicide and the sacrificial epitaxial layer into a sacrificial silicide layer in a silicidation process wherein the first set of epitaxial source/drain regions underneath the sacrificial epitaxial layer is not affected by the silicidation process; removing selectively the sacrificial silicide layer; and converting a top portion of the first set of epitaxial source/drain regions into another metal silicide.Type: GrantFiled: August 29, 2013Date of Patent: April 7, 2015Assignee: International Business Machines CorporationInventors: Praneet Adusumilli, Emre Alptekin, Kangguo Cheng, Shom Ponoth, Balasubramanian Pranatharthiharan