Self-aligned Patents (Class 438/299)
  • Patent number: 12046600
    Abstract: Techniques are disclosed for achieving multiple fin dimensions on a single die or semiconductor substrate. In some cases, multiple fin dimensions are achieved by lithographically defining (e.g., hardmasking and patterning) areas to be trimmed using a trim etch process, leaving the remainder of the die unaffected. In some such cases, the trim etch is performed on only the channel regions of the fins, when such channel regions are re-exposed during a replacement gate process. The trim etch may narrow the width of the fins being trimmed (or just the channel region of such fins) by 2-6 nm, for example. Alternatively, or in addition, the trim may reduce the height of the fins. The techniques can include any number of patterning and trimming processes to enable a variety of fin dimensions and/or fin channel dimensions on a given die, which may be useful for integrated circuit and system-on-chip (SOC) applications.
    Type: Grant
    Filed: December 23, 2022
    Date of Patent: July 23, 2024
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy
  • Patent number: 11842927
    Abstract: A semiconductor structure includes a substrate including a first region and a second region, a first channel layer disposed in the first region and a second channel layer disposed in the second region, a first dielectric layer disposed on the first channel layer and a second dielectric layer disposed on the second channel layer, and a first gate electrode disposed on the first dielectric layer and a second gate electrode disposed on the second dielectric layer. The first channel layer in the first region includes Ge compound of a first Ge concentration, the second channel layer in the second region includes Ge compound of a second Ge concentration. The first Ge concentration in the first channel layer is greater than the second Ge concentration in the second channel layer.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Ming Chang, Chung-Liang Cheng, Hsiang-Pi Chang, Hung-Chang Sun, Yao-Sheng Huang, Yu-Wei Lu, Fang-Wei Lee, Ziwei Fang, Huang-Lin Chao
  • Patent number: 11728215
    Abstract: A method includes forming a first gate structure over a substrate, where the first gate structure is surrounded by a first dielectric layer; and forming a mask structure over the first gate structure and over the first dielectric layer, where forming the mask structure includes selectively forming a first capping layer over an upper surface of the first gate structure; and forming a second dielectric layer around the first capping layer. The method further includes forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the mask structure; removing the exposed portion of the mask structure and a portion of the first dielectric layer underlying the exposed portion of the mask structure, thereby forming a recess exposing a source/drain region adjacent to the first gate structure; and filling the recess with a conductive material.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shich-Chang Suen, Kei-Wei Chen, Liang-Guang Chen
  • Patent number: 11688788
    Abstract: An integrated circuit includes a gate structure in contact with a portion of semiconductor material between a source region and a drain region. The gate structure includes gate dielectric and a gate electrode. The gate dielectric includes at least two hybrid stacks of dielectric material. Each hybrid stack includes a layer of low-? dielectric and a layer of high-? dielectric on the layer of low-? dielectric, where the layer of high-? dielectric has a thickness at least two times the thickness of the layer of low-? dielectric. In some cases, the layer of low-? dielectric has a thickness no greater than 1.5 nm. The layer of high-? dielectric may be a composite layer that includes two or more layers of compositionally-distinct materials. The gate structure can be used with any number of transistor configurations but is particularly useful with respect to group III-V transistors.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: June 27, 2023
    Assignee: Intel Corporation
    Inventors: Johann C. Rode, Samuel J. Beach, Nidhi Nidhi, Rahul Ramaswamy, Han Wui Then, Walid Hafez
  • Patent number: 11652154
    Abstract: A method of fabricating a metal gate transistor includes providing a substrate. An interlayer dielectric layer covers the substrate. A dummy gate is embedded in the interlayer dielectric layer. A high-k dielectric layer is disposed between the dummy gate and the substrate. Later, the dummy gate is removed to form a trench, and the high-k dielectric layer is exposed through the trench. After the dummy gate is removed, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. Finally, after the ion implantation process, a metal gate is formed to fill in the trench.
    Type: Grant
    Filed: August 15, 2021
    Date of Patent: May 16, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee
  • Patent number: 11616140
    Abstract: A vertical field effect transistor structure having at least two vertically oriented fins extending from a substrate. The vertical field effect transistor structure further includes a first source/drain region disposed in the substrate between the two vertically oriented fins and under each of the fins. The outer ends of the first source/drain region are in contact with outer ends of the fins. A portion of the first source/drain region extends beyond the fins.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: March 28, 2023
    Assignee: International Business Machines Corporation
    Inventors: Heng Wu, Gen Tsutsui, Lan Yu, Ruilong Xie
  • Patent number: 11610805
    Abstract: A method includes, through a backside of a substrate, removing a portion of a gate structure to form a trench that isolates the gate structure in two portions. The method further includes depositing a sacrificial material within the trench and conformally along sidewalls of the trench, filling a remainder of the trench with a first dielectric material, partially removing the sacrificial material to leave an opening between the first dielectric material and the gate structure, and filling the opening with a work-function metal.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: March 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wang-Chun Huang, Yu-Xuan Huang, Hou-Yu Chen, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11569361
    Abstract: An embodiment includes a method of forming a semiconductor device and the resulting device. The method may include forming a source/drain on an exposed portion of a semiconductor layer of a layered nanosheet. The method may include forming a sacrificial material on the source/drain. The method may include forming a dielectric layer covering the sacrificial material. The method may include replacing the sacrificial material with a contact liner. The semiconductor device may include a first gate nanosheet stack and second gate nanosheet stack. The semiconductor device may include a first source/drain in contact with the first nanosheet stack and a second source/drain in contact with the second nanosheet stack. The semiconductor device may include a source/drain dielectric located between the first source/drain and the second source/drain. The semiconductor device may include a contact liner in contact with the first source/drain, the second source/drain and the source/drain dielectric.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: January 31, 2023
    Assignee: International Business Machines Corporation
    Inventors: Julien Frougier, Ruilong Xie, Kangguo Cheng, Chanro Park
  • Patent number: 11515430
    Abstract: A tilted nanowire structure is provided which has an increased gate length as compared with a horizontally oriented semiconductor nanowire at the same pitch. Such a structure avoids complexity required for vertical transistors and can be fabricated on a bulk semiconductor substrate without significantly changing/modifying standard transistor fabrication processing.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: November 29, 2022
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Kangguo Cheng, Alexander Reznicek, Karthik Balakrishnan
  • Patent number: 11437472
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: September 6, 2022
    Assignee: Intel Corporation
    Inventors: Siddharth Chouksey, Glenn Glass, Anand Murthy, Harold Kennel, Jack T. Kavalieros, Tahir Ghani, Ashish Agrawal, Seung Hoon Sung
  • Patent number: 11430745
    Abstract: A method of forming a semiconductor structure includes forming first semiconductor devices over a first substrate, forming a first dielectric material layer over the first semiconductor devices, forming vertical recesses in the first dielectric material layer, such that each of the vertical recesses vertically extends from a topmost surface of the first dielectric material layer toward the first substrate, forming silicon nitride material portions in each of the vertical recesses; and locally irradiating a second subset of the silicon nitride material portions with a laser beam.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: August 30, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Chen Wu, Peter Rabkin, Yangyin Chen, Masaaki Higashitani
  • Patent number: 11380774
    Abstract: A method includes forming a dummy gate stack, forming a dielectric layer, with the dummy gate stack located in the dielectric layer, removing the dummy gate stack to form a opening in the dielectric layer, forming a metal layer extending into the opening, and etching back the metal layer. The remaining portions of the metal layer in the opening have edges lower than a top surface of the dielectric layer. A conductive layer is selectively deposited in the opening. The conductive layer is over the metal layer, and the metal layer and the conductive layer in combination form a replacement gate.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: July 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Peng-Soon Lim, Cheng-Lung Hung, Mao-Lin Huang, Weng Chang
  • Patent number: 11315829
    Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jyh-Nan Lin, Chia-Yu Wu, Kai-Shiung Hsu, Ding-I Liu
  • Patent number: 11295969
    Abstract: A computer-implemented method for measuring a parameter of a semiconductor. A non-limiting example of the computer-implemented method includes receiving, using a processor, a raw signal from a first tool representing a measured parameter of a semiconductor device. The method also receives, using the processor, data on the measured parameter from a second tool, and calculates, using the processor, the measured parameter based on the data received from the second tool and on a constraint based on the raw signal from the first tool.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: April 5, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gangadhara Raja Muthinti, Matthew Sendelbach, Roy Koret, Aron Cepler, Wei Ti Lee
  • Patent number: 11189531
    Abstract: A method includes forming a first dummy gate and a second dummy gate over a fin that protrudes above a substrate; replacing the first dummy gate and the second dummy gate with a first metal gate and a second metal gate, respectively; forming a dielectric cut pattern between the first and the second metal gates, the dielectric cut pattern extending further from the substrate than the first and the second metal gates; forming a patterned mask layer over the first metal gate, the second metal gate, and the dielectric cut pattern, an opening in the patterned mask layer exposing a portion of the first metal gate, a portion of the second metal gate, and a portion of the dielectric cut pattern underlying the opening; filling the opening with a first electrically conductive material; and recessing the first electrically conductive material below an upper surface of the dielectric cut pattern.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lin-Yu Huang, Sheng-Tsung Wang, Chia-Hao Chang, Tien-Lu Lin, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11056588
    Abstract: A method for fabricating a vertical transistor device includes forming a plurality of fins on a substrate. The method further includes forming an interlevel dielectric layer on the substrate and sidewalls of each of the fins. The method further includes selectively removing the interlevel dielectric layer between adjacent fins. The method further includes laterally recessing a portion of the substrate between the adjacent fins to form a bottom source/drain cavity exposing a bottom portion of each fin and extending beyond each fin. The method further includes epitaxially growing an epitaxial growth material from the substrate and filling the bottom source/drain cavity.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: July 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Heng Wu, Gen Tsutsui, Lan Yu, Ruilong Xie
  • Patent number: 11049722
    Abstract: Methods of modifying the threshold voltage of metal oxide stacks are discussed. These methods utilize materials which provide larger shifts in threshold voltage while also being annealed at lower temperatures.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: June 29, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Siddarth Krishnan, Rajesh Sathiyanarayanan, Atashi Basu, Paul F. Ma
  • Patent number: 11038009
    Abstract: A shadow mask used for OLED evaporation and a manufacturing method therefor, and an OLED panel manufacturing method. The shadow mask used for OLED evaporation includes: a semiconductor substrate including a front surface and a back surface opposite thereto, a recess penetrating the front surface and the back surface being provided in the semiconductor substrate; and a grid film layer provided on the front surface of the semiconductor substrate. A number of openings arranged in an array are provided in the grid film layer. Each of the openings has an upper portion and a lower portion. A width of the upper portion is greater than a width of the lower portion. The recess exposes the number of openings in the grid film layer and the grid film layer between adjacent openings.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: June 15, 2021
    Assignee: SEEYA OPTRONICS CO., LTD.
    Inventors: Yuhan Ju, Tieer Gu, Jie Kong
  • Patent number: 11024540
    Abstract: A method includes forming a first gate structure over a substrate, where the first gate structure is surrounded by a first dielectric layer; and forming a mask structure over the first gate structure and over the first dielectric layer, where forming the mask structure includes selectively forming a first capping layer over an upper surface of the first gate structure; and forming a second dielectric layer around the first capping layer. The method further includes forming a patterned dielectric layer over the mask structure, the patterned dielectric layer exposing a portion of the mask structure; removing the exposed portion of the mask structure and a portion of the first dielectric layer underlying the exposed portion of the mask structure, thereby forming a recess exposing a source/drain region adjacent to the first gate structure; and filling the recess with a conductive material.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shich-Chang Suen, Kei-Wei Chen, Liang-Guang Chen
  • Patent number: 10991630
    Abstract: In an embodiment, a method includes: forming a first gate stack and a second gate stack on a fin; etching the fin to form a recess in the fin between the first gate stack and the second gate stack; forming an epitaxial source/drain region in the recess, the forming including: forming a first layer lining sides and a bottom of the recess by dispensing silane, dichlorosilane, trichlorosilane, and hydrochloric acid in the recess; and after forming the first layer, forming a second layer on the first layer by dispensing the silane, dichlorosilane, trichlorosilane, and hydrochloric acid in the recess, where each of the silane, dichlorosilane, trichlorosilane, and hydrochloric acid are dispensed at a first flow rate when forming the first layer and at a second flow rate when forming the second layer.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: April 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Ching Lin, Chien-Chih Lin, Feng-Ching Chu, Tuoh Bin Ng
  • Patent number: 10903108
    Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active tin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: January 26, 2021
    Inventors: Sunguk Jang, Seokhoon Kim, Seung Hun Lee, Yang Xu, Jeongho Yoo, Jongryeol Yoo, Youngdae Cho
  • Patent number: 10868131
    Abstract: A method for forming a gaseous spacer in a semiconductor device and a semiconductor device including the gaseous spacer are disclosed. In an embodiment, the method may include forming a gate stack over a substrate, depositing a first gate spacer on sidewalls of the gate stack, epitaxially growing source/drain regions on opposite sides of the gate stack, and depositing a second gate spacer over the first gate spacer to form a gaseous spacer below the second gate spacer. The gaseous spacer may be disposed laterally between the source/drain regions and the gate stack.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Hao Yeh, Ching Yu Huang
  • Patent number: 10854582
    Abstract: Disclosed is a light-emitting module including: a first insulation film having light transmissive property; a conductor layer provided on the first insulation film; a second insulation film disposed to face the first insulation film; a plurality of light-emitting elements interposed between the first insulation film and the second insulation film and have one surface on which a pair of electrodes connected to the conductor layer are provided; and a board that is connected to the first insulation film and has a circuit connected to the conductor layer.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: December 1, 2020
    Assignee: Toshiba Hokuto Electronics Corporation
    Inventor: Keiichi Maki
  • Patent number: 10833161
    Abstract: A semiconductor device includes: (i) a substrate; (ii) a first elongated semiconductor structure extending in a first horizontal direction along the substrate and protruding vertically above the substrate, wherein a first set of source/drain regions are formed on the first semiconductor structure; (iii) a second elongated semiconductor structure extending along the substrate in parallel to the first semiconductor structure and protruding vertically above the substrate, wherein a second set of source/drain regions are formed on the second semiconductor structure; and (iv) a first set of source/drain contacts formed on the first set of source/drain regions, wherein a first source/drain contact of the first set of source/drain contacts includes: (a) a vertically extending contact portion formed directly above a first source/drain region of the first set of source/drain regions, and (b) a via landing portion protruding horizontally from the vertically extending contact portion in a direction towards the second se
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: November 10, 2020
    Assignees: IMEC VZW, GLOBALFOUNDRIES INC.
    Inventors: Syed Muhammad Yasser Sherazi, Julien Ryckaert, Juergen Boemmels, Guillaume Bouche
  • Patent number: 10818770
    Abstract: Method for producing field-effect transistor including source electrode and drain electrode, gate electrode, active layer, and gate insulating layer, the method including etching the gate insulating layer, wherein the gate insulating layer is metal oxide including A-element and at least one selected from B-element and C-element, the A-element is at least one selected from Sc, Y, Ln (lanthanoid), Sb, Bi, and Te, the B-element is at least one selected from Ga, Ti, Zr, and Hf, the C-element is at least one selected from Group 2 elements in periodic table, etching solution A is used when at least one selected from the source electrode and the drain electrode, the gate electrode, and the active layer is formed, and etching solution B that is etching solution having same type as the etching solution A is used when the gate insulating layer is etched.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: October 27, 2020
    Assignee: Ricoh Company, Ltd.
    Inventors: Minehide Kusayanagi, Naoyuki Ueda, Yuki Nakamura, Yukiko Abe, Shinji Matsumoto, Yuji Sone, Ryoichi Saotome, Sadanori Arae
  • Patent number: 10784363
    Abstract: Various methods and structures for fabricating a contact for a semiconductor FET or FinFET device. A semiconductor FET structure includes a substrate, a source/drain region layer and source/drain contact. First and second gate spacers are adjacent respective first and second opposing sides of the source/drain contact. The source/drain contact is disposed directly on and contacting the entire source/drain region layer, and at a vertical level thereabove, the source/drain contact being recessed to a limited horizontal area continuing vertically upwards from the vertical level. The limited horizontal area horizontally extending along less than a full horizontal length of a vertical sidewall of the first and second gate spacers, and less than fully covering the source/drain region layer. A method uses a reverse contact mask to form a shape of the source/drain contact into an inverted “T” shape.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 10777420
    Abstract: A material layer having recesses is formed on a substrate including a high pattern density area and a low pattern density area. A first dielectric layer and a second dielectric layer are sequentially formed to cover the material layer, wherein a top surface of the first dielectric layer in the high pattern density area is higher than a top surface of the first dielectric layer in the low pattern density area, thereby a thickness of the second dielectric layer in the low pattern density area being thicker than a thickness of the second dielectric layer in the high pattern density area. An etching back process is performed to remove the second dielectric layer and the first dielectric layer, wherein the etching rate of the etching back process to the second dielectric layer is lower than the etching rate of the etching back process to the first dielectric layer.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: September 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuan-Ying Lai, Chang-Mao Wang, Hsin-Yu Hsieh
  • Patent number: 10727342
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kun-Mu Li, Tsz-Mei Kwok, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
  • Patent number: 10714590
    Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing at least one fin on a semiconductor substrate; forming a stacked channel layer having at least one sacrificial layer on the fin and a channel layer on the sacrificial layer; forming a dummy gate structure on the stacked channel layer; forming openings in the stacked channel layer at both sides of the dummy gate structure; removing portions of the sacrificial layer under the dummy gate structure to form grooves on sidewall surfaces of the openings; and forming a protective layer in the grooves.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: July 14, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) Corporation
    Inventor: Fei Zhou
  • Patent number: 10707316
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a dielectric layer over the substrate, a first metal gate structure in the dielectric layer and having a first width and a second metal gate structure in the dielectric layer and having a second width. The first metal gate structure includes a first metal electrode, and the second metal gate structure includes a second metal electrode. The second metal electrode includes a first conductive portion having a third width and a second conductive portion over the first conductive portion and having a fourth width. The fourth width is greater than the third width. The semiconductor device structure also includes two first source/drain portions at opposite sides of the first metal gate structure, and two second source/drain portions at opposite sides of the second metal gate structure.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ching Huang, Tsung-Yu Chiang
  • Patent number: 10600693
    Abstract: A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: March 24, 2020
    Assignee: Tessera, Inc.
    Inventor: Kangguo Cheng
  • Patent number: 10573645
    Abstract: A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: February 25, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Young Bae Kim, Kwang Il Kim, Jun Hyun Kim, In Sik Jung, Jae Hyung Jang, Jin Yeong Son
  • Patent number: 10535666
    Abstract: Integrated circuit devices are provided. An integrated circuit device includes a substrate having first and second fin-shaped Field Effect Transistor (FinFET) bodies protruding from the substrate. The first and second FinFET bodies have different respective first and second shapes in a first region and a second region, respectively, of the integrated circuit device.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: January 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-yup Chung
  • Patent number: 10522422
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on the sidewall of the gate stack structure, and the gate spacers include a top portion and a bottom portion adjoined to the top portion, and the bottom portion slopes to a top surface of the substrate. The semiconductor device structure further includes an epitaxial structure formed adjacent to the gate spacers, and the epitaxial structure is formed below the gate spacers.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yung-Tsun Liu
  • Patent number: 10446662
    Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: October 15, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih Wei Bih, Han-Wen Liao, Xuan-You Yan, Yen-Yu Chen, Chun-Chih Lin
  • Patent number: 10446586
    Abstract: Disclosed are a pixel unit, an array substrate and a manufacturing method therefor, a display panel and a display device. At least two step portions adjacent to each other in an upward direction are provided at at least one of a first side of a drain electrode close to a display region and a second side of the drain electrode away from the display region, such that a pixel electrode is lapped onto the drain electrode gently.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: October 15, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Xiao Wang
  • Patent number: 10381491
    Abstract: A semiconductor device according to an embodiment includes a first electrode; a second electrode; a silicon carbide layer disposed between the first electrode and the second electrode; an n-type silicon carbide region disposed in the silicon carbide layer and having a first nitrogen concentration; a first p-type silicon carbide region disposed in the silicon carbide layer between the n-type silicon carbide region and the first electrode and having a second nitrogen concentration higher than the first nitrogen concentration; and a second p-type silicon carbide region disposed in the silicon carbide layer between the first p-type silicon carbide region and the first electrode, having a third nitrogen concentration higher than the second nitrogen concentration, and having a p-type impurity concentration higher than that of the first p-type silicon carbide region.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: August 13, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tatsuo Shimizu
  • Patent number: 10355017
    Abstract: A CMOS device includes a p-type field effect transistor containing p-doped active regions, an n-type field effect transistor containing n-doped active regions, a silicon oxide layer overlying the n-type field effect transistor and not overlying the p-type field effect transistor, boron-doped epitaxial pillar structures contacting a top surface of, and epitaxially aligned to, a respective one of the p-doped active regions, first active region contact via structures contacting a top surface of a respective one of the boron-doped epitaxial pillar structures, and second active region contact via structures contacting a top surface of a respective one of the n-doped active regions.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: July 16, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hiroshi Nakatsuji, Kiyokazu Shishido, Hiroyuki Ogawa
  • Patent number: 10345698
    Abstract: A method for fabricating a semiconductor device includes forming a pellicle including an amorphous carbon layer, attaching the pellicle onto a reticle, and forming a photoresist pattern by utilizing EUV light transmitted through the pellicle and reflected by the reticle. The forming the pellicle includes forming a first dielectric layer on a first side of the substrate, forming the amorphous carbon layer on the first dielectric layer, forming a second dielectric layer on a second side of the substrate opposite to the first side of the substrate, etching the second dielectric layer overlapping the first region of the substrate to form a mask pattern, and forming a support including the second region of the substrate and the remaining part of the first dielectric layer. The forming the support includes etching the first region of the substrate and the first dielectric layer on the first region.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: July 9, 2019
    Assignees: Samsung Electronics Co., Ltd., Research & Business Foundation Sungyunkwan University
    Inventors: Ji Beom Yoo, Sung Won Kwon, Dong Wook Shin, Mun Ja Kim, Jin Su Kim, Hwan Chul Jeon
  • Patent number: 10332796
    Abstract: A semiconductor device is provided that includes a first plurality of fin structures having a first width in a first region of a substrate, and a second plurality of fin structures having a second width in a second region of the substrate, the second width being less than the first width. A first gate structure is formed on the first plurality of fin structures including a first high-k gate dielectric that is in direct contact with a channel region of the first plurality of fin structures and a first gate conductor. A second gate structure is formed on the second plurality of fin structures including a high voltage gate dielectric that is in direct contact with a channel region of the second plurality of fin structures, a second high-k gate dielectric and a second gate conductor.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10304934
    Abstract: The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lukas Czornomaz, Veeresh V. Deshpande, Vladimir Djara
  • Patent number: 10304683
    Abstract: By decoupling the formation of a metal silicide in the gate electrode structure and the raised drain and source regions, superior flexibility in designing transistor elements and managing overall process flow may be achieved. To this end, the metal silicide in the gate electrode structures may be formed prior to actually patterning the gate electrode structures, while, also during this process sequence, a mask material may be applied for reliably covering any device regions in which a silicidation is not required. Consequently, superior gate conductivity may be accomplished, without increasing the risk of silicide penetration into the channel region of sophisticated fully depleted SOI transistors.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: May 28, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Elliot John Smith
  • Patent number: 10256302
    Abstract: A vertical transistor has a first air-gap spacer between a gate and a bottom source/drain region, and a second air-gap spacer between the gate and the contact to the bottom source/drain region. A dielectric layer disposed between the gate and the contact to the top source/drain decreases parasitic capacitance and inhibits electrical shorting.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Tak H. Ning
  • Patent number: 10141190
    Abstract: In a manufacturing method of a semiconductor device according to an embodiment, an oxide film is formed on a semiconductor layer containing an impurity. A heat treatment is performed on the semiconductor layer to diffuse part of the impurity into the oxide film with hydrogen plasma treatment on the oxide film or with ultraviolet irradiation on the oxide film. After the heat treatment, the oxide film is removed.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: November 27, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Tatsunori Isogai
  • Patent number: 10128110
    Abstract: Embodiments of the present disclosure generally relate to methods for forming a doped silicon epitaxial layer on semiconductor devices at increased pressure and reduced temperature. In one embodiment, the method includes heating a substrate disposed within a processing chamber to a temperature of about 550 degrees Celsius to about 800 degrees Celsius, introducing into the processing chamber a silicon source comprising trichlorosilane (TCS), a phosphorus source, and a gas comprising a halogen, and depositing a silicon containing epitaxial layer comprising phosphorus on the substrate, the silicon containing epitaxial layer having a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, wherein the silicon containing epitaxial layer is deposited at a chamber pressure of about 150 Torr or greater.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: November 13, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Abhishek Dube, Xuebin Li, Yi-Chiau Huang, Hua Chung, Schubert S. Chu
  • Patent number: 10121852
    Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie, Derrick Liu, Soon-Cheon Seo, Stuart A. Sieg
  • Patent number: 10121853
    Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie, Derrick Liu, Soon-Cheon Seo, Stuart A. Sieg
  • Patent number: 10014386
    Abstract: There is provided a method for manufacturing a transistor including a gate above an underlying layer of a semiconductor material and including at least one first flank and one second flank, a gate foot formed in the underlying layer, a peripheral portion of the underlying layer surrounding the gate foot, and spacers covering at least partially the first and second flanks so as to not cover the gate foot; the method including forming the underlying layer by partially removing the semiconductor material around the gate to form the gate foot and the peripheral portion; then forming a dielectric layer for forming spacers by a deposition to cover both the first and second flanks, the gate foot, and an upper surface of the peripheral portion; and then partially removing the dielectric layer so as to expose the upper surface and so as to not expose the first and second flanks.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: July 3, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Christian Arvet
  • Patent number: 10008569
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a gate structure is formed on the substrate, a recess is formed adjacent to the gate structure, a buffer layer is formed in the recess, and an epitaxial layer is formed on the buffer layer. Preferably, the buffer layer includes a crescent moon shape.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: June 26, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq
  • Patent number: 9966309
    Abstract: A method includes forming a metallic layer over a Metal-Oxide-Semiconductor (MOS) device, forming reverse memory posts over the metallic layer, and etching the metallic layer using the reverse memory posts as an etching mask. The remaining portions of the metallic layer include a gate contact plug and a source/drain contact plug. The reverse memory posts are then removed. After the gate contact plug and the source/drain contact plug are formed, an Inter-Level Dielectric (ILD) is formed to surround the gate contact plug and the source/drain contact plug.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: May 8, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yuan Ting, Jyu-Horng Shieh