Self-aligned Patents (Class 438/299)
  • Patent number: 10903108
    Abstract: Semiconductor devices and methods of forming the same are provided. The methods may implanting dopants into a substrate to form a preliminary impurity region and heating the substrate to convert the preliminary impurity region into an impurity region. Heating the substrate may be performed at an ambient temperature of from about 800° C. to about 950° C. for from about 20 min to about 50 min. The method may also include forming first and second trenches in the impurity region to define an active tin and forming a first isolation layer and a second isolation layer in the first and second trenches, respectively. The first and second isolation layers may expose opposing sides of the active fin. The method may further include forming a gate insulation layer extending on the opposing sides and an upper surface of the active fin and forming a gate electrode traversing the active fin.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: January 26, 2021
    Inventors: Sunguk Jang, Seokhoon Kim, Seung Hun Lee, Yang Xu, Jeongho Yoo, Jongryeol Yoo, Youngdae Cho
  • Patent number: 10868131
    Abstract: A method for forming a gaseous spacer in a semiconductor device and a semiconductor device including the gaseous spacer are disclosed. In an embodiment, the method may include forming a gate stack over a substrate, depositing a first gate spacer on sidewalls of the gate stack, epitaxially growing source/drain regions on opposite sides of the gate stack, and depositing a second gate spacer over the first gate spacer to form a gaseous spacer below the second gate spacer. The gaseous spacer may be disposed laterally between the source/drain regions and the gate stack.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Hao Yeh, Ching Yu Huang
  • Patent number: 10854582
    Abstract: Disclosed is a light-emitting module including: a first insulation film having light transmissive property; a conductor layer provided on the first insulation film; a second insulation film disposed to face the first insulation film; a plurality of light-emitting elements interposed between the first insulation film and the second insulation film and have one surface on which a pair of electrodes connected to the conductor layer are provided; and a board that is connected to the first insulation film and has a circuit connected to the conductor layer.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: December 1, 2020
    Assignee: Toshiba Hokuto Electronics Corporation
    Inventor: Keiichi Maki
  • Patent number: 10833161
    Abstract: A semiconductor device includes: (i) a substrate; (ii) a first elongated semiconductor structure extending in a first horizontal direction along the substrate and protruding vertically above the substrate, wherein a first set of source/drain regions are formed on the first semiconductor structure; (iii) a second elongated semiconductor structure extending along the substrate in parallel to the first semiconductor structure and protruding vertically above the substrate, wherein a second set of source/drain regions are formed on the second semiconductor structure; and (iv) a first set of source/drain contacts formed on the first set of source/drain regions, wherein a first source/drain contact of the first set of source/drain contacts includes: (a) a vertically extending contact portion formed directly above a first source/drain region of the first set of source/drain regions, and (b) a via landing portion protruding horizontally from the vertically extending contact portion in a direction towards the second se
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: November 10, 2020
    Assignees: IMEC VZW, GLOBALFOUNDRIES INC.
    Inventors: Syed Muhammad Yasser Sherazi, Julien Ryckaert, Juergen Boemmels, Guillaume Bouche
  • Patent number: 10818770
    Abstract: Method for producing field-effect transistor including source electrode and drain electrode, gate electrode, active layer, and gate insulating layer, the method including etching the gate insulating layer, wherein the gate insulating layer is metal oxide including A-element and at least one selected from B-element and C-element, the A-element is at least one selected from Sc, Y, Ln (lanthanoid), Sb, Bi, and Te, the B-element is at least one selected from Ga, Ti, Zr, and Hf, the C-element is at least one selected from Group 2 elements in periodic table, etching solution A is used when at least one selected from the source electrode and the drain electrode, the gate electrode, and the active layer is formed, and etching solution B that is etching solution having same type as the etching solution A is used when the gate insulating layer is etched.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: October 27, 2020
    Assignee: Ricoh Company, Ltd.
    Inventors: Minehide Kusayanagi, Naoyuki Ueda, Yuki Nakamura, Yukiko Abe, Shinji Matsumoto, Yuji Sone, Ryoichi Saotome, Sadanori Arae
  • Patent number: 10784363
    Abstract: Various methods and structures for fabricating a contact for a semiconductor FET or FinFET device. A semiconductor FET structure includes a substrate, a source/drain region layer and source/drain contact. First and second gate spacers are adjacent respective first and second opposing sides of the source/drain contact. The source/drain contact is disposed directly on and contacting the entire source/drain region layer, and at a vertical level thereabove, the source/drain contact being recessed to a limited horizontal area continuing vertically upwards from the vertical level. The limited horizontal area horizontally extending along less than a full horizontal length of a vertical sidewall of the first and second gate spacers, and less than fully covering the source/drain region layer. A method uses a reverse contact mask to form a shape of the source/drain contact into an inverted “T” shape.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: September 22, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu
  • Patent number: 10777420
    Abstract: A material layer having recesses is formed on a substrate including a high pattern density area and a low pattern density area. A first dielectric layer and a second dielectric layer are sequentially formed to cover the material layer, wherein a top surface of the first dielectric layer in the high pattern density area is higher than a top surface of the first dielectric layer in the low pattern density area, thereby a thickness of the second dielectric layer in the low pattern density area being thicker than a thickness of the second dielectric layer in the high pattern density area. An etching back process is performed to remove the second dielectric layer and the first dielectric layer, wherein the etching rate of the etching back process to the second dielectric layer is lower than the etching rate of the etching back process to the first dielectric layer.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: September 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuan-Ying Lai, Chang-Mao Wang, Hsin-Yu Hsieh
  • Patent number: 10727342
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kun-Mu Li, Tsz-Mei Kwok, Hsueh-Chang Sung, Chii-Horng Li, Tze-Liang Lee
  • Patent number: 10714590
    Abstract: Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing at least one fin on a semiconductor substrate; forming a stacked channel layer having at least one sacrificial layer on the fin and a channel layer on the sacrificial layer; forming a dummy gate structure on the stacked channel layer; forming openings in the stacked channel layer at both sides of the dummy gate structure; removing portions of the sacrificial layer under the dummy gate structure to form grooves on sidewall surfaces of the openings; and forming a protective layer in the grooves.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: July 14, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, SMIC New Technology Research and Development (Shanghai) Corporation
    Inventor: Fei Zhou
  • Patent number: 10707316
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate, a dielectric layer over the substrate, a first metal gate structure in the dielectric layer and having a first width and a second metal gate structure in the dielectric layer and having a second width. The first metal gate structure includes a first metal electrode, and the second metal gate structure includes a second metal electrode. The second metal electrode includes a first conductive portion having a third width and a second conductive portion over the first conductive portion and having a fourth width. The fourth width is greater than the third width. The semiconductor device structure also includes two first source/drain portions at opposite sides of the first metal gate structure, and two second source/drain portions at opposite sides of the second metal gate structure.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ching Huang, Tsung-Yu Chiang
  • Patent number: 10600693
    Abstract: A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: March 24, 2020
    Assignee: Tessera, Inc.
    Inventor: Kangguo Cheng
  • Patent number: 10573645
    Abstract: A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region and second region, respectively, wherein the first transistor includes a thick gate insulating layer and a thin buffer insulating layer formed in the substrate, a first gate electrode formed on the thick gate insulating layer, a first spacer formed on the thin buffer insulating layer, and a source region and a drain region formed in the substrate.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: February 25, 2020
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Young Bae Kim, Kwang Il Kim, Jun Hyun Kim, In Sik Jung, Jae Hyung Jang, Jin Yeong Son
  • Patent number: 10535666
    Abstract: Integrated circuit devices are provided. An integrated circuit device includes a substrate having first and second fin-shaped Field Effect Transistor (FinFET) bodies protruding from the substrate. The first and second FinFET bodies have different respective first and second shapes in a first region and a second region, respectively, of the integrated circuit device.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: January 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-yup Chung
  • Patent number: 10522422
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on the sidewall of the gate stack structure, and the gate spacers include a top portion and a bottom portion adjoined to the top portion, and the bottom portion slopes to a top surface of the substrate. The semiconductor device structure further includes an epitaxial structure formed adjacent to the gate spacers, and the epitaxial structure is formed below the gate spacers.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yung-Tsun Liu
  • Patent number: 10446662
    Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: October 15, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih Wei Bih, Han-Wen Liao, Xuan-You Yan, Yen-Yu Chen, Chun-Chih Lin
  • Patent number: 10446586
    Abstract: Disclosed are a pixel unit, an array substrate and a manufacturing method therefor, a display panel and a display device. At least two step portions adjacent to each other in an upward direction are provided at at least one of a first side of a drain electrode close to a display region and a second side of the drain electrode away from the display region, such that a pixel electrode is lapped onto the drain electrode gently.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: October 15, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Xiao Wang
  • Patent number: 10381491
    Abstract: A semiconductor device according to an embodiment includes a first electrode; a second electrode; a silicon carbide layer disposed between the first electrode and the second electrode; an n-type silicon carbide region disposed in the silicon carbide layer and having a first nitrogen concentration; a first p-type silicon carbide region disposed in the silicon carbide layer between the n-type silicon carbide region and the first electrode and having a second nitrogen concentration higher than the first nitrogen concentration; and a second p-type silicon carbide region disposed in the silicon carbide layer between the first p-type silicon carbide region and the first electrode, having a third nitrogen concentration higher than the second nitrogen concentration, and having a p-type impurity concentration higher than that of the first p-type silicon carbide region.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: August 13, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tatsuo Shimizu
  • Patent number: 10355017
    Abstract: A CMOS device includes a p-type field effect transistor containing p-doped active regions, an n-type field effect transistor containing n-doped active regions, a silicon oxide layer overlying the n-type field effect transistor and not overlying the p-type field effect transistor, boron-doped epitaxial pillar structures contacting a top surface of, and epitaxially aligned to, a respective one of the p-doped active regions, first active region contact via structures contacting a top surface of a respective one of the boron-doped epitaxial pillar structures, and second active region contact via structures contacting a top surface of a respective one of the n-doped active regions.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: July 16, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hiroshi Nakatsuji, Kiyokazu Shishido, Hiroyuki Ogawa
  • Patent number: 10345698
    Abstract: A method for fabricating a semiconductor device includes forming a pellicle including an amorphous carbon layer, attaching the pellicle onto a reticle, and forming a photoresist pattern by utilizing EUV light transmitted through the pellicle and reflected by the reticle. The forming the pellicle includes forming a first dielectric layer on a first side of the substrate, forming the amorphous carbon layer on the first dielectric layer, forming a second dielectric layer on a second side of the substrate opposite to the first side of the substrate, etching the second dielectric layer overlapping the first region of the substrate to form a mask pattern, and forming a support including the second region of the substrate and the remaining part of the first dielectric layer. The forming the support includes etching the first region of the substrate and the first dielectric layer on the first region.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: July 9, 2019
    Assignees: Samsung Electronics Co., Ltd., Research & Business Foundation Sungyunkwan University
    Inventors: Ji Beom Yoo, Sung Won Kwon, Dong Wook Shin, Mun Ja Kim, Jin Su Kim, Hwan Chul Jeon
  • Patent number: 10332796
    Abstract: A semiconductor device is provided that includes a first plurality of fin structures having a first width in a first region of a substrate, and a second plurality of fin structures having a second width in a second region of the substrate, the second width being less than the first width. A first gate structure is formed on the first plurality of fin structures including a first high-k gate dielectric that is in direct contact with a channel region of the first plurality of fin structures and a first gate conductor. A second gate structure is formed on the second plurality of fin structures including a high voltage gate dielectric that is in direct contact with a channel region of the second plurality of fin structures, a second high-k gate dielectric and a second gate conductor.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10304683
    Abstract: By decoupling the formation of a metal silicide in the gate electrode structure and the raised drain and source regions, superior flexibility in designing transistor elements and managing overall process flow may be achieved. To this end, the metal silicide in the gate electrode structures may be formed prior to actually patterning the gate electrode structures, while, also during this process sequence, a mask material may be applied for reliably covering any device regions in which a silicidation is not required. Consequently, superior gate conductivity may be accomplished, without increasing the risk of silicide penetration into the channel region of sophisticated fully depleted SOI transistors.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: May 28, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Elliot John Smith
  • Patent number: 10304934
    Abstract: The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lukas Czornomaz, Veeresh V. Deshpande, Vladimir Djara
  • Patent number: 10256302
    Abstract: A vertical transistor has a first air-gap spacer between a gate and a bottom source/drain region, and a second air-gap spacer between the gate and the contact to the bottom source/drain region. A dielectric layer disposed between the gate and the contact to the top source/drain decreases parasitic capacitance and inhibits electrical shorting.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Tak H. Ning
  • Patent number: 10141190
    Abstract: In a manufacturing method of a semiconductor device according to an embodiment, an oxide film is formed on a semiconductor layer containing an impurity. A heat treatment is performed on the semiconductor layer to diffuse part of the impurity into the oxide film with hydrogen plasma treatment on the oxide film or with ultraviolet irradiation on the oxide film. After the heat treatment, the oxide film is removed.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: November 27, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Tatsunori Isogai
  • Patent number: 10128110
    Abstract: Embodiments of the present disclosure generally relate to methods for forming a doped silicon epitaxial layer on semiconductor devices at increased pressure and reduced temperature. In one embodiment, the method includes heating a substrate disposed within a processing chamber to a temperature of about 550 degrees Celsius to about 800 degrees Celsius, introducing into the processing chamber a silicon source comprising trichlorosilane (TCS), a phosphorus source, and a gas comprising a halogen, and depositing a silicon containing epitaxial layer comprising phosphorus on the substrate, the silicon containing epitaxial layer having a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, wherein the silicon containing epitaxial layer is deposited at a chamber pressure of about 150 Torr or greater.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: November 13, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Abhishek Dube, Xuebin Li, Yi-Chiau Huang, Hua Chung, Schubert S. Chu
  • Patent number: 10121852
    Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie, Derrick Liu, Soon-Cheon Seo, Stuart A. Sieg
  • Patent number: 10121853
    Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Fee Li Lie, Derrick Liu, Soon-Cheon Seo, Stuart A. Sieg
  • Patent number: 10014386
    Abstract: There is provided a method for manufacturing a transistor including a gate above an underlying layer of a semiconductor material and including at least one first flank and one second flank, a gate foot formed in the underlying layer, a peripheral portion of the underlying layer surrounding the gate foot, and spacers covering at least partially the first and second flanks so as to not cover the gate foot; the method including forming the underlying layer by partially removing the semiconductor material around the gate to form the gate foot and the peripheral portion; then forming a dielectric layer for forming spacers by a deposition to cover both the first and second flanks, the gate foot, and an upper surface of the peripheral portion; and then partially removing the dielectric layer so as to expose the upper surface and so as to not expose the first and second flanks.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: July 3, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Christian Arvet
  • Patent number: 10008569
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a gate structure is formed on the substrate, a recess is formed adjacent to the gate structure, a buffer layer is formed in the recess, and an epitaxial layer is formed on the buffer layer. Preferably, the buffer layer includes a crescent moon shape.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: June 26, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Yu-Hsiang Hung, Wei-Chi Cheng, Jyh-Shyang Jenq
  • Patent number: 9966309
    Abstract: A method includes forming a metallic layer over a Metal-Oxide-Semiconductor (MOS) device, forming reverse memory posts over the metallic layer, and etching the metallic layer using the reverse memory posts as an etching mask. The remaining portions of the metallic layer include a gate contact plug and a source/drain contact plug. The reverse memory posts are then removed. After the gate contact plug and the source/drain contact plug are formed, an Inter-Level Dielectric (ILD) is formed to surround the gate contact plug and the source/drain contact plug.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: May 8, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yuan Ting, Jyu-Horng Shieh
  • Patent number: 9935199
    Abstract: A semiconductor device includes a substrate including a first fin element, a second fin element, and a third fin element. A first source/drain epitaxial feature is disposed over the first and second fin elements. A first portion of the first source/drain epitaxial feature disposed on the first fin element and a second portion of the first source/drain epitaxial feature disposed on the second fin element merge at a merge point. A second source/drain epitaxial feature is disposed over the third fin element. A first sidewall of the second source/drain epitaxial feature interfaces a first third-fin spacer disposed along a first sidewall of the third fin element. A second sidewall of the second source/drain epitaxial feature interfaces a second third-fin spacer disposed along a second sidewall of the third fin element. The merge point has a first height less than a second height of the first third-fin spacer.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chih-Hao Wang, Ying-Keung Leung
  • Patent number: 9887080
    Abstract: A method of forming a SiOCN material layer and a method of fabricating a semiconductor device are provided, the method of forming a SiOCN material layer including supplying a silicon source onto a substrate; supplying a carbon source onto the substrate; supplying an oxygen source onto the substrate; and supplying a nitrogen source onto the substrate, wherein the silicon source includes a non-halogen silylamine, a silane compound, or a mixture thereof.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: February 6, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kang-hun Moon, Yong-suk Tak, Gi-gwan Park
  • Patent number: 9881790
    Abstract: Embodiments of the present disclosure generally relate to methods for forming a doped silicon epitaxial layer on semiconductor devices at increased pressure and reduced temperature. In one embodiment, the method includes heating a substrate disposed within a processing chamber to a temperature of about 550 degrees Celsius to about 800 degrees Celsius, introducing into the processing chamber a silicon source comprising trichlorosilane (TCS), a phosphorus source, and a gas comprising a halogen, and depositing a silicon containing epitaxial layer comprising phosphorus on the substrate, the silicon containing epitaxial layer having a phosphorus concentration of about 1×1021 atoms per cubic centimeter or greater, wherein the silicon containing epitaxial layer is deposited at a chamber pressure of about 150 Torr or greater.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: January 30, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Abhishek Dube, Xuebin Li, Yi-Chiau Huang, Hua Chung, Schubert S. Chu
  • Patent number: 9865515
    Abstract: A semiconductor device fabricated using a high-temperature ion implantation process is provided. The high-temperature ion implantation process includes providing a substrate having a plurality of fins. A mask material is deposited and patterned to expose a group of fins of the plurality of fins and a test structure. A first ion implantation may be performed, at a first temperature, through the group of fins and the test structure. Additionally, a second ion implantation may be performed, at a second temperature greater than the first temperature, through the group of fins and the test structure. An interstitial cluster is formed within the group of fins and within the test structure. Thereafter, an anneal process is performed, where the anneal process serves to remove the interstitial cluster from the group of fins and form at least one dislocation loop within the test structure.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: January 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsan-Chun Wang, Chun Hsiung Tsai, Ziwei Fang
  • Patent number: 9842778
    Abstract: A method of fabricating a semiconductor device includes forming a first well region and a second well region in a semiconductor substrate, forming an isolation region defining a first fin active region and a second fin active region on the semiconductor substrate, forming a sacrificial gate layer on the semiconductor substrate having the first and second fin active regions and the isolation region, forming a hardmask line on the sacrificial gate layer, forming a gate cut mask having a gate cut opening on the hardmask line, and forming first and second hardmask patterns spaced apart from each other by etching the hardmask line using the gate cut mask as an etching mask. The gate cut opening overlaps a boundary between the first and second well regions formed between the first and second fin active regions, and has a line shape in a direction intersecting the hardmask line.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: December 12, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junggun You, Sukhoon Jeong
  • Patent number: 9837357
    Abstract: Various methods and semiconductor structures for fabricating at least one FET device having textured gate-source-drain contacts of the FET device that reduce or eliminate variability in parasitic resistance between the contacts of the FET device. An example fabrication method includes epitaxially growing a source-drain contact region on an underlying semiconductor substrate of one of a pFET device or an nFET device. The method deposits a Nickel film layer directly on the epitaxially grown source-drain contact region. A first anneal forms a textured Nickel silicide film layer directly on the epitaxially grown source-drain contact region. A second metal film layer is deposited on the textured Nickel silicide film layer. A second anneal forms a textured second metal silicide film layer. The method can be repeated on the other one of the pFET device or the nFET device.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: December 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Hemanth Jagannathan, Christian Lavoie, Jean L. Sweet
  • Patent number: 9825044
    Abstract: The method for preventing epitaxial growth in a semiconductor device begins with cutting a set of long fins into a set of fins of a FinFET structure, the set of fins having respective cut faces of a set of cut faces located at respective fin ends of a set of fin ends. A photoresist layer is patterned over the set of fin ends of the set of fins of the FinFET structure. The photoresist pattern over the set of fin ends differs from the photoresist pattern over other areas of the FinFET structure as the photoresist pattern over the set of fin ends protects the first dielectric material at the set of fin ends. A set of dielectric blocks is formed at the set of fin ends, wherein each of the dielectric blocks covers at least one cut face. The set of dielectric blocks prevents epitaxial growth at the set of fin ends in a subsequent epitaxial growth step.
    Type: Grant
    Filed: October 8, 2016
    Date of Patent: November 21, 2017
    Assignees: International Business Machines Corporation, Global Foundries
    Inventors: Balasubramanian Pranatharthiharan, Hui Zang
  • Patent number: 9825034
    Abstract: A semiconductor device may include a strain relaxed buffer layer provided on a substrate to contain silicon germanium, a semiconductor pattern provided on the strain relaxed buffer layer to include a source region, a drain region, and a channel region connecting the source region with the drain region, and a gate electrode enclosing the channel region and extending between the substrate and the channel region. The source and drain regions may contain germanium at a concentration of 30 at % or higher.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: November 21, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Hwan Lee, Sangsu Kim
  • Patent number: 9780001
    Abstract: A method of fabricating Schottky barrier contacts for an integrated circuit (IC). A substrate including a silicon including surface is provided. A plurality of transistors are formed on the silicon including surface in at least one PMOS region and at least one NMOS region, where the plurality of transistors include at least one exposed p-type surface region and at least one exposed n-type surface region. Pre-silicide cleaning removes oxide from the exposed p-type surface regions and exposed n-type surface regions. A plurality of metals are deposited including Yb and Pt to form at least one metal layer on the substrate. The metal layer is heated to induce formation of an inhomogeneous silicide layer including both Ptsilicide and Ybsilicide on the exposed p-type and exposed n-type surface regions. Unreacted metal of the metal layer is stripped.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: October 3, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Deborah Jean Riley, Judy Browder Shaw, Christopher L. Hinkle, Creighton T. Buie
  • Patent number: 9741776
    Abstract: A method for manufacturing an organic light emitting diode display includes forming a thin-film transistor on a substrate, forming a protection layer by using a deposition method on an entire surface of the substrate, and forming an organic light emitting element on the protection layer. Forming the protection layer includes forming a first protection layer, a surface thereof including a first wrinkle, and forming a second protection layer on the first protection layer, a surface thereof including a second wrinkle. A first modulus value of the first protection layer is less than a second modulus value of the second protection layer by at least 300 MPa.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: August 22, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jae Heung Ha, Yong Tack Kim, Jong Woo Kim, Ji Young Moon, Min Ho Oh, Seung Jae Lee, Yoon Hyeung Cho
  • Patent number: 9722023
    Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: August 1, 2017
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Tahir Ghani
  • Patent number: 9704972
    Abstract: A method is provided for fabricating transistors. The method includes providing a semiconductor substrate. The substrate has a gate film and a mask film formed on a top surface. The mask film contains implanted carbon ions. The method further includes forming a mask layer by etching the mask film and then forming a gate layer by etching through the gate film using the mask layer as a mask until the substrate is exposed. The method also includes forming a first sidewall containing implanted carbon ions on the side surface of the gate layer and the mask layer; forming a stress layer in the substrate on both sides of the gate layer and the first sidewall; and forming a source region on one side of the gate layer and the first sidewall and a drain region on the other side of the gate layer and the first side wall.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 11, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Qiuhua Han, Jie Chen
  • Patent number: 9698245
    Abstract: A vertical transistor has a first air-gap spacer between the gate and the bottom source/drain, and a second air-gap spacer between the gate and the contact to the bottom source/drain. A dielectric layer disposed between the gate and the contact to the top source/drain decreases parasitic capacitance and inhibits electrical shorting.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: July 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Tak H. Ning
  • Patent number: 9691695
    Abstract: A 3D-IC includes a first tier device and a second tier device. The first tier device and the second tier device are vertically stacked together. The first tier device includes a first substrate and a first interconnect structure formed over the first substrate. The second tier device includes a second substrate, a doped region formed in the second substrate, a dummy gate formed over the substrate, and a second interconnect structure formed over the second substrate. The 3D-IC also includes an inter-tier via extends vertically through the second substrate. The inter-tier via has a first end and a second end opposite the first end. The first end of the inter-tier via is coupled to the first interconnect structure. The second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: June 27, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ta-Pen Guo, Carlos H. Diaz, Jean-Pierre Colinge, Yi-Hsiung Lin
  • Patent number: 9685538
    Abstract: The present invention provides a low temperature polysilicon thin film transistor and a fabricating method thereof. According to the method, a laser annealing process is performed to a remained portion of a a-Si layer on a substrate to form a first lightly doped drain (LDD) terminal, a second LDD terminal, a first phosphor material structure and a second phosphor material structure. A gate metal layer is then formed on the remained portion of the a-Si layer. A source metal layer and a drain metal layer are formed on the first doped layer and the second doped layer located at opposite sides of the gate metal layer, respectively. The present invention use the high temperature of the laser annealing process to perform a heat diffusion of phosphor material to form the LDD terminal and the phosphor material structure, the times of photomasks are used is reduced, and the process is simplified.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: June 20, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Songshan Li, Xiaoxing Zhang
  • Patent number: 9620619
    Abstract: A borderless contact structure or partially borderless contact structure and methods of manufacture are disclosed. The method includes forming a gate structure and a space within the gate structure, defined by spacers. The method further includes blanket depositing a sealing material in the space, over the gate structure and on a semiconductor material. The method further includes removing the sealing material from over the gate structure and on the semiconductor material, leaving the sealing material within the space. The method further includes forming an interlevel dielectric material over the gate structure. The method further includes patterning the interlevel dielectric material to form an opening exposing the semiconductor material and a portion of the gate structure. The method further includes forming a contact in the opening formed in the interlevel dielectric material.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: April 11, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Veeraraghavan S. Basker, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Patent number: 9620622
    Abstract: A method for manufacturing a field effect transistor includes chelating a molecular mask to a replacement metal gate in a field effect transistor. The method may further include forming a patterned dielectric layer on a bulk dielectric material and a gate dielectric barrier in one or more deposition steps. The method may include removing the molecular mask and exposing part of the gate dielectric barrier before depositing a dielectric cap that touches the gate dielectric barrier and the replacement metal gate.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: April 11, 2017
    Assignee: International Business Machines Corporation
    Inventors: Damon B. Farmer, Michael A. Guillorn, Balasubramanian Pranatharthiharan, George S. Tulevski
  • Patent number: 9608113
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The semiconductor device structure also includes a sealing structure over a sidewall of the gate stack, and a width ratio of the sealing structure to the gate stack is in a range from about 0.05 to about 0.7. The semiconductor device structure further includes an etch stop layer over the semiconductor substrate, the gate stack, and the sealing structure. The etch stop layer is in contact with the sealing structure.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: March 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Cheng Chang, Yi-Jen Chen, Yung-Jung Chang
  • Patent number: 9601586
    Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device includes forming a metal layer on source/drain regions of respective semiconductor structures, after replacing a dummy gate structure of the semiconductor device with a metal gate structure. The method includes forming a contact structure that overlaps the metal layer on one or more, but not all, of the semiconductor structures. Moreover, an insulating material is between the source/drain regions.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: March 21, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jorge A. Kittl, Joon Goo Hong, Mark S. Rodder
  • Patent number: 9601433
    Abstract: In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: March 21, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Terada, Shigeya Toyokawa, Atsushi Maeda