Method for opto-electronic integration on a SOI substrate and related structure

- Newport Fab, LLC

According to an exemplary embodiment, a method includes providing a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. A trench is formed in the silicon layer and the buried oxide layer, where the trench exposes a portion of the bulk silicon substrate, and where the trench is situated adjacent to an optical region of said silicon-on-insulator substrate. According to this exemplary embodiment, an epitaxial layer is formed on the exposed portion of the bulk silicon substrate in the trench. The epitaxial layer and the bulk silicon substrate form a bulk silicon electronic region of the silicon-on-insulator substrate.

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Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is generally in the field of semiconductors. More particularly, the invention is in the field of semiconductor substrates for integration of optical and electronic components.

2. Background Art

Different substrate requirements for optical components, such as waveguides, gratings, and modulators, and bulk silicon electronic devices, such as bipolar and Complementary-Metal-Oxide-Semiconductor (“CMOS”) devices, hinder the integration of optical components and bulk silicon electronics on a single substrate. For example, optical components can be optimized on a Silicon-On-Insulator (“SOI”) substrate having a thin silicon layer situated over a thicker buried oxide layer, which is in turn situated over bulk silicon. In a SOI substrate that is optimized for optical components, the thin silicon layer in the SOI substrate can have an exemplary thickness of a few thousand Angstroms. However, bulk silicon electronic devices, such as vertical bipolar transistors, require much thicker silicon, such as silicon having a thickness of hundreds of microns.

Optical components have been fabricated using Silicon-On-Saphire (“SOS”) technology, which takes advantage of a transparent saphire substrate. However, an undesirably high defectivity rate in SOS substrates currently reduces the feasibility of integrating optical components and bulk silicon electronics on a SOS substrate. Additionally, the cost of the SOS substrate is very high.

Thus, there is a need in the art for an effective method for integrating optical components and bulk silicon electronics on a single semiconductor substrate.

SUMMARY OF THE INVENTION

The present invention is directed to method for opto-electronic integration on a SOI substrate and related structure. The present invention addresses and resolves the need in the art for an effective method for integrating optical components and bulk silicon electronics on a semiconductor substrate.

According to an exemplary embodiment, a method includes providing a silicon-on-insulator substrate including a buried oxide layer situated over a bulk silicon substrate and a silicon layer situated over the buried oxide layer. A trench is formed in the silicon layer and the buried oxide layer, where the trench exposes a portion of the bulk silicon substrate, and where the trench is situated adjacent to an optical region of the silicon-on-insulator substrate.

According to this exemplary embodiment, an epitaxial layer is formed on the exposed portion of the bulk silicon substrate in the trench. The epitaxial layer can be single-crystal silicon and can be grown on the exposed portion of the bulk silicon substrate be formed by using a selective epitaxial process, for example. A top surface of the epitaxial layer and a top surface of the silicon layer can form a substantially planar surface, for example. The epitaxial layer and the bulk silicon substrate form a bulk silicon electronic region of the silicon-on-insulator substrate. The method further includes forming a conformal dielectric layer over the silicon-on-insulator substrate and planarizing the conformal dielectric layer such that the top surface of the silicon layer and the top surface of the epitaxial layer are exposed.

According to this exemplary embodiment, an interlayer dielectric layer can be formed over the silicon-on-insulator substrate and a first and a second contact can be formed in the interlayer dielectric layer, where the first contact is situated over the optical region of the silicon-on-insulator substrate and the second contact is situated over the bulk silicon electron region of the silicon-on-insulator substrate. A first and a second interconnect metal segment can be formed on the interlayer dielectric layer, where the first interconnect metal segment is situated over the first contact and the second interconnect metal segment is situated over the second contact. The first interconnect metal segment and the second interconnect metal segment can be connected to provide communication between the optical region and the bulk silicon electronic region.

According to one embodiment, the invention is a structure that is achieved by utilizing the above-described method. Other features and advantages of the present invention will become more readily apparent to those of ordinary skill in the art after reviewing the following detailed description and accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a flowchart illustrating the steps taken to implement an embodiment of the present invention.

FIG. 2A illustrates a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to an intermediate step in the flowchart in FIG. 1.

FIG. 2B illustrates a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to an intermediate step in the flowchart in FIG. 1.

FIG. 2C illustrates a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to an intermediate step in the flowchart in FIG. 1.

FIG. 2D illustrates a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to an intermediate step in the flowchart in FIG. 1.

FIG. 2E illustrates a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to an intermediate step in the flowchart in FIG. 1.

FIG. 2F illustrates a cross-sectional view, which includes a portion of a wafer processed according to an embodiment of the invention, corresponding to a final step in the flowchart in FIG. 1.

 DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to method for opto-electronic integration on a SOI substrate and related structure. The following description contains specific information pertaining to the implementation of the present invention. One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order to not obscure the invention. The specific details not described in the present application are within the knowledge of a person of ordinary skill in the art.

The drawings in the present application and their accompanying detailed description are directed to merely example embodiments of the invention. To maintain brevity, other embodiments of the invention which use the principles of the present invention are not specifically described in the present application and are not specifically illustrated by the present drawings.

The present invention involves a process to effectively integrate optical components and bulk silicon electronic devices on a SOI (silicon-on-insulator) substrate. As will be discussed below, the present invention's innovative process results in the SOI substrate having optical regions for formation of optimized optical components, such as waveguides, gratings, and modulators, and bulk silicon electronic regions for formation of bulk silicon electronic devices, such as bipolar transistors and/or CMOS devices.

FIG. 1 shows a flow chart illustrating an exemplary method according to an embodiment of the present invention. Certain details and features have been left out of flowchart 100 that are apparent to a person of ordinary skill in the art. For example, a step may consist of one or more substeps or may involve specialized equipment or materials, as known in the art. Steps 170 through 180 indicated in flowchart 100 are sufficient to describe one embodiment of the present invention, other embodiments of the invention may utilize steps different from those shown in flowchart 100.

Moreover, structures 270 through 280 in FIGS. 2A through 2F illustrate the result of performing steps 170 through 180 of flowchart 100, respectively. For example, structure 270 shows a semiconductor structure after processing step 170, structure 272 shows structure 270 after the processing of step 172, structure 274 shows structure 272 after the processing of step 174, and so forth. It is noted that although formation of only one bulk silicon electronic region and two optical regions are specifically discussed herein to preserve brevity, multiple bulk silicon electronic regions and optical regions may be formed on a SOI substrate by utilizing the innovative process of the present invention.

Referring now to step 170 in FIG. 1 and structure 270 in FIG. 2A, at step 170 of flowchart 100, SOI substrate 202 is provided, which includes bulk silicon substrate 204, buried oxide layer 206, which is situated on bulk silicon substrate 204, and silicon layer 208, which is situated on buried oxide layer 206. SOI substrate 202 can be optimized for formation of optical components, such as waveguides, gratings, and modulators, by appropriately controlling thickness 210 of buried oxide layer 206 and thickness 212 of silicon layer 208. By way of example, for optimal optical component formation, thickness 210 of buried oxide layer 206 can be approximately 1.25 microns while thickness 212 of silicon layer 208 can be between approximately 3000.0 Angstroms and approximately 6000.0 Angstroms. By way of example, thickness 214 of bulk silicon substrate 204 can be approximately 1.0 mm.

SOI substrate 202 can be formed, for example, by thermally growing a layer of silicon oxide on a silicon surface on each of two wafers. The oxidized surfaces of the wafers can then be pressed against each other at a sufficiently high temperature to cause the wafers to bond together. Silicon oxide situated in the bonding plane of the bonded wafers forms a buried oxide layer, i.e. buried oxide layer 206, in the subsequently formed SOI substrate, i.e. SOI substrate 202. The excess silicon in one of the wafers can be substantially removed by an etching process, a grinding process, or other appropriate process such that a silicon layer, i.e. silicon layer 208, having a desired thickness is obtained. SOI substrate 202 can also be formed by other appropriate methods as known in the art. The result of step 170 of flowchart 100 is illustrated by structure 270 in FIG. 2A.

Referring to step 172 in FIG. 1 and structure 272 in FIG. 2B, at step 172 of flowchart 100, trench 216 is formed in silicon layer 208 and buried oxide layer 206 of SOI substrate 202 to expose portion 218 of bulk silicon substrate 204. Trench 216 has sidewalls 220 and 222, bottom surface 224, width 226, and depth 228. By way of example, width 226 of trench 216 can be between approximately 6.0 microns and approximately 10.0 microns. By way of example, depth 228 of trench 216 can be between approximately 1.5 microns and approximately 2.0 microns. Sidewalls 220 and 222 of trench 216 define edges of respective optical regions 230 and 232 of SOI substrate 202.

Trench 216 can be formed by using a masking process to deposit and pattern a photoresist mask on silicon layer 208. The photoresist mask covers optical regions 230 and 232 of SOI substrate 202 while leaving a trench opening uncovered. In one embodiment, a masking process can be used to form a hard mask on silicon layer 208. After the trench opening has been formed in the mask, portions of silicon layer 208 and buried oxide layer 206 are sequentially removed in the trench opening by using an appropriate etch process or processes to form trench 216. For example, a dry etch process can initially be used to ensure straight trench sidewalls and achieve a desired trench depth. After the dry etch process, a wet etch process can be used to remove any remaining oxide in the trench and ensure a high quality trench bottom surface. The wet etch process can comprise an etchant such as hydrofluoric acid (HF), which is selective to silicon and, therefore, will cause minimal erosion of bulk silicon substrate 204. The wet etch process can also be used to remove the mask after formation of trench 216. The result of step 172 of flowchart 100 is illustrated by structure 272 in FIG. 2B.

Referring to step 174 in FIG. 1 and structure 274 in FIG. 2C, at step 174 of flowchart 100, spacers 234 and 236 are formed on respective sidewalls 220 and 222 of trench 216 and epitaxial layer 238 is formed between spacers 234 and 236 on exposed portion 218 (FIG. 2B) of bulk silicon substrate 204 to form electronic region 244 of SOI substrate 202. Spacers 234 and 236 are situated on bottom surface 224 and on respective sidewalls 220 and 222 of trench 216 and can comprise silicon oxide or other appropriate dielectric material. Spacers 234 and 236 can be formed, for example, by depositing a conformal layer of silicon oxide over silicon layer 208 and over sidewalls 220 and 222 and bottom surface 224 of trench 216. The deposited conformal layer of silicon oxide can then be “etched back” using an anisotropic etch process, which can comprise an etchant that is selective to silicon and, consequently, will not etch bulk silicon substrate 204. Spacers 234 and 236 prevent silicon from growing on exposed edges of silicon layer 208 during subsequent epitaxial layer formation.

Epitaxial layer 238 is situated between spacers 234 and 236 in trench 216 and on bulk silicon substrate 204 and can comprise single-crystal silicon. Epitaxial layer 238 can be formed on exposed portion 218 (FIG. 2B) of bulk silicon substrate 204 by using a selective epitaxial process. In the selective epitaxial process, single-crystal silicon is grown on exposed regions, such as electronic region 244, of bulk silicon substrate 204 and not grown on the unexposed regions, such as optical regions 230 and 232 and spacers 234 and 236. To prevent silicon from growing on top surface 240 of silicon layer 208 in optical regions 230 and 232, optical regions 230 and 232 can be covered by a mask (not shown in FIG. 2C), such as a photoresist mask or a silicon oxide hard mask. The selective epitaxial process can be implemented by using a chemical vapor deposition (“CVD”) process or other appropriate processes to deposit silicon only on exposed silicon surfaces, such as exposed portion 218 (FIG. 2B) of bulk silicon substrate 204. Thus, the selective epitaxial process is selective to, i.e. will not deposit silicon on, dielectric surfaces comprising oxide, such as spacers 234 and 236, or surfaces protected by a mask (not shown in FIG. 2C), such as top surface 240 of silicon layer 208 in optical regions 230 and 232. In the selective epitaxial process, epitaxial layer 238 can be doped with an appropriate dopant having a desired dopant concentration.

By way of background, the particular process chemistry used for epitaxial deposition of silicon determines the thickness of silicon deposited on different materials as a function of time. Although the silicon deposition rate may be similar for different materials once a seed layer is formed, each material typically requires a different amount of time, i.e. an incubation time, to form the seed layer and begin nucleating. For example, for silicon deposition the incubation time required to form a seed layer on silicon oxide is greater than the incubation time required to form a seed layer on silicon. As a result, during epitaxial silicon deposition, a certain thickness of silicon may form on a silicon surface prior to silicon nucleating on a silicon oxide surface.

The difference between the time required to form a seed layer, or nucleate, on silicon oxide, for example, and the time required to form a seed layer on silicon, i.e. the “incubation window,” is determined, among other things, by pressure, gas flow, and the chemistries used in the selective epitaxial emitter process. Thus, in the present embodiment, the selective epitaxial process can be engineered to widen the incubation window to achieve a desired thickness for epitaxial layer 238 on exposed portion 218 of bulk silicon substrate 204 without nucleating any silicon on silicon oxide, i.e. on spacers 234 and 236, or on a mask (not shown in FIG. 2C) formed over silicon layer 208 in optical regions 230 and 232. In the present embodiment, epitaxial layer 238 can be grown to a sufficient thickness such that top surface 242 of epitaxial layer 238 is substantially level with top surface 240 of silicon layer 208, i.e. top surface 242 of epitaxial layer 238 and top surface 240 of silicon layer 208 form a substantially planar surface. In other embodiments, top surface 242 of epitaxial layer 238 may be situated above or below top surface 240 of silicon layer 208. In other embodiments, epitaxial layer 238 may comprise semiconductor materials other than single crystal silicon.

Bulk silicon electronic region 244 of SOI substrate 202 is situated between spacers 234 and 236 and is formed by growing epitaxial layer 238 on bulk silicon substrate 204 as discussed above. Thus, in one embodiment, bulk silicon electronic region 244 comprises single crystal silicon only and has total thickness 246 which is equivalent to thickness 214 (FIG. 2A) of bulk silicon substrate 204 plus depth 228 (FIG. 2B) of trench 216. Thus, in one embodiment, total thickness 246 is equivalent to approximately 1.0 millimeter plus the relatively negligible thickness of approximately 1.5 to 2.0 microns. Thus, electronic region 244 has sufficient thickness to form bulk silicon electronic devices, such as bipolar transistors and/or CMOS devices.

By forming bulk silicon electronic region 244 adjacent to optical regions 230 and 232 in SOI substrate 204, the present invention advantageously achieves integration of optical components in optical regions 230 and 232 with bulk silicon electronic devices in bulk silicon electronic region 244 on a single SOI substrate. Furthermore, optical regions 230 and 232 can be optimized for formation of optical components and devices while bulk silicon devices, such as bipolar transistors and/or CMOS devices, can be formed in sufficiently thick silicon in bulk silicon electronic region 244. The result of step 174 of flowchart 100 is illustrated by structure 274 in FIG. 2C.

Referring to step 176 in FIG. 1 and structure 276 in FIG. 2D, at step 176 of flowchart 100, conformal dielectric layer 246 is formed over SOI substrate 202. Conformal dielectric layer 246, which has top surface 248, is situated on silicon layer 208, spacers 234 and 236, and epitaxial layer 238 and can comprise silicon oxide or other appropriate dielectric. Conformal dielectric layer 246 can be formed by using a CVD process or other appropriate deposition process to deposit a conformal layer of silicon oxide or other appropriate dielectric over SOI substrate 202. The result of step 176 of flowchart 100 is illustrated by structure 276 in FIG. 2D.

Referring to step 178 in FIG. 1 and structure 278 in FIG. 2E, at step 178 of flowchart 100, top surface 248 of conformal dielectric layer 246 on SOI substrate 202 is planarized to form planar surface 250 and expose top surface 240 of silicon layer 208 and top surface 242 of epitaxial layer 238. Planar surface 250 can be formed by using a chemical mechanical polishing (“CMP”) process or other appropriate planarization process to remove a sufficient portion of conformal dielectric layer 246 such that top surface 240 of silicon layer 208 and top surface 242 of epitaxial layer 238 are exposed. By way of background, CMP is a wafer polishing process that combines chemical removal with mechanical buffing, and is used, among other things, for wafer planarization during the wafer fabrication process.

After the planarization process has been performed, conformal dielectric layer portions 251 and 253 remain situated between epitaxial layer 238 and respective spacers 234 and 236. After planar surface 250 has been formed on SOI substrate 202, optical components can be formed in optical regions 230 and 232 of SOI substrate 202 and bulk silicon electronic devices, such as bipolar transistors and/or CMOS devices, can be formed in bulk silicon electronic region 244 of SOI substrate 202. Conformal dielectric layer portion 251 and spacer 234 provide isolation between optical region 230 and bulk silicon electronic region 244, while conformal dielectric layer portion 253 and spacer 236 provide isolation between optical region 232 and bulk silicon electronic region 244. The result of step 178 of flowchart 100 is illustrated by structure 278 in FIG. 2E.

Referring to step 180 in FIG. 1 and structure 280 in FIG. 2F, at step 180 of flowchart 100, interlayer dielectric (“ILD”) layer 252 is formed on SOI substrate 202, contacts 256a, 256b, and 256c are formed in ILD layer 252; and metal segments 254a, 254b, 254c, and 254d are patterned on ILD layer 252. ILD layer 252 is situated on planar surface 250 of SOI substrate 202 and can comprise silicon oxide or other appropriate dielectric, such as a dielectric having a low dielectric constant, i.e. a low-k dielectric. ILD layer 252 can be formed by CVD process or other appropriate deposition processes. Contacts 256a and 256b are situated in ILD layer 252 over optical region 230 and contact 256c is situated in ILD layer 252 over bulk silicon electronic region 244. Contacts 256a, 256b, and 256c can comprise tungsten or other appropriate metal and can be formed by etching a contact hole in ILD layer 252 using a plasma etch or other appropriate etch process. The contact hole can then be filled with tungsten or other appropriate metal to form contacts 256a, 256b, and 256c.

*** Interconnect metal segments 254a and 254b are situated on ILD layer 252 over respective contacts 256a and 256b, interconnect metal segment 254c is situated on ILD layer 252 over contact 256c, and interconnect metal segment 254d is situated on ILD layer 252 over optical region 232 of SOI substrate 202. Interconnect metal segments 254a, 254b, 254c, and 254d can comprise aluminum, copper, or other suitable metal and may be formed by depositing and patterning a layer of interconnect metal on ILD layer 252 in a manner known in the art. Interconnect metal segments 254a and 254b are connected to optical region 230 by respective contacts 256a and 256b and interconnect metal segment 254c is connected to bulk silicon electronic region 244 by contact 256c. Interconnect metal segments 254a or 254b can be connected to interconnect metal segment 254c in the same interconnect metal layer that they are formed in or connected in a higher interconnect metal layer (not shown in FIG. 2F) to provide communication between optical region 230 and bulk silicon electronic region 244. The result of step 180 of flowchart 100 is illustrated by structure 280 in FIG. 2F.

Thus, as discussed above, the present invention achieves a SOI substrate having a bulk silicon electronic region, which includes an epitaxial layer situated on a bulk silicon substrate, situated adjacent to at least one optical region, which includes a thin silicon layer situated on a buried oxide layer. As a result, the present invention advantageously achieves a SOI substrate suitable for integrating optical components, such as waveguides, gratings, and modulators, in an optical region of the SOI substrate with bulk silicon electronic devices, such as bipolar transistors and/or CMOS devices, in a bulk silicon electronic region of the SOI substrate.

Also, the present invention advantageously provides a SOI substrate having an optical region that can be optimized for formation of optical components while providing an adjacent bulk silicon electronic region for formation of bulk silicon electronic devices. Thus, by providing a bulk silicon electronic region and an optical region in a single SOI substrate, the present invention advantageously eliminates the complexity associated with attempting to form bulk silicon electronic devices in silicon and buried oxide layers of a SOI substrate that are optimized for formation of optical components.

From the above description of the invention it is manifest that various techniques can be used for implementing the concepts of the present invention without departing from its scope. Moreover, while the invention has been described with specific reference to certain embodiments, a person of ordinary skill in the art would appreciate that changes can be made in form and detail without departing from the spirit and the scope of the invention. Thus, the described embodiments are to be considered in all respects as illustrative and not restrictive. It should also be understood that the invention is not limited to the particular embodiments described herein but is capable of many rearrangements, modifications, and substitutions without departing from the scope of the invention.

Thus, method for opto-electronic integration on a SOI substrate and related structure have been described.

Claims

1. A structure comprising:

a silicon-on-insulator substrate comprising a buried oxide layer having a first thickness situated over a bulk silicon substrate and a silicon layer having a second thickness situated over said buried oxide layer;
a trench situated in said silicon layer and said buried oxide layer, said trench having a first and a second sidewall, said trench being situated adjacent to an optical region of said silicon-on-insulator substrate, wherein said optical region comprises at least one optical component;
an epitaxial layer situated in said trench and situated on said bulk silicon substrate;
wherein said epitaxial layer and said bulk silicon substrate form a bulk silicon electronic region of said silicon-on-insulator substrate;
wherein said optical region of said silicon-on-insulator substrate is optimized for at least one optical component by controlling said first thickness of said buried oxide layer and said second thickness of said silicon layer.

2. The structure of claim 1 further comprising a first spacer and a second spacer, said first spacer being situated between said first sidewall of said trench and said epitaxial layer said second spacer being situated between said second sidewall of said trench and said epitaxial layer.

3. The structure of claim 1 further comprising an interlayer dielectric layer situated over said silicon-on-insulator substrate.

4. The structure of claim 3 further comprising a first interconnect metal segment and a second interconnect metal segment situated on said interlayer dielectric layer, said first interconnect metal segment connected to said optical region by a first contact and said second interconnect metal segment connected to said bulk silicon electronic region by a second contact.

5. The structure of claim 1 wherein said silicon-on-insulator substrate has a planar surface, said planar surface including a top surface of said silicon layer and a top surface of said epitaxial layer.

6. The structure of claim 2 further comprising a first conformal dielectric layer portion situated between said first spacer and said epitaxial layer and a second conformal dielectric layer portion situated between said second spacer and said epitaxial layer.

7. The structure of claim 1 wherein said trench has a depth of between approximately 1.5 microns and approximately 2.0 microns.

8. The structure of claim 1 wherein said second thickness of said silicon layer is between approximately 3000.0 Angstroms and approximately 6000.0 Angstroms.

9. The structure of claim 1 wherein said first thickness of said buried oxide layer is approximately 1.25 microns.

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Patent History
Patent number: 7338848
Type: Grant
Filed: Oct 20, 2004
Date of Patent: Mar 4, 2008
Assignee: Newport Fab, LLC (Newport Beach, CA)
Inventor: Paul H Kempf (Santa Ana, CA)
Primary Examiner: George R. Fourson
Assistant Examiner: John M. Parker
Attorney: Farjami & Farjami LLP
Application Number: 10/970,645