Abstract: The invented method and device provide a reliable contact to a passive device of a semiconductor circuit device, the passive device being, for example, a resistor, an inductor, a fuse or the like. Adjacent, spaced, elevated, so-called dummy pattern (shoulder) regions are formed under the portions of the passive device on which the contact hole is formed. The shoulder region is formed of the same material as the first conductive layer of the gate of the peripheral transistor. The electrode may be formed through the contact hole to be a reliable contact to the integrated passive device.

Abstract: A reference voltage supply circuit is provided with a PNP transistor. The PNP transistor has an N-type well for a base formed at a surface of a P-type semiconductor substrate. The reference voltage supply circuit is further provided with a resistor element connected to an emitter of the PNP transistor. The resistor element has an N-type well for a resistor at the surface of the P-type semiconductor substrate. The well is fabricated at the same time as when the N-type well for a base is fabricated.

Abstract: The present invention provides an integrated circuit, comprising a semiconductor substrate, an active element formed on the side of one main surface of the semiconductor substrate, an insulating region formed on the side of the main surface of the semiconductor substrate by burying an insulating material in a groove having a depth of at least 20 &mgr;m, and a passive element formed directly or indirectly on the insulating region. It is desirable for the passive element to be an inductor.

Abstract: A thin-film resistor includes a resistive element with a predetermined length and width deposited on a substrate. An insulator layer is patterned so as to cover all of the resistive element except the ends in the width direction and is tapered. Electrodes are connected to respective ends of the resistive element via a plating base layer. The electrodes have a reduced resistance. The thin-film resistor can exhibit high accuracy and a small range of variation of the resistance.

Abstract: The integrated inductor comprises a coil of metal which is formed in the second metal level. The coil is supported by a bracket extending above spaced from a semiconductor material body by an air gap obtained by removing a sacrificial region formed in the first metal level. The bracket is carried by the semiconductor material body through support regions which are arranged peripherally on the bracket and are separated from one another by through apertures which are connected to the air gap. A thick oxide region extends above the semiconductor material body, below the air gap, to reduce the capacitive coupling between the inductor and the semiconductor material body. The inductor thus has a high quality factor, and is produced by a process compatible with present microelectronics processes.

Abstract: A high surface area capacitor comprising a double metal layer of an electrode metal and a barrier material deposited on hemispherical grain (HSG) silicon and a high dielectric constant (HDC) material deposited over the double metal layer. An upper cell plate electrode is deposited over the HDC material. The double metal layer preferably comprises one noble metal for the electrode metal and an oxidizable metal for the barrier material. The noble metal alone would normally allow oxygen to diffuse into and oxidize any adhesion layer and/or undesirably oxidize any silicon-containing material during the deposition of the HDC material. The barrier metal is used to form a conducting oxide layer or a conducting layer which stops the oxygen diffusion. The HSG polysilicon provides a surface roughness that boosts cell capacitance. The HDC material is also used to boost cell capacitance.

Abstract: A semiconductor device includes a semiconductor substrate on which a circuit element forming region and a plurality of connection pads are formed, a first columnar electrode which is formed on a first connection pad so as to be electrically connected to the first connection pad, a first conductive layer which is formed on a second connection pad so as to be electrically connected to the second connection pad, an encapsulating film which is formed at least around the first columnar electrode, on the semiconductor substrate and on the first conductive layer, and a second conductive layer which is formed on the encapsulating film so as to face the first conductive layer. A passive element is formed from the first and second conductive layers.

Abstract: A multilayer wiring substrate has a passive circuit element disposed on an insulating base substrate, and an insulating layer is disposed on the insulating base substrate with the passive circuit element interposed therebetween. The insulating layer is formed to have via holes for exposing specific portions of the passive circuit element, and a terminal electrodes are disposed in the via holes. Accordingly, the entire area of the multilayer wiring substrate can be reduced, and cracks caused by residual stress produced by a firing step can be prevented.

Abstract: A multistack 3-D semiconductor structure comprising a first level structure comprising a first semiconductor substrate and first active devices; and a second level structure comprising a SOI semiconductor structure bonded to the first level structure and further comprising second active devices; and wherein the first active devices are more heat tolerant than the second active devices is provided along with a method for its fabrication.

Abstract: A semiconductor device includes a first insulating film comprising an opening, a capacitor formed at a selected position in the opening, a second insulating film formed at least in the opening, and a third insulating film formed on the second insulating film.

Abstract: An inductor obtained by laminating a plurality of ceramic layers having an internal coil conductor, and a thermistor obtained by laminating a plurality of ceramic layers having internal electrodes and having a predetermined resistance-temperature characteristic are laminated via an intermediate insulating layer. Both ends of the internal coil conductor of the inductor and the internal electrodes of the thermistor are connected to a pair of external electrodes. Thus, the inductor and the thermistor are connected in parallel.

Abstract: A spherical semiconductor device 1a comprises three spherical semiconductors 10, 20 and 30, which are connected together. An electronic circuit is formed on the surface of the central spherical semiconductor 10, among the three spherical semiconductors, while a coil 21 and a capacitor 31 are formed on the respective surfaces of the other spherical semiconductors 20 and 30, respectively. Since the spherical semiconductors 20 and 30 at the opposite ends are independent of the central spherical semiconductor 10, an insulating film on the coil 21 never influences the properties of the electronic circuit of the central spherical semiconductor 10, and the capacitor 31 can secure a capacity large enough to maintain satisfactory operating power for the spherical semiconductor device 1a. Since the three spherical semiconductors 10, 20 and 30 are manufactured in different processes, moreover, the productivity of the spherical semiconductors cannot be lowered by differences between manufacturing processes.

Abstract: Inductor losses to a semiconducting substrate are eliminated in an IC structure by etching a well into the substrate down to the insulating layer coating the substrate and fabricating a grounded Faraday shield in the shape of elongated segments in the bottom of the well. The well lies directly below the inductor and is optionally filled with cured low-k organic dielectric or air.

Abstract: A metal capacitor formed as part of metal dual damascene process in the BEOL, of a wafer. A lower plate (27) of the capacitor is sandwiched between an insulating layer (25) and a dielectric layer (29). The insulating layer on an opposite side abuts a layer of metalization (23, 24) and the dielectric layer separates the lower plate of the capacitor from an upper plate (59) of the capacitor. A portion (27A) of the lower plate projects into a via (37) adjacent to it that is filled with copper (63). The via projects up to a common surface with the upper plate but is electrically isolated form the upper plate. The via also extends down to the layer of metalization.

Abstract: The present invention provides a method for fabricating a high-Q inductance device. First, a first dielectric layer is formed on a semiconductor substrate. A spiral conducting line is formed above the first dielectric layer. Then, a passivation layer is formed above the spiral conducting line and the first dielectric layer, such that a spiral air gap is formed in the passivation layer within the space around the spiral conducting line. Finally, the inductance device is immersed in an acid solution so as to increase the size of the spiral air gap. When an additional dielectric layer and spiral conducting line are formed between the first dielectric layer and the passivation layer, the air gap can be formed not only in the passivation layer, but also in the additional dielectric layer. Therefore, the inductance device of the present invention can have a plurality of air gaps that are formed in the passivation layer or formed in both of the passivation layer and the dielectric layers.

Abstract: A unitary-formed electrode structure serving as both a collector and a polarization electrode includes an electrically conductive base serving as the collector, and a polarization electrode that includes a multiplicity of separate polarization particles dispersed throughout the base and exposed in at least a part of a surface of the base.

Abstract: Methods of forming capacitors and resultant capacitor structures are described. In one embodiment, a capacitor storage node layer is formed over a substrate and has an uppermost rim defining an opening into an interior volume. At least a portion of the rim is capped by forming a material which is different from the capacitor storage node layer over the rim portion. After the rim is capped, a capacitor dielectric region and a cell electrode layer are formed over the storage node layer. In another embodiment, a capacitor storage node layer is formed within a container which is received within an insulative material. A capacitor storage node layer is formed within the container and has an outer surface. A layer of material is formed within less than the entire capacitor container and covers less than the entire capacitor storage node layer outer surface. The layer of material comprises a material which is different from the insulative material within which the capacitor container is formed.

Abstract: A method of manufacturing a semiconductor device comprising a poly-emitter transistor (1) and a capacitor (2). A base electrode (14), a first electrode (16, 37) and an emitter window (18) are formed at the same time in a first polysilicon layer (13) covered with an insulating layer (25). Subsequently, the side walls of the electrodes (20, 39) and the wall (23) of the emitter window are covered at the same time with insulating spacers (22, 44) by depositing a layer of an insulating material, followed by an anisotropic etching process. The base (8) of the transistor is formed by ion implantation. The emitter (9) is formed by diffusion, from an emitter electrode (30) formed in a second polysilicon layer. Preferably, the first electrode of the capacitor consists of mutually connected strips (37).

Abstract: It is an object of the present invention to provide a semiconductor device capable of decreasing electric resistance of a lower electrode provided therein, as well as capable of accurately responding to external signals having high frequencies inputted therein. The lower electrode 7 consists of three layers such as a silicon lower electrode layer 7a made of poly-crystalline silicon, a tungsten-silicide layer 7b made of tungsten silicide as a chemical compound of tungsten and silicon, and a protection layer 7c made of poly-crystalline silicon. By constructing the semiconductor device as described above, oxidation of the tungsten-silicide layer 7b may be prevented by the protection layer 7c made of poly-crystalline silicon even when oxidation layers of an ONO (silicon oxidation) layer 11 is formed by thermal oxidation. Consequently, electric resistance of the lower electrode 7 can be decreased.

Abstract: The present invention discloses a simple and convenient method for fabricating a capacitor device with BiCMOS processes. An electrode of the capacitor device formed according to the present invention is an ion doping region formed in an epitaxy layer so that the thickness of the dielectric layer of the capacitor device decreased relative to a specific ion concentration. Accordingly, the capacitor device formed therein has a high capacitance and good performance.

Abstract: A cavity structure formed in a semiconductor substrate and under a device formation region on which a device if formed. The cavity structure has supporting pillars providing the device formation region with mechanical strength.

Abstract: An integrated circuit and method of fabrication are disclosed for achieving electrical isolation between a spiral inductor and an underlying silicon substrate using standard semiconductor manufacturing process flow. A spiral conductor with square windings is formed in metal layer (20) patterned so that straight runs of successive turns (22, 23, 24) overlie corresponding runs of concentric square rings (16, 17, 18) formed in underlying metal layer (14). A unity gain voltage buffer (30) connects each ring (16, 17, 18) with a respective overlying turn (22, 23, 24).

Abstract: A method for fabricating a resistive load static random access memory (SRAM) capable of providing a high resistive load without local resistance variation, includes a step of forming an isolated layer on a semiconductor substrate having driver and access transistors provided thereto, a step of selectively etching said isolated layer to provide a butting contact region, a step of forming a doped polysilicon layer on a resulting structure, a step of selectively counter-doping said doped polysilicon layer, and a step of patterning said doped polysilicon layer to provide a power supply line, a butting contact and a high load resistor.

Abstract: A thin film resistor processing flow solves the problem of accurately incorporating the resistor (80) to be trimmed in an optimized multilayer stack (60,70). This is achieved by measuring the total thickness of the dielectric stack (60) between the silicon substrate and the top of the dielectric stack just prior to the formation of the thin film resistor (80). Then, the thickness of the dielectric stack (60) is adjusted (60+70) to be an odd integer number of laser quarter wavelengths. The thin film resistor (60) is then formed and overlying dielectric (120) is deposited. The thickness of the overlying dielectric (120) may likewise be adjusted (120+130) to be an odd integer number of laser quarter wavelengths.

Abstract: A semiconductor includes a buried conducting layer, such as a buried collector, comprises a trench, the walls of which are covered with a layer of a material in which dopant ions diffuse faster than in monocrystalline silicon. A contact area is doped in close proximity to the trench wall. The dopants will diffuse through the layer and form a low resistance connection to the buried layer. The layer may comprise polysilicon or porous silicon, or a silicide. If the material used in the layer is not in itself conducting, the size of the component may be significantly reduced.

Abstract: A method for forming a semiconductor device having a capacitor, a resistor and a MOS transistor with characteristics conforming to design. To this end, a polysilicon film (4), a capacitor-dielectric/insulating film (5), a polysilicon film (6) are deposited, and an upper electrode (7) of the capacitor is formed from the polysilicon film (6), and edge portions (7a) of the upper electrode (7) are oxidized. On top of this, an inorganic anti-reflection coating film (9) and a CAP oxide film (10) are deposited and etched to form a mask pattern (12) for forming the capacitor and the resistor. On the other hand, a tungsten silicide film (13), an inorganic anti-reflection coating film (14) and a CAP oxide film (15) are deposited and etched to form a mask pattern (17) for forming a gate electrode. The polysilicon film (4) is etched by using the mask patterns (12) and (17), leaving behind the tungsten silicide film (13) beneath the mask pattern 17.

Abstract: A method and apparatus for synthesizing high-frequency signals that overcomes integration problems while meeting demanding phase noise and other impurity requirements. In one embodiment, on-package oscillator circuit inductors are provided for band selection purposes, with no external package connection to connect off-package or external inductors to on-package inductance circuits. Multiple package electrical connection points may also be provided on-package to allow for selection of alternate oscillator inductance values during package assembly.

Abstract: A cavity structure formed in a semiconductor substrate and under a device formation region on which a device if formed. The cavity structure has supporting pillars providing the device formation region with mechanical strength.

Abstract: In one aspect, the invention provides a method of exposing a material from which photoresist cannot be substantially selectively removed utilizing photoresist. In one preferred implementation, a first material from which photoresist cannot be substantially selectively removed is formed over a substrate. At least two different material layers are formed over the first material. Photoresist is deposited over the two layers and an opening formed within the photoresist over an outermost of the two layers. First etching is conducted through the outermost of the two layers within the photoresist opening to outwardly expose an innermost of the two layers and form an exposure opening thereto. After the first etching, photoresist is stripped from the substrate. After the stripping, a second etching is conducted of the innermost of the two layers within the exposure opening.

Abstract: The structure of a high-Q inductor applied in a monolithic circuit according to the invention comprises a plurality of spiral metal lines and a plurality of dielectric layers, each dielectric layer formed between two adjacent spiral metal lines. Furthermore, via plugs are formed in each dielectric layer to electrically connect two adjacent spiral metal lines. A spiral air trench is formed along the spacing of the spiral metal lines in the dielectric layers. Therefore, the 3D-structure of the inductor of the invention can greatly reduce the series resistance thereof without widening the spiral metal lines. In addition, the spiral air trench, filled with air which has a lower dielectric constant, can efficiently reduce the parasitic capacitance between the spacing of the spiral metal lines. As a result, the inductor of the invention has a higher quality factor at a proper RF operating frequency region.

Abstract: A spiral inductor fabricated above a semiconductor substrate provides a large inductance while occupying only a small surface area. Including a layer of magnetic material above and below the inductor increases the inductance of the inductor. The magnetic material also acts as barrier that confines electronic noise generated in the spiral inductor to the area occupied by the spiral inductor. Inductance in a pair of stacked spiral inductors is increased by including a layer of magnetic material between the stacked spiral inductors.

Abstract: An inductive component includes a substrate on the surface of which is a lower insulation layer having a shallow concavity or trench, a first plurality of conductive elements formed in the trench, a magnetic core formed over the first plurality of conductive elements, and a second plurality of conductive elements formed over the core. The first and second pluralities of conductive elements are connected to each other so as to form an inductive coil around the core. First and second core insulation layers are disposed between the core and the first and second pluralities of conductive elements, respectively. The component is fabricated by a method in which it is built up in the trench using thin film techniques. A first array of conductors is patterned over the lower insulation layer, and a first core insulation layer is applied over the first conductor array. A magnetic core is formed on top of the first core insulation layer, and a second core insulation layer is applied over the core.

Abstract: An improved RC network integrated circuit semiconductor device is disclosed which incorporates an improved method for fabrication. The new device and method includes the use of a tantalum nitride layer as the resistive material for the resistor and a protective metal layer formed between the resistive layer and a metal interconnect layer. The capacitor uses a metal electrode as one plate of the capacitor and a heavily doped semiconductor region as the other plate of the capacitor and separated from the one plate of the capacitor by a silicon nitride insulation layer.

Abstract: The present invention provides a thin-film resistor positioned on a semiconductor wafer and its method of formation. The thin-film resistor comprises a dielectric layer, a resistance layer, a protective layer, an insulating layer and two conductive layers. The dielectric layer is positioned on the semiconductor wafer. The resistance layer is positioned in a predetermined area of the dielectric layer. The protective layer positioned on the resistance layer comprises two openings formed above two ends of the resistance layer by using the wet-etching process. The insulating layer positioned on the protective layer comprises two openings on the two openings of the protective layer by using the dry-etching process. The two conductive layers are separately positioned in the two openings of the protective layer and the insulating layer to connect two ends of the resistance layer and function as two electrical terminals.

Abstract: A semiconductor device having a capacitor, a bipolar transistor and complementary MOSFETs on a semiconductor substrate, the capacitor being constituted from a first electrode 8, a second electrode 13 separated from the first electrode by an insulating film 11 and a third electrode 15 separated from the second electrode by another insulating film 14 and connected to the first electrode is manufactured; where all electrodes in the capacitor and insulating films between them are formed simultaneously with other manufacturing steps of a bipolar transistor or the MOSFETs. This manufacturing method can produce a semiconductor device such as a Bi—CMOS and the like, which is capable of large scale integration and has a capacitor with a large capacitance but occupying only a small area, with a high efficiency and a low cost.

Abstract: The present invention relates to a method of manufacturing a capacitor in a BICMOS integrated circuit manufacturing technology, including the steps of depositing, on a thick oxide region, a polysilicon layer corresponding to a MOS transistor gate electrode; successively depositing a base polysilicon layer and a silicon oxide layer; forming an opening in these last two layers; performing a thermal anneal in an oxidizing atmosphere; depositing a silicon nitride layer and a spacer polysilicon layer; depositing an emitter polysilicon layer; and making a contact with the base polysilicon layer and a contact with the emitter polysilicon layer.

Abstract: A method to manufacture a laminated chip capacitor by laminating and bonding elementary body sheets 14a, 14b which have via holes 17a, 17b and internal electrodes 11a, 11b, and are made of an insulating material, external electrode sheets 15a, 15b which are made of an insulating material, and a dummy sheet 16 which has via hole 17a and is made of an insulating material, treating the sheets to eliminate a binder, and calcining the sheets. This method allows the external electrode sheets 15a, 15b to form external terminal electrodes by themselves, thereby permitting the external terminal electrodes to be formed extremely easily only on two end surfaces of an elementary body opposed to each other.

Abstract: The monolithic inductor (30) includes a substrate (38), a spiral metal trace (32) disposed insulatively above the substrate (38), where a parasitic capacitance (56) is generated between the spiral metal trace (32) and the substrate (38), and a depletion layer is generated under the spiral metal trace (32) with a depletion junction capacitance (58) coupled in series with the parasitic capacitance (56). The overall capacitance is thus reduced, which enhances the self-resonance frequency of the inductor (30). For the same self-resonance frequency, a thicker metal trace may be used to implement the inductor, resulting in an improved quality factor, Q.

Abstract: The dynamic range is increased and the noise level is reduced in a bipolar-based active pixel sensor cell with a capacitively coupled base region by forming the capacitor over a portion of the base region and the field oxide region of the cell. In addition, the noise levels are also reduced by heavily-doping the material which forms a portion of the bottom plate of the capacitor with the same conductivity type as the base region of the cell, and by placing the material which forms the portion of the bottom plate in direct contact with the base region.

Abstract: A high-resistance polycrystalline Si resistor having a stable resistance value even when micro-sized and a low-resistance polycrystalline Si resistor having a sufficiently low desired resistance value wherein a polycrystalline Si film is formed on an insulation film located on a Si substrate, high-resistance-making ion implantation is applied to the entire surface and medium-resistance-making ion implantation is selectively applied to a medium-resistance-making region of the polycrystalline Si film. Low-resistance-making ion implantation is selectively applied to a low-resistance-making region of the polycrystalline Si film. The product is annealed to grow the polycrystalline Si film by solid-phase growth, the film is patterned to form a high-resistance polycrystalline Si resistor, medium-resistance polycrystalline Si resistor, and low-resistance polycrystalline Si resistor.

Abstract: A fabrication method for a capacitor having high capacitance that increases capacitance of a capacitor and consequently decreases defective semiconductor devices includes: forming a doped first polysilicon layer pattern on a semiconductor substrate; forming a silicide film pattern on the first polysilicon layer pattern; annealing the semiconductor substrate; sequentially forming a first insulating film and a second insulating film over the silicide film pattern; forming a contact hole to expose a portion of the silicide film pattern and then sequentially placing the semiconductor substrate in an etchant solution and a buffered etchant solution to remove a portion of the first insulating film formed on the silicide film pattern; forming a first capacitor electrode on a portion of an upper surface of the second insulating film pattern and the silicide film pattern, and at inner walls of the contact hole; and forming a dielectric layer on an outer surface of the lower electrode and then a second capacitor electr

Abstract: A semiconductor IC including a resistance element on a circuit substrate. The resistance element includes a resistance layer formed on an insulating layer. The resistance layer is formed using a Si layer obtained by forming an a-Si layer, doping the a-Si layer with impurities, and heating the doped a-Si layer to diffuse the impurities while substantially preserving the fineness of the a-Si layer surface. Preferably, a SiN layer is provided lying beneath the resistance layer. A capacitor may be integrated on the same circuit substrate where the resistance element is formed. In this case, a lower electrode, a SiN dielectric layer, and an upper electrode are formed in this order to constitute a capacitor. The SiN dielectric layer of the capacitor is formed extending from a capacitor formation region to another region, so that the resistance layer of the resistance element is formed on the extending SiN dielectric layer.

Abstract: A method of making a resistor begins with forming a field effect transistor on a silicon semiconductor substrate. Then a first insulating layer is deposited on the field effect transistor. The first insulating layer is etched by the photolithography and etching techniques to form a bit line contact, and a bit line is subsequently formed. Next, upon the entire structure, a second insulating layer is formed and etched by the photolithography and ion etching techniques to form a contact hole with high aspect ratio. A polysilicon layer is deposited across the contact hole and the polysilicon outside the contact hole is removed, forming a polysilicon plug in the contact hole. Then, a third insulating layer is formed and etched to form a contact hole for metallurgy. After a first metal interconnection is formed, a third insulating layer is formed upon the entire structure and then etched to form a via hole by the photolithography and plasma etching techniques.

Abstract: A diffusion resistor is provided that utilizes the block mask to cover only the intrinsic polysilicon gate region. The n-type source/drain doping is implanted in the contact regions, but not in the intrinsic polysilicon gate region. A N-type (or P-type) diffusion resistor in P-well (or N-well) is provided that utilizes a block mask to cover only the intrinsic polysilicon gate region. The N-type (or P-type) source/drain doping is implanted in the contact regions but not in the intrinsic polysilicon gate region. The P-well (or N-well) block mask is used to keep the P-well (or N-well) from forming under the buried resistor. This makes the parasitic capacitance of the diffusion junction very low. Also provided is a buried capacitor and method of making both a buried resistor and a buried capacitor.

Abstract: A method of forming a flower shaped capacitor for a DRAM over a bitline is disclosed. The method comprises the steps of: forming a first polysilicon layer over said bitline; forming a TEOS layer over said first polysilicon layer, patterning and etching an opening through said TEOS layer; depositing a second polysilicon layer; etching back said second polysilicon layer and the first polysilicon layer to form sidewall spacers in said opening; using the first polysilicon layer and sidewall spacers as a mask, etching through to said bitline and thereby removing said TEOS layer; depositing a third polysilicon layer; patterning and etching the third polysilicon layer to form a bottom storage node of the capacitor; and forming a dielectric layer and a top conductive layer over the bottom storage node.

Abstract: Method for fabricating an inductor on a semiconductor substrate including a cell region in a semiconductor device is disclosed, including the steps of forming impurity diffusion regions having a predetermined diffusion depth and spaced away from one another by a predetermined distance beneath surface of a semiconductor substrate; selectively oxidizing the semiconductor substrate in a direction crossing the impurity diffusion regions to form an inductor core layer; and forming a polysilicon layer on the entire surface including the inductor core layer and selectively patterning the polysilicon layer to form a plurality of polysilicon pattern layers each connecting with one of ends of the impurity diffusion regions with an opposite end of the adjacent impurity diffusion region so as to form an inductor coil layer electronically connecting the impurity diffusion regions.

Abstract: The present invention provides a method for producing a semiconductor laser device having at least a light emitting section, a cap layer and an electrode successively formed on a semiconductor substrate, the light emitting section including a light emitting layer located approximately in a middle of a thickness of the device. The method includes the step of growing the light emitting section and the cap layer using a vapor phase epitaxy method, wherein a growth rate of the cap layer is greater than a growth rate of the light emitting section.

Abstract: A method of forming an SRAM cell includes, a) providing a pair of pull-down gates having associated transistor diffusiion regions operatively adjacent thereto, one of the diffusion regions of each pull-down gate being electrically connected to the other pull-down gate; b) providing a pair of pull-up resistor nodes for electrical connection with a pair of respective pull-up resistors, the pull-up nodes being in respective electrical connection with one of the pull-down diffusion regions and the other pull-down gate; c) providing a first electrical insulating layer outwardly of the reistor nodes; d) providing a pair of contact openings, with respective width, through the first insulating layer to the pair of resistor nodes; e) providing a second electrical insulating layer over the first layer and to within the pair of contact openings to a thickness which is less than one-half the open widths; f) anisotropically etching the second electrical insulating layer to define respective electrical insulating annulus s

Abstract: A method for manufacturing an optoelectronic integrated circuit including a photo diode for transforming light into electric signals, an HBT for amplifying said electric signals from said photo diode, a capacitor, and a resistor is disclosed. An HBT including an emitter, a base, and a collector on a predetermined location of a semiconductor substrate, and a photo diode including an N type metal, non doped layer, and a P type metal are formed. A lower electrode of a capacitor is formed on the semiconductor substrate located in a place separated by a predetermined space from said photo diode. A SiN film is deposited over the surface of the resulting structure of the semiconductor substrate. The above described SiN film is patterned to exist only on the surfaces of the HBT, photo diode, lower electrode, and semiconductor substrate separated from the lower electrode by a predetermined space. Furthermore, a resistor is formed on the SiN film existing on a predetermined surface of the semiconductor substrate.

Abstract: A silicon oxide film is formed on a wire array by CVD employing a gas mixture composed of a gas containing silicon atoms and hydrogen peroxide, and the thickness of the silicon oxide film in the region apart from the wire array is formed to be at least 50% of the wire thickness. Planarization of the silicon oxide film over the wire array region is attained.