Graded Composition Patents (Class 438/37)
  • Patent number: 9425583
    Abstract: An aluminium gallium indium phosphide (AlGaInP)-based semiconductor laser device is provided. On a main surface of a semiconductor substrate formed of n-type GaAs (gallium arsenide), from the bottom layer, an n-type buffer layer, an n-type cladding layer formed of an AlGaInP-based semiconductor containing silicon (Si) as a dopant, an active layer, a p-type cladding layer formed of an AlGaInP-based semiconductor containing magnesium (Mg) or zinc (Zn) as a dopant, an etching stopper layer, and a p-type contact layer are formed. Here, when an Al composition ratio x of the AlGaInP-based semiconductor is taken as a composition ratio of Al and Ga defined as (AlxGa1?x)0.5In0.5P, a composition of the n-type cladding layer is expressed as (AlxnGa1?xn)0.5In0.5P (0.9<xn<1) and a composition of the p-type cladding layer is expressed as (AlxpGa1?xp)0.5In0.5P (0.9<xp?1), and xn and xp satisfy a relationship of xn<xp.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: August 23, 2016
    Assignee: USHIO OPTO SEMICONDUCTORS, INC.
    Inventors: Masato Hagimoto, Haruki Fukai, Tsutomu Kiyosumi, Shinji Sasaki, Satoshi Kawanaka
  • Patent number: 9136430
    Abstract: A method of manufacturing a semiconductor device includes forming a silicon substrate, forming a buffer layer on the silicon substrate, and forming a nitride semiconductor layer on the buffer layer. The buffer layer includes a first layer, a second layer, and a third layer. The first layer includes AlxInyGa1-x-yN (0?x?1, 0?y?1, 0?x+y?1) and has a lattice constant LP1 that is smaller than a lattice constant LP0 of the silicon substrate. The second layer is formed on the first layer, includes AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1), and has a lattice constant LP2 that is greater than LP1 and smaller than LP0. The third layer is formed on the second layer, includes AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1), and has a lattice constant LP3 that is smaller than LP2.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: September 15, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-jo Tak, Jae-kyun Kim, Joo-sung Kim, Jun-youn Kim, Jae-won Lee, Hyo-ji Choi
  • Publication number: 20150108426
    Abstract: In at least one embodiment, the method is designed to produce an active zone for an optoelectronic semiconductor chip and comprises the following steps: growing a fourth barrier layer (24) based on Alx4Iny4Ga1-x4-y4N where 0?x4?0.40 and on average 0<y4?0.4, wherein the In content increases along a growth direction (z), growing a quantum well layer (20) on the fourth barrier layer (24), wherein the quantum well layer (20) is based on InyGa1-yN where 0.08?y?0.35, growing a first barrier layer (21) based on Alx1Iny1Ga1-x1-y1N where 0?x1?0.40 and on average 0<y1?0.4 onto the quantum well layer (20), wherein the In content decreases along the growth direction (z), growing a second barrier layer (22) based on GaN onto the first barrier layer (21), and growing a third barrier layer (23) based on GaN onto the second barrier layer (22), wherein the third barrier layer (23) is grown with the addition of H2 gas.
    Type: Application
    Filed: May 3, 2013
    Publication date: April 23, 2015
    Applicant: OSRAM Opto Semiconductors GmbH
    Inventors: Joachim Hertkorn, Thomas Lehnhardt, Marcus Eichfelder, Jan-Philipp Ahl
  • Patent number: 9012886
    Abstract: According to one embodiment, a semiconductor light emitting device includes: a first semiconductor layer; a second semiconductor layer; and a light emitting layer provided between the first and the second semiconductor layers. The first semiconductor layer includes a nitride semiconductor, and is of an n-type. The second semiconductor layer includes a nitride semiconductor, and is of a p-type. The light emitting layer includes: a first well layer; a second well layer provided between the first well layer and the second semiconductor layer; a first barrier layer provided between the first and the second well layers; and a first Al containing layer contacting the second well layer between the first barrier layer and the second well layer and containing layer containing Alx1Ga1-x1N (0.1?x1?0.35).
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jongil Hwang, Shinji Saito, Rei Hashimoto, Shinya Nunoue
  • Patent number: 9012252
    Abstract: This invention is about a method to be used in the fabrication of an electroluminescent diode and a diode fabricated with this method. The temperatures needed for the crystalline LEDs produced presently under specified temperatures in a furnace, will be provided within the semiconductor by the Joule effect. As an alternative to the commercial LEDs, whose costs are suitable only when they are produced in the order of centimeters, our process renders the fabrication of LEDs over very large surfaces of the order of meters, with the temperature raised by applying electric current without any requirements of high temperature furnace treatments. The effects of the chemical processes experienced during the Joule heating are permanent and the diode is able to luminesce.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: April 21, 2015
    Inventors: Mustafa Anutgan, Bayram Katircioglu, Tamila Anutgan, Ismail Atilgan
  • Publication number: 20150084088
    Abstract: Disclosed is a light-emitting diode with an n-type graded buffer layer and a manufacturing method therefor. An epitaxial structure of a light-emitting diode comprises: a growth substrate; an n-type graded buffer layer located on the growth substrate; an n-type limiting layer (231) located on the n-type graded buffer layer; an active layer (232) located on the n-type limiting layer (231); and a p-type limiting layer (233) located on the active layer (232). A buffer layer is converted into an n-type graded buffer layer by means of an ion implantation method, and is applied to a light-emitting diode chip of a vertical structure while ensuring that a high-quality epitaxial structure is obtained, thereby being able to effectively reduce the contact resistance.
    Type: Application
    Filed: March 19, 2013
    Publication date: March 26, 2015
    Inventors: Shaohua Huang, Jyh-Chiarng Wu
  • Publication number: 20150083994
    Abstract: Heterostructures for use in optoelectronic devices are described. One or more parameters of the heterostructure can be configured to improve the reliability of the corresponding optoelectronic device. The materials used to create the active structure of the device can be considered in configuring various parameters the n-type and/or p-type sides of the heterostructure.
    Type: Application
    Filed: September 23, 2014
    Publication date: March 26, 2015
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Maxim S. Shatalov, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 8981340
    Abstract: A nitride semiconductor device according to the present invention includes a p-type nitride semiconductor layer, an n-type nitride semiconductor layer, and an active layer interposed between the p-type nitride semiconductor layer and the n-type nitride semiconductor layer. The p-type nitride semiconductor layer includes: a first p-type nitride semiconductor layer containing Al and Mg; and a second p-type nitride semiconductor layer containing Mg. The first p-type nitride semiconductor layer is located between the active layer and the second p-type nitride semiconductor layer, and the second p-type nitride semiconductor layer has a greater band gap than a band gap of the first p-type nitride semiconductor layer.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: March 17, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Yasutoshi Kawaguchi, Toshitaka Shimamoto, Akihiko Ishibashi, Isao Kidoguchi, Toshiya Yokogawa
  • Publication number: 20150053920
    Abstract: A lighting emitting diode including: an n side layer and a p side layer formed by nitride semiconductors respectively; an active layer comprising a nitride semiconductor is between the n side layer and the p side layer; wherein, the n-side layer is successively laminated by an extrinsically-doped buffer layer and a compound multi-current spreading layer; the compound multi-current spreading layer is successively-laminated by a first current spreading layer, a second current spreading layer and a third current spreading layer; the first current spreading layer and the third current spreading layer are alternatively-laminated layers comprising a u-type nitride semiconductor layer and an n-type nitride semiconductor layer; the second current spreading layer is a distributed insulation layer formed on the n-type nitride semiconductor layer; and the first current spreading layer is adjacent to the extrinsically-doped buffer layer; and the third current spreading layer is adjacent to the active layer.
    Type: Application
    Filed: November 3, 2014
    Publication date: February 26, 2015
    Applicant: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: MENG-HSIN YEH, JYH-CHIARNG WU
  • Patent number: 8963122
    Abstract: In a semiconductor light emitting element outputting light indicating green color by using a group III nitride semiconductor, light emission output is improved. A semiconductor light emitting element includes: an n-type cladding layer containing n-type impurities (Si); a light emitting layer laminated on the n-type cladding layer; and a p-type cladding layer containing p-type impurities and laminated on the light emitting layer. The light emitting layer has a barrier layer including first to fifth barrier layers and a well layer including first to fourth well layers, and has a multiple quantum well structure to sandwich one well layer by two barrier layers. The light emitting layer is configured such that the first to fourth well layers are set to have a composition to emit green light, and the first barrier layer is doped with n-type impurities, whereas the other barrier layers are not doped with n-type impurities.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: February 24, 2015
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Katsuki Kusunoki, Hisao Sato
  • Patent number: 8951829
    Abstract: Methods, devices, and systems associated with oxide based memory can include a method of forming a resistive switching region of a memory cell. Forming a resistive switching region of a memory cell can include forming a metal oxide material on an electrode and forming a metal material on the metal oxide material, wherein the metal material formation causes a reaction that results in a graded metal oxide portion of the memory cell.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: February 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: D.V. Nirmal Ramaswamy, Gurtej S. Sandhu
  • Patent number: 8946764
    Abstract: A GaN-based semiconductor element which can suppress a leakage current generated during reverse bias application, an optical device using the same, and an image display apparatus using the optical device are provided. The GaN-based semiconductor element has a first GaN-based compound layer including an n-type conductive layer; a second GaN-based compound layer including a p-type conductive layer; and an active layer provided between the first GaN-based compound layer and the second GaN-based compound layer. In this GaN-based semiconductor element, the first GaN-based compound layer includes an underlayer having an n-type impurity concentration in the range of 3×1018 to 3×1019/cm3, and when a reverse bias of 5 V is applied, a leakage current density, which is the density of a current flowing per unit area of the active layer, is 2×10?5 A/cm2 or less.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: February 3, 2015
    Assignee: Sony Corporation
    Inventors: Goshi Biwa, Ippei Nishinaka, Hiroyuki Okuyama
  • Publication number: 20150021558
    Abstract: An organic light-emitting diode includes a first electrode, an intermediate layer on the first electrode, and a second electrode on the intermediate layer. The intermediate layer includes an emission layer including an organic material, and a functional layer between the second electrode and the emission layer and including at least one of a metal compound and a semiconductor compound including at least one of an oxygen atom and a sulfur atom. An oxygen concentration in the functional layer increases toward the second electrode, and a sulfur concentration in the functional layer increases toward the emission layer.
    Type: Application
    Filed: November 13, 2013
    Publication date: January 22, 2015
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ji-Hwang Lee, Eui-Gyu Kim, A-Rong Lee, Yool-Guk Kim, Seok-Soon Back
  • Patent number: 8932888
    Abstract: A method of applying a conversion means to an optoelectronic semiconductor chip includes preparing the optoelectronic semiconductor chip having a main radiation face, preparing the conversion means, the conversion means being applied to a main carrier face of a carrier, arranging the conversion means such that it faces the main radiation face and has a spacing relative to the main radiation face, and releasing the conversion means from the carrier and applying the conversion means to the main radiation face by irradiation and heating of an absorber constituent of the conversion means and/or of a release layer located between the conversion means and the carrier with a pulsed laser radiation which passes through the carrier.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: January 13, 2015
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Ralph Wagner
  • Publication number: 20140374700
    Abstract: A semiconductor light-emitting diode, including: an n-GaN layer, a quantum well layer, an electron blocking layer, and a p-GaN layer, which are sequentially stacked on a substrate. The electron blocking layer includes at least one first AlGaN layer and at least one second AlGaN layer. The first AlGaN layer and the second AlGaN layer are alternately stacked. The adjacent first and second AlGaN layers have different Al component.
    Type: Application
    Filed: September 6, 2014
    Publication date: December 25, 2014
    Inventors: Wenbing LI, Jiangbo WANG, Binzhong DONG, Chunyan YANG
  • Publication number: 20140339598
    Abstract: The present invention relates to a nitride-semiconductor light-emitting element in which a p-type nitride layer is doped with carbon, and to a production method therefor. More specifically, the present invention relates to a nitride-semiconductor light-emitting element comprising a p-type nitride layer formed from a nitride having a high concentration of free holes as the carbon is auto-doped in accordance with adjustment of the rate of flow of a nitrogen source. The nitride-semiconductor light-emitting element of the present invention can provide a high free-hole concentration, which is difficult to achieve with conventional single p-type dopants, and can therefore lower the resistance and increase the light efficiency of the light-emitting element.
    Type: Application
    Filed: December 27, 2012
    Publication date: November 20, 2014
    Applicant: ILJIN LED CO.,LTD.
    Inventors: Jung-Won Park, Sung-Hak Yi, Tae-Wan Kwon
  • Patent number: 8890114
    Abstract: A light-emitting device comprises a first semiconductor layer; a second semiconductor layer; an active layer formed between the first semiconductor layer and the second semiconductor layer; a first electron blocking layer formed between the first semiconductor layer and the active layer; and a second electron blocking layer formed between the second semiconductor layer and the active layer, wherein the thickness of the second electron blocking layer is not equal to that of the first electron blocking layer, and/or the band gap energy of the second electron blocking layer is not equal to that of the first electron blocking layer.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: November 18, 2014
    Assignee: Epistar Corporation
    Inventors: Sheng-Horng Yen, Ta-Cheng Hsu
  • Patent number: 8860044
    Abstract: A nitride light-emitting diode is provided including a current spreading layer. The current spreading layer includes a first layer having a plurality of distributed insulating portions configured to have electrical current flow therebetween; and a second layer including interlaced at least one substantially undoped nitride semiconductor layer and at least one n-type nitride semiconductor layer configured to spread laterally the electrical current from the first layer.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: October 14, 2014
    Assignee: Xiamen Sanan Optoelectronics Technology Co., Ltd.
    Inventors: Meng-hsin Yeh, Jyh-Chiamg Wu, Shao-hua Huang, Chi-lun Chou, Hsing-wei Lu, Kechuang Lin
  • Patent number: 8859313
    Abstract: A method for manufacturing a semiconductor light emitting element (1) which includes a first step of forming a first n-type semiconductor layer (12c) on a substrate (11) and a second step of sequentially forming a regrowth layer (12d) of the first n-type semiconductor layer (12c), a second n-type semiconductor layer (12b), a light emitting layer (13), and a p-type semiconductor layer (14) on the first n-type semiconductor layer (12c). In the step of forming the second n-type semiconductor layer (12b), a step (1) of supplying Si less than that forming the regrowth layer (12d) as a dopant to form a first layer of the second n-type semiconductor layer and a step (2) of supplying the Si more than that in the step (1) to form a second layer of the second n-type semiconductor layer are performed in this order.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: October 14, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Hiromitsu Sakai
  • Patent number: 8828765
    Abstract: A method (50) is provided for processing a graded-density AR silicon surface (14) to provide effective surface passivation. The method (50) includes positioning a substrate or wafer (12) with a silicon surface (14) in a reaction or processing chamber (42). The silicon surface (14) has been processed (52) to be an AR surface with a density gradient or region of black silicon. The method (50) continues with heating (54) the chamber (42) to a high temperature for both doping and surface passivation. The method (50) includes forming (58), with a dopant-containing precursor in contact with the silicon surface (14) of the substrate (12), an emitter junction (16) proximate to the silicon surface (14) by doping the substrate (12). The method (50) further includes, while the chamber is maintained at the high or raised temperature, forming (62) a passivation layer (19) on the graded-density silicon anti-reflection surface (14).
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: September 9, 2014
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Hao-Chih Yuan, Howard M. Branz, Matthew R. Page
  • Patent number: 8822250
    Abstract: Certain embodiments provide a method for manufacturing a semiconductor light emitting device, including: providing a first stack film on a first substrate, the first stack film being formed by stacking a p-type nitride semiconductor layer, an active layer having a multiquantum well structure of a nitride semiconductor, and an n-type nitride semiconductor layer in this order; forming an n-electrode on an upper face of the n-type nitride semiconductor layer; and forming a concave-convex region on the upper face of the n-type nitride semiconductor layer by performing wet etching on the upper face of the n-type nitride semiconductor layer with the use of an alkaline solution, except for a region in which the n-electrode is formed.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: September 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kotaro Zaima, Toru Gotoda, Toshiyuki Oka, Shinya Nunoue
  • Patent number: 8796674
    Abstract: Provided is a method of manufacturing an organic electronic device, wherein an organic electronic device that controls the injection and mobility of carriers in an organic charge transport layer thereof is manufactured by laminating organic layers comprising the same charge transportable organic compound, when manufacturing the organic electronic device with the coating method.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: August 5, 2014
    Assignee: Konica Minolta Holdings, Inc.
    Inventors: Shun Furukawa, Tomoyuki Nakayama, Hiroshi Ishidai
  • Publication number: 20140191193
    Abstract: Disclosed are a nitride semiconductor light-emitting element having a superior current spreading effect as a result of using a current spreading part containing current spreading impurities, and a method for manufacturing same. The nitride semiconductor light-emitting element according to the present invention comprises: an n-type nitride layer; a current spreading part, which is formed from nitride comprising current spreading impurities, and which is disposed on the n-type nitride layer; an activation layer disposed on the current spreading part; and a p-type nitride layer disposed on the activation layer, wherein the current spreading impurities comprise carbon (C).
    Type: Application
    Filed: August 2, 2012
    Publication date: July 10, 2014
    Applicant: ILJIN LED CO., LTD.
    Inventors: Won-Jin Choi, Jung-Won Park
  • Patent number: 8772066
    Abstract: Methods and apparatus for encapsulating organic light emitting diode (OLED) structures disposed on a substrate using a hybrid layer of material are provided. The processing parameters used during deposition of the hybrid layer of material allow control of the characteristics of the deposited hybrid layer. The hybrid layer may be deposited such that the layer has characteristics of an inorganic material in some sublayers of the hybrid layer and characteristics of an organic material in other sublayers of the hybrid layer. Use of the hybrid material allows OLED encapsulation using a single hard mask for the complete encapsulating process with low cost and without alignment issues present in conventional processes.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: July 8, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Jrjyan Jerry Chen, Soo Young Choi
  • Patent number: 8772623
    Abstract: Low bandgap, monolithic, multi-bandgap, optoelectronic devices (10), including PV converters, photodetectors, and LED's, have lattice-matched (LM), double-heterostructure (DH), low-bandgap GaInAs(P) subcells (22, 24) including those that are lattice-mismatched (LMM) to InP, grown on an InP substrate (26) by use of at least one graded lattice constant transition layer (20) of InAsP positioned somewhere between the InP substrate (26) and the LMM subcell(s) (22, 24). These devices are monofacial (10) or bifacial (80) and include monolithic, integrated, modules (MIMs) (190) with a plurality of voltage-matched subcell circuits (262, 264, 266, 270, 272) as well as other variations and embodiments.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: July 8, 2014
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Mark W. Wanlass, Jeffrey J. Carapella
  • Publication number: 20140183446
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting layer. The p-type semiconductor layer includes a first p-side layer, a second p-side layer, and a third p-side layer. A concentration profile of Mg of a p-side region includes a first portion, a second portion, a third portion, a fourth portion, a fifth portion, a sixth portion and a seventh portion. The p-side region includes the light emitting layer, the second p-side layer, and the third p-side layer. A Mg concentration of the sixth portion is not less than 1×1020 cm?3 and not more than 3×1020 cm?3. The Al concentration is 1/100 of the maximum value at a second position. A Mg concentration at the second position is not less than 2×1018 cm?3.
    Type: Application
    Filed: December 2, 2013
    Publication date: July 3, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hajime NAGO, Yoshiyuki HARADA, Shigeya KIMURA, Hisashi YOSHIDA, Shinya NUNOUE
  • Publication number: 20140167097
    Abstract: A method of fabricating an optoelectronic device comprising, providing a substrate, wherein the substrate comprises a first major surface and a second major surface opposite to the first major surface; forming a semiconductor epitaxial stack on the first major surface including a first conductive-type semiconductor layer having a first doping concentration, an active layer, and a second conductive-type semiconductor layer wherein the semiconductor epitaxial stack having four boundaries and a geometric center; and forming a plurality of the hollow components in the first conductive-type semiconductor layer wherein the plurality of the hollow components is formed from the boundary of the semiconductor epitaxial stack to the geometric center of the semiconductor epitaxial stack.
    Type: Application
    Filed: December 12, 2013
    Publication date: June 19, 2014
    Applicant: EPISTAR CORPORATION
    Inventors: HSIN-HSIEN WU, YU-YAO LIN, YEN-CHIH CHEN, CHIEN-YUAN TSENG, CHUN-TA YU, CHENG-HSIUNG YEN, SHIH-CHUN LING, TSUN-KAI KO, DE-SHAN KUO
  • Publication number: 20140162388
    Abstract: A method for producing light emission from a semiconductor structure, including the following steps: providing a semiconductor structure that includes a semiconductor base region of a first conductivity type and having a relatively long minority carrier diffusion length characteristic, between a semiconductor emitter region of a second conductivity type opposite to that of the first conductivity type, and a semiconductor drain region of the second conductivity type; providing, between the base region and the drain region, a semiconductor auxiliary region of the first conductivity type and having a relatively short minority carrier diffusion length characteristic; providing, within the base region, a region exhibiting quantum size effects; providing an emitter electrode coupled with the emitter region; providing a base/drain electrode coupled with the base region and the drain region; and applying signals with respect to the emitter and base/drain electrodes to obtain light emission from the semiconductor stru
    Type: Application
    Filed: December 2, 2013
    Publication date: June 12, 2014
    Applicant: Quantum Electro Opto Systems Sdn. Bhd.
    Inventor: Gabriel Walter
  • Publication number: 20140158981
    Abstract: A multiple quantum well structure for an ultraviolet light-emitting diode, comprising: an Alx1Ga1-x1N barrier portion comprising an AlN barrier atomic layer and a GaN barrier atomic layer, which are alternately arranged; and an Alx2Ga1-x2N quantum well portion formed on the Alx1Ga1-x1N barrier portion and comprising an AlN well atomic layer and a GaN well atomic layer, which are alternately arranged, wherein the Al composition ratio (x1) of the Alx1Ga1-x2N barrier portion is 0-0.7, the Al composition ratio (x2) of the Alx2Ga1-x2N quantum well portion is 0-0.7, the Al composition ratio (x1) of the Alx1Ga1-x1N barrier portion is greater than the Al composition ratio (x2) of the Alx2Ga1-x2N quantum well portion, and the Alx1Ga1-x1N barrier portion and the Alx2Ga1-x2N quantum well portion are alternately deposited two or more times.
    Type: Application
    Filed: July 16, 2012
    Publication date: June 12, 2014
    Applicant: CHIP TECHNOLOGY CO., LTD
    Inventors: Byoung-Gu Cho, Jae-Sik Min, Se-Hun Kwon
  • Patent number: 8716752
    Abstract: A graded SiGe sacrificial layer is epitaxially grown overlying a silicon substrate. A single crystal silicon layer is then grown by an epitaxial process overlying the graded SiGe layer. A SiGe layer is next grown by an epitaxial process as a single crystal layer overlying the silicon layer. A subsequent silicon layer, which becomes the active silicon layer for the transistors, is epitaxially grown overlying the second silicon germanium layer. Together the epitaxially grown Si, SiGe and Si layers form a laminate semiconductor structure. A MOS transistor is then formed on the active area of the single crystal silicon. The graded SiGe sacrificial layer is removed by an etch process to electrically isolate the laminate semiconductor structure from the substrate.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: May 6, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: Barry Dove
  • Patent number: 8698126
    Abstract: In the nitride semiconductor device of the present invention, an active layer 12 is sandwiched between a p-type nitride semiconductor layer 11 and an n-type nitride semiconductor layer 13. The active layer 12 has, at least, a barrier layer 2a having an n-type impurity, a well layer 1a made of a nitride semiconductor that includes In; and a barrier layer 2c that has a p-type impurity, or that has been grown without being doped. An appropriate injection of carriers into the active layer 12 becomes possible by arranging the barrier layer 2c nearest to the p-type layer side.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: April 15, 2014
    Assignee: Nichia Corporation
    Inventor: Tokuya Kozaki
  • Patent number: 8697465
    Abstract: An LED epitaxial structure includes a substrate, a buffer layer and an epitaxial layer. The buffer layer is grown on a top surface of the substrate, and the epitaxial layer is formed on a surface of the buffer layer. The epitaxial layer has a first n-type epitaxial layer and a second n-type epitaxial layer. The first n-type epitaxial layer is formed between the buffer layer and the second n-type epitaxial layer. The first n-type epitaxial layer has a plurality of irregular holes therein.
    Type: Grant
    Filed: November 20, 2011
    Date of Patent: April 15, 2014
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Po-Min Tu, Shih-Cheng Huang
  • Patent number: 8686455
    Abstract: A composite substrate for the formation of a light-emitting device, ensuring that a high-quality nitride-based light-emitting diode can be easily formed on its top surface and the obtained substrate-attached light-emitting diode functions as a light-emitting device capable of emitting light for an arbitrary color such as white, is provided.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: April 1, 2014
    Assignees: Ube Industries, Ltd., Riken
    Inventors: Yasuyuki Ichizono, Hideki Hirayama
  • Patent number: 8685772
    Abstract: There is provided a method of manufacturing a light emitting diode and a light emitting diode manufactured by the same. The method includes growing a first conductivity type nitride semiconductor layer and an undoped nitride semiconductor layer on a substrate sequentially in a first reaction chamber; transferring the substrate having the first conductivity type nitride semiconductor layer and the undoped nitride semiconductor layer grown thereon to a second reaction chamber; growing an additional first conductivity type nitride semiconductor layer on the undoped nitride semiconductor layer in the second reaction chamber; growing an active layer on the additional first conductivity type nitride semiconductor layer; and growing a second conductivity type nitride semiconductor layer on the active layer.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: April 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Ju Lee, Heon Ho Lee, Hyun Wook Shim, Young Sun Kim
  • Publication number: 20140077239
    Abstract: According to one embodiment, a semiconductor device includes a functional layer of a nitride semiconductor. The functional layer is provided on a nitride semiconductor layer including a first stacked multilayer structure provided on a substrate. The first stacked multilayer structure includes a first lower layer, a first intermediate layer, and a first upper layer. The first lower layer contains Si with a first concentration and has a first thickness. The first intermediate layer is provided on the first lower layer to be in contact with the first lower layer, contains Si with a second concentration lower than the first concentration, and has a second thickness thicker than the first thickness. The first upper layer is provided on the first intermediate layer to be in contact with the first intermediate layer, contains Si with a third concentration lower than the second concentration, and has a third thickness.
    Type: Application
    Filed: February 28, 2013
    Publication date: March 20, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hung HUNG, Naoharu Sugiyama, Hisashi Yoshida, Toshiki Hikosaka, Yoshiyuki Harada, Shinya Nunoue
  • Patent number: 8659071
    Abstract: The invention provides a SONOS structure, a manufacturing method thereof and a semiconductor device with the SONOS structure. The SONOS structure comprises: a first tunneling oxide layer formed on a substrate, a charge storage silicon nitride layer, a second silicon oxide layer, a thin graded silicon nitride layer having graded Si/N content formed on the second silicon oxide layer, a third silicon oxide layer formed on the thin graded silicon nitride layer, and a polysilicon control gate. The Si/N content ratio of the silicon nitride of the thin graded silicon nitride layer increases gradually, wherein the silicon nitride of the graded silicon nitride layer closer to the second silicon oxide layer contains higher nitride content, and the silicon nitride of the graded silicon nitride layer closer to the third silicon oxide layer contains higher silicon content.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: February 25, 2014
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventor: Zhi Tian
  • Patent number: 8658446
    Abstract: Presented is a method for fabricating a semiconductor substrate. The method includes implanting impurity material into the semiconductor substrate, and forming a reflective layer-like zone in the semiconductor substrate that includes the impurity material.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: February 25, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Volker Härle
  • Patent number: 8652862
    Abstract: A method for etching an insulating film includes the steps of forming an insulating film; forming a first resin layer composed of a non-silicon-containing resin on the insulating film; forming a pattern including projections and recesses in the first resin layer; forming a second resin layer composed of a silicon-containing resin to cover the projections and the recesses of the pattern in the first resin layer; etching the second resin layer by reactive ion etching with etching gas containing CF4 gas and oxygen gas until the projections of the first resin layer are exposed, a Si component of the second resin layer being oxidized in etching the second resin layer; selectively etching the first resin layer until the insulating film is exposed using as a mask the second resin layer buried in the recesses of the first resin layer to form a resin layer mask; and etching the insulating film using the resin layer mask.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: February 18, 2014
    Assignee: Sumitomo Electronic Industries Ltd.
    Inventor: Yukihiro Tsuji
  • Publication number: 20140045284
    Abstract: A method of manufacturing a semiconductor device includes forming a silicon substrate, forming a buffer layer on the silicon substrate, and forming a nitride semiconductor layer on the buffer layer. The buffer layer includes a first layer, a second layer, and a third layer. The first layer includes AlxInyGa1-x-yN (0?x?1, 0?y?1, 0?x+y?1) and has a lattice constant LP1 that is smaller than a lattice constant LP0 of the silicon substrate. The second layer is formed on the first layer, includes AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1), and has a lattice constant LP2 that is greater than LP1 and smaller than LP0. The third layer is formed on the second layer, includes AlxInyGa1-x-yN (0?x<1, 0?y<1, 0?x+y<1), and has a lattice constant LP3 that is smaller than LP2.
    Type: Application
    Filed: August 9, 2013
    Publication date: February 13, 2014
    Inventors: Young-jo TAK, Jae-kyun KIM, Joo-sung KIM, Jun-youn KIM, Jae-won LEE, Hyo-ji CHOI
  • Publication number: 20140030835
    Abstract: A semiconductor structure includes a photonic modulator and a field effect transistor on a same substrate. The photonic modulator includes a modulator semiconductor structure and a semiconductor contact structure employing a same semiconductor material as a gate electrode of a field effect transistor. The modulator semiconductor structure includes a lateral p-n junction, and the semiconductor contact structure includes another lateral p-n junction. To form this semiconductor structure, the modulator semiconductor structure in the shape of a waveguide and an active region of a field effect transistor region can be patterned in a semiconductor substrate. A gate dielectric layer is formed on the modulator semiconductor structure and the active region, and is subsequently removed from the modulator semiconductor structure.
    Type: Application
    Filed: August 15, 2012
    Publication date: January 30, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Solomon Assefa, William M. J. Green, Marwan H. Khater, Yurii A. Vlasov
  • Patent number: 8618551
    Abstract: According to one embodiment, a semiconductor light emitting device includes a substrate, a first electrode, a first conductivity type layer, a light emitting layer, a second conductivity type layer and a second electrode. The first conductivity type layer includes a first contact layer, a window layer having a lower impurity concentration than the first contact layer and a first cladding layer. The second conductivity type layer includes a second cladding layer, a current spreading layer and a second contact layer. The second electrode includes a narrow-line region on the second contact layer and a pad region electrically connected to the narrow-line region. Band gap energies of the first contact and window layers are larger than that of the light emitting layer. The first contact layer is provided selectively between the window layer and the first electrode and without overlapping the second contact layer as viewed from above.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: December 31, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukie Nishikawa, Hironori Yamasaki, Katsuyoshi Furuki, Takashi Kataoka
  • Patent number: 8586859
    Abstract: A method of forming a plurality of discrete, interconnected solar cells mounted on a carrier by providing a first semiconductor substrate; depositing on the first substrate a sequence of layers of semiconductor material forming a solar cell structure; forming a metal back contact layer over the solar cell structure; mounting a carrier on top of the metal back contact; removing the first substrate; and lithographically patterning and etching the solar cell structure to form a plurality of discrete solar cells mounted on the carrier.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: November 19, 2013
    Assignee: Emcore Solar Power, Inc.
    Inventor: Tansen Varghese
  • Patent number: 8587004
    Abstract: A semiconductor light emitting device made of nitride III-V compound semiconductors including an active layer made of a first nitride III-V compound semiconductor containing In and Ga, such as InGaN; an intermediate layer made of a second nitride III-V compound semiconductor containing In and Ga and different from the first nitride III-V compound semiconductor, such as InGaN; and a cap layer made of a third nitride III-V compound semiconductor containing Al and Ga, such as p-type AlGaN, which are deposited in sequential contact.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: November 19, 2013
    Assignee: Sony Corporation
    Inventors: Osamu Goto, Takeharu Asano, Yasuhiko Suzuki, Motonobu Taketani, Katsuyoshi Shibuya, Takashi Mizuno, Tsuyoshi Tojo, Shiro Uchida, Masao Ikeda
  • Patent number: 8575593
    Abstract: A semiconductor light emitting device and a fabrication method thereof are provided. The semiconductor light emitting device includes: first and second conductivity-type semiconductor layers; and an active layer disposed between the first and second conductivity-type semiconductor layers and having a structure in which a quantum barrier layer and a quantum well layer are alternately disposed, and the quantum barrier layer includes first and second regions disposed in order of proximity to the first conductivity-type semiconductor layer.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: November 5, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Heon Han, Jong Hyun Lee, Jin Young Lim, Dong Ju Lee, Heon Ho Lee, Young Sun Kim, Sung Tae Kim
  • Patent number: 8575011
    Abstract: A semiconductive device is fabricated by forming, within a semiconductive substrate, at least one continuous region formed of a material having a non-uniform composition in a direction substantially perpendicular to the thickness of the substrate.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: November 5, 2013
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Daniel-Camille Bensahel, Yves Morand
  • Publication number: 20130260500
    Abstract: This invention is about a method to be used in the fabrication of an electroluminescent diode and a diode fabricated with this method. The temperatures needed for the crystalline LEDs produced presently under specified temperatures in a furnace, will be provided within the semiconductor by the Joule effect. As an alternative to the commercial LEDs, whose costs are suitable only when they are produced in the order of centimeters, our process renders the fabrication of LEDs over very large surfaces of the order of meters, with the temperature raised by applying electric current without any requirements of high temperature furnace treatments. The effects of the chemical processes experienced during the Joule heating are permanent and the diode is able to luminesce.
    Type: Application
    Filed: November 2, 2011
    Publication date: October 3, 2013
    Inventors: Mustafa Anutgan, Bayram Katircioglu, Tamila Anutgan, Ismail Atilgan
  • Patent number: 8530255
    Abstract: A method of manufacturing a semiconductor laser having an end face window structure, by growing over a substrate a nitride type Group III-V compound semiconductor layer including an active layer including a nitride type Group III-V compound semiconductor containing at least In and Ga. The method includes the steps of forming a mask including an insulating film over the substrate, at least in the vicinity of the position of forming the end face window structure; and growing the nitride type Group III-V compound semiconductor layer including the active layer over a part, not covered with the mask, of the substrate.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: September 10, 2013
    Assignee: Sony Corporation
    Inventors: Masaru Kuramoto, Eiji Nakayama, Yoshitsugu Ohizumi, Tsuyoshi Fujimoto
  • Publication number: 20130228791
    Abstract: A semiconductor light emitting device includes a first conductive semiconductor layer including a V-shaped recess in a cross-sectional view. An active layer is disposed on the first conductive semiconductor layer, conforming to the shape of the V-shaped recess. An intermediate layer is disposed on the active layer and is doped with a first impurity. A second conductive semiconductor layer is disposed on the intermediate layer. The intermediate layer includes a first intermediate layer and a second intermediate layer. The first intermediate layer is disposed on the active layer, conforming to the shape of the V-shape recess. The second intermediate layer is disposed on the first intermediate layer and includes a protrusion to fill the V-shaped recess.
    Type: Application
    Filed: March 4, 2013
    Publication date: September 5, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joo Young Cheon, Yu Ri Sohn
  • Publication number: 20130223463
    Abstract: A nitride semiconductor device according to the present invention includes a p-type nitride semiconductor layer, an n-type nitride semiconductor layer, and an active layer interposed between the p-type nitride semiconductor layer and the n-type nitride semiconductor layer. The p-type nitride semiconductor layer includes: a first p-type nitride semiconductor layer containing Al and Mg; and a second p-type nitride semiconductor layer containing Mg. The first p-type nitride semiconductor layer is located between the active layer and the second p-type nitride semiconductor layer, and the second p-type nitride semiconductor layer has a greater band gap than a band gap of the first p-type nitride semiconductor layer.
    Type: Application
    Filed: April 4, 2013
    Publication date: August 29, 2013
    Applicant: Panasonic Corporation
    Inventor: Panasonic Corporation
  • Patent number: 8518285
    Abstract: A substrate section for a flexible display device is disclosed. The substrate section includes: a first substrate, a second substrate disposed above a center region of the first substrate, a reinforcing layer disposed between the first and second substrates, configured to reinforce adhesion between the first and second substrates, and a barrier layer disposed above the second substrate and surrounding side surfaces of the second substrate and of the reinforcing layer.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: August 27, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventor: Dong-Beom Lee