Graded Composition Patents (Class 438/37)
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Patent number: 7495314Abstract: An ohmic contact in accordance with the invention includes a layer of p-type GaN-based material. A first layer of a group II-VI compound semiconductor is located adjacent to the layer of p-type GaN-based material. The ohmic contact further includes a metal layer that provides metal contact. A second layer of a different II-VI compound semiconductor is located adjacent to the metal layer.Type: GrantFiled: September 26, 2005Date of Patent: February 24, 2009Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.Inventors: Jeffrey N. Miller, David P. Bour, Virginia M. Robbins, Steven D. Lester
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Patent number: 7482183Abstract: An electronic device includes a conductive n-type substrate, a Group III nitride active region, an n-type Group III-nitride layer in vertical relationship to the substrate and the active layer, at least one p-type layer, and means for providing a non-rectifying conductive path between the p-type layer and the n-type layer or the substrate. The non-rectifying conduction means may include a degenerate junction structure or a patterned metal layer.Type: GrantFiled: January 22, 2007Date of Patent: January 27, 2009Assignee: Cree, Inc.Inventors: John A. Edmond, Kathleen M. Doverspike, Michael J. Bergmann, Hua-Shuang Kong
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Patent number: 7479658Abstract: A technique for suppressing the bowing of an epitaxial wafer is provided. The epitaxial wafer is prepared by successively epitaxially growing a target group III-nitride layer, an interlayer and another group III-nitride layer on a substrate with a buffer layer. The interlayer is mainly composed of a mixed crystal of GaN and InN expressed in a general formula (GaxIny)N (0?x?1, 0?y?1, x+y=1) (or a crystal of GaN), and does not contain Al. The interlayer is epitaxially formed at a lower growth temperature than those of the group III-nitride layers, more specifically at a temperature in a range of at least 350° C. to not more than 1000° C.Type: GrantFiled: August 2, 2004Date of Patent: January 20, 2009Assignee: NGK Insulators, Ltd.Inventors: Masahiro Sakai, Mitsuhiro Tanaka, Takashi Egawa
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Publication number: 20080315244Abstract: Provided are a light emitting diode (LED) and a method for manufacturing the same. The LED includes an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The active layer includes a well layer and a barrier layer that are alternately laminated at least twice. The barrier layer has a thickness at least twice larger than a thickness of the well layer.Type: ApplicationFiled: June 11, 2008Publication date: December 25, 2008Applicant: SEOUL OPTO DEVICE CO., LTD.Inventors: Hwa Mok KIM, Duck Hwan Oh, Dae Won Kim, Dae Sung Kal
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Patent number: 7449353Abstract: Semi-insulating Group III nitride layers and methods of fabricating semi-insulating Group III nitride layers include doping a Group III nitride layer with a shallow level p-type dopant and doping the Group III nitride layer with a deep level dopant, such as a deep level transition metal dopant. Such layers and/or method may also include doping a Group III nitride layer with a shallow level dopant having a concentration of less than about 1×1017 cm?3 and doping the Group III nitride layer with a deep level transition metal dopant. The concentration of the deep level transition metal dopant is greater than a concentration of the shallow level p-type dopant.Type: GrantFiled: September 18, 2006Date of Patent: November 11, 2008Assignee: Cree, Inc.Inventor: Adam William Saxler
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Patent number: 7437047Abstract: Photosensitive optical materials are used for establishing more versatile approaches for optical device formation. In some embodiments, unpatterned light is used to shift the index-of-refraction of planar optical structures to shift the index-of-refraction of the photosensitive material to a desired value. This approach can be effective to produce cladding material with a selected index-of-refraction. In additional embodiments gradients in index-of-refraction are formed using photosensitive materials. In further embodiments, the photosensitive materials are patterned within the planar optical structure. Irradiation of the photosensitive material can selectively shift the index-of-refraction of the patterned photosensitive material. By patterning the light used to irradiate the patterned photosensitive material, different optical devices can be selectively activated within the optical structure.Type: GrantFiled: April 30, 2007Date of Patent: October 14, 2008Assignee: NeoPhotonics CorporationInventors: Michael A. Bryan, Nobuyuki Kambe
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Patent number: 7399657Abstract: Ball grid array packages for semiconductor die include a thermally conductive container and a substrate that substantially enclose a semiconductor die. The die is positioned with respect to the container by thermally conductive supports formed in the container or attached to the container. The die contacts the supports so that the die and the container form a cavity that is at least partially filled with a thermally conductive material such as a conductive epoxy to promote thermal conduction between the die and the container. The die electrically connects to the substrate with bond wires that extend through an aperture in the substrate and attach to bond pads provided on the substrate. The aperture is typically filled with a protective layer of resin, epoxy, or other material that also encapsulates the bond wires.Type: GrantFiled: July 31, 2002Date of Patent: July 15, 2008Assignee: Micron Technology, Inc.Inventors: Todd O. Bolken, Chad A. Cobbley
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Publication number: 20080142781Abstract: Provided is a nitride semiconductor light emitting device including: a first nitride semiconductor layer; an active layer formed above the first nitride semiconductor layer; and a delta doped second nitride semiconductor layer formed above the active layer. According to the present invention, the optical power of the nitride semiconductor light emitting device is enhanced, optical power down phenomenon is improved and reliability against ESD (electro static discharge) is enhanced.Type: ApplicationFiled: December 5, 2005Publication date: June 19, 2008Applicant: LG INNOTEK CO., LTD.Inventor: Suk Hun Lee
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Patent number: 7368308Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.Type: GrantFiled: September 15, 2005Date of Patent: May 6, 2008Assignee: AmberWave Systems CorporationInventors: Christopher Vineis, Vicky Yang, Matthew Currie, Richard Westhoff, Christopher Leitz
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Patent number: 7364697Abstract: Methods and apparatus for screening diverse arrays of materials using infrared imaging techniques are provided. Typically, each of the individual materials on the array will be screened or interrogated for the same material characteristic. Once screened, the individual materials may be ranked or otherwise compared relative to each other with respect to the material characteristic under investigation. According to one aspect, infrared imaging techniques are used to identify the active sites within an array of compounds by monitoring the temperature change resulting from a reaction. This same technique can also be used to quantify the stability of each new material within an array of compounds. According to another aspect, identification and characterization of condensed phase products is achieved, wherein library elements are activated by a heat source serially, or in parallel.Type: GrantFiled: January 27, 2005Date of Patent: April 29, 2008Assignee: Symyx Technologies, Inc.Inventors: Eric W. McFarland, William Archibald
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Publication number: 20080054279Abstract: A method of forming an LED lamp with a desired distribution of phosphor is disclosed. The method includes the steps of mixing a plurality of phosphor particles in an uncured polymer resin for which the viscosity can be controlled in response to temperature to form a substantially uniform suspension of the phosphor particles in the resin. The uncured resin is then placed into a defined position adjacent an LED chip and the temperature of the resin is increased to correspondingly decrease its viscosity but to less than the temperature at which the resin would cure unreasonably quickly. The phosphor particles are encouraged to settle in the lowered-viscosity resin to a desired position with respect to the LED chip, and the temperature of the resin is thereafter increased to the point at which it will cured and solidify.Type: ApplicationFiled: August 16, 2007Publication date: March 6, 2008Inventors: Christopher P. Hussell, Micheal J. Bergmann, Brian T. Collins, David T. Emerson
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Patent number: 7271021Abstract: A light emitting device includes a substrate, an epitaxial structure positioned on the substrate, an ohmic contact electrode positioned on the epitaxial structure and a current blocking structure positioned in the epitaxial structure. The epitaxial structure includes a bottom cladding layer, an upper cladding layer, a light-emitting layer positioned between the bottom and the upper cladding layer, a window layer positioned on the upper cladding layer and a contact layer positioned on the window layer. The current blocking structure can extend from the bottom surface of the ohmic contact electrode to the light-emitting layer. According to the present invention, at least one ionic implanting process is performed to implant at least one proton beam into the epitaxial structure to form the current blocking structure.Type: GrantFiled: September 28, 2005Date of Patent: September 18, 2007Assignee: Atomic Energy Council-Institute of Nuclear Energy ResearchInventors: Tsun-Neng Yang, Shan-Ming Lan
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Patent number: 7259036Abstract: Methods and apparatus are described for irradiating one or more substrate surfaces with accelerated gas clusters including strain-inducing atoms for blanket and/or localized introduction of such atoms into semiconductor substrates, with additional, optional introduction of dopant atoms and/or C. Processes for forming semiconductor films infused into and/or deposited onto the surfaces of semiconductor and/or dielectric substrates are also described. Such films may be doped and/or strained as well.Type: GrantFiled: February 14, 2005Date of Patent: August 21, 2007Assignee: TEL Epion Inc.Inventors: John O. Borland, John J. Hautala, Wesley J. Skinner, Martin D. Tabat
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Patent number: 7224882Abstract: Photosensitive optical materials are used for establishing more versatile approaches for optical device formation. In some embodiments, unpatterned light is used to shift the index-of-refraction of planar optical structures to shift the index-of-refraction of the photosensitive material to a desired value. This approach can be effective to produce cladding material with a selected index-of-refraction. In additional embodiments gradients in index-of-refraction are formed using, photosensitive materials. In further embodiments, the photosensitive materials are patterned within the planar optical structure. Irradiation of the photosensitive material can selectively shift the index-of-refraction of the patterned photosensitive material. By patterning the light used to irradiate the patterned photosensitive material, different optical devices can be selectively activated within the optical structure.Type: GrantFiled: July 15, 2003Date of Patent: May 29, 2007Assignee: NeoPhotonics CorporationInventors: Michael A. Bryan, Nobuyuki Kambe
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Patent number: 7214598Abstract: In order to reduce dislocation pile-ups in a virtual substrate, a buffer layer 32 is provided, between an underlying Si substrate 34 and an uppermost constant composition SiGe layer 36, which comprises alternating graded SiGe layers 38 and uniform SiGe layers 40. During the deposition of each of the graded SiGe layers 38 the Ge fraction x is linearly increased from a value corresponding to the Ge composition ratio of the preceding layer to a value corresponding to the Ge composition ratio of the following layer. Furthermore the Ge fraction x is maintained constant during deposition of each uniform SiGe layer 40, so that the Ge fraction x varies in step-wise fashion through the depth of the buffer layer. After the deposition of each pair of graded and uniform SiGe layers 38 and 40, the wafer is annealed at an elevated temperature greater than the temperature at which the layers have been deposited.Type: GrantFiled: May 30, 2003Date of Patent: May 8, 2007Assignee: AdvanceSis LimitedInventors: Adam Daniel Capewell, Timothy John Grasby, Evan Hubert Cresswell Parker, Terence Whall
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Patent number: 7211458Abstract: A method of fabricating a semiconductor device includes forming a strained first semiconductor layer on an insulating layer that is between second semiconductor layers. The strained first semiconductor layer may be epitaxially grown from the second semiconductor layers to extend onto the insulating layer between the second semiconductor layers. The second semiconductor layers have a lattice constant that is different than that of the first semiconductor layer, such that strain may be created in the first semiconductor layer. Related devices are also discussed.Type: GrantFiled: August 8, 2005Date of Patent: May 1, 2007Assignee: North Carolina State UniversityInventors: Mehmet Ozturk, Veena Misra, Saurabh Chopra
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Patent number: 7052931Abstract: A method of fabricating a flat panel display comprises forming a first electrode, forming at least one organic electroluminescent layer on the first electrode, forming an second electrode, wherein the first electrode comprises a first component of a transparent material and a second component of a metallic material, and the forming of the first electrode comprises depositing the first and second components so as to have a gradual concentration gradient in which the first component is decreased while the second component is increased at a part in contact with the exposed electrode, according to a thickness of the first electrode. The first electrode functions as a pixel electrode and a black matrix of the flat panel display.Type: GrantFiled: March 30, 2005Date of Patent: May 30, 2006Assignee: Samsung SDI Co., Ltd.Inventors: Jae-Bon Koo, Dong-Chan Shin
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Patent number: 7049627Abstract: Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading dislocations distributed substantially uniformly across its surface as a starting layer and/or at least one intermediate layer during growth and relaxation of the compositionally graded layer. The semiconductor layer may include a seed layer disposed proximal to the surface of the semiconductor layer and having the threading dislocations uniformly distributed therein.Type: GrantFiled: August 22, 2003Date of Patent: May 23, 2006Assignee: AmberWave Systems CorporationInventors: Christopher Vineis, Vicky Yang, Matthew Currie, Richard Westhoff, Christopher Leitz
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Patent number: 7042023Abstract: A semiconductor light emitting device includes a semiconductor substrate; a stacked semiconductor structure formed on the semiconductor substrate; a striped ridge structure; and a semiconductor current confinement layer provided on a side surface of the striped ridge structure. The stacked semiconductor structure includes a first semiconductor clad layer, a semiconductor active layer, a second semiconductor clad layer, and a semiconductor etching stop layer. The striped ridge structure includes a third semiconductor clad layer, a semiconductor intermediate layer, and a semiconductor cap layer. The striped ridge structure is provided on the semiconductor etching stop layer. An interface between the semiconductor current confinement layer and the semiconductor etching stop layer and an interface between the semiconductor current confinement layer and the striped ridge structure each have a content of impurities of less than 1×1017/cm3.Type: GrantFiled: July 22, 2003Date of Patent: May 9, 2006Assignee: Sharp Kabushiki KaishaInventor: Kentaro Tani
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Patent number: 7042011Abstract: A compound semiconductor laser of a III group nitride semiconductor of the present invention includes a first cladding layer 104 of a first conduction type formed on a substrate 101, an active layer 106 formed on the first cladding layer, a second cladding layer 108 of a second conduction type formed on the active layer 106, and a buried layer 110 formed on the second cladding layer 108, the buried layer having an opening portion for constricting a current in a selected region of the active layer, wherein an upper portion of the second cladding layer 108 has a ridge portion, the ridge portion residing in the opening portion of the buried layer 110, and the buried layer 110 does not substantially absorb light output from the active layer 106, and the buried layer has a refractive index which is approximately identical with that of the second cladding layer 108.Type: GrantFiled: November 18, 2004Date of Patent: May 9, 2006Assignee: Sharp Kabushiki KaishaInventor: Kunihiro Takatani
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Patent number: 7009224Abstract: A metamorphic device including a substrate structure upon which a semiconductor device can be formed. In the metamorphic device, a buffer layer matching a substrate lattice constant is formed at normal growth temperatures and a thin grading layer which grades past the desired lattice constant is configured at a low temperature. A reverse grading layer grades the lattice constant back to match a desired lattice constant. Thereafter, a thick layer is formed thereon, based on the desired lattice constant. Annealing can then occur to isolate dislocated material in at least the grading layer and the reverse grading layer. Thereon a strained layer superlattice is created upon which a high-speed photodiode or other semiconductor device can be formed.Type: GrantFiled: April 14, 2003Date of Patent: March 7, 2006Assignee: Finisar CorporationInventors: Ralph H. Johnson, James K. Guenter, James R. Biard
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Patent number: 7005681Abstract: A radiation-emitting semiconductor component having a semiconductor body (1), which has a radiation-generating active layer (9) and a p-conducting contact layer (2), which contains InGaN or AlInGaN and to which a contact metalization (3) is applied.Type: GrantFiled: August 30, 2002Date of Patent: February 28, 2006Assignee: Osram Opto Semiconductors GmbHInventors: Stefan Bader, Viorel Dumitru, Volker Härle, Bertram Kuhn, Alfred Lell, Jürgen Off, Ferdinand Scholz, Heinz Schweizer
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Patent number: 6962828Abstract: A novel light-emitting device includes a saphire substrate with a light-emitting layer comprising InXGa1?XN, where the critical value of the indium mole fraction X is determined by a newly derived relationship between the indium mole fraction X and the wavelength ? of emitted light.Type: GrantFiled: November 15, 2000Date of Patent: November 8, 2005Assignees: Toyoda Gosei Co., Ltd.Inventors: Norikatsu Koide, Masayoshi Koike, Shiro Yamasaki, Isamu Akasaki, Hiroshi Amano
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Patent number: 6888984Abstract: A photonic device suitable for being optically coupled to at least one optical fiber having a first spot-size, the device including: at least one photonic component; and, a graded index lens optically coupled between the at least one photonic component and the at least one optical fiber; wherein, the graded index lens is adapted to convert optical transmissions from the at least one photonic component to the first spot size.Type: GrantFiled: August 12, 2002Date of Patent: May 3, 2005Assignee: Sarnoff CorporationInventors: Joseph H. Abeles, Nagendranath Maley, Ralph Doud Whaley, Jr., Liyou Yang
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Patent number: 6881601Abstract: A nitride compound semiconductor light-emitting device having a stack of layers including an active layer for a light emitting device and a method of manufacturing the device is disclosed. The method includes the steps of growing a first layer on a substrate at a first temperature to obtain an incomplete crystalline structure including both indium and aluminum and having the composition expressed as InXAlYGa1-X-YN(0?X?1, 0?Y?1). The method grows a cap layer on the first layer to cover the first layer, with growth of the cap layer proceeding at a second temperature substantially equal to or below the first temperature. The first layer is heat treated at a third temperature above the first temperature to cause the incomplete crystalline structure to crystallize and to create areas of differing compositions, thus changing the first layer to an active layer. The material of the cap layer is selected to be heat stable during the heat-treating step.Type: GrantFiled: January 30, 2003Date of Patent: April 19, 2005Assignee: Kabushiki Kaisha ToshibaInventor: Hideto Sugawara
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Patent number: 6864115Abstract: A semiconductor structure and method of processing same including a substrate, a lattice-mismatched first layer deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, and a second layer deposited on the first layer with a greater lattice mismatch to the substrate than the first semiconductor layer. In another embodiment there is provided a semiconductor graded composition layer structure on a semiconductor substrate and a method of processing same including a semiconductor substrate, a first semiconductor layer having a series of lattice-mismatched semiconductor layers deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, a second semiconductor layer deposited on the first semiconductor layer with a greater lattice mismatch to the substrate than the first semiconductor layer, and annealed at a temperature greater than 100° C. above the deposition temperature of the second semiconductor layer.Type: GrantFiled: October 9, 2002Date of Patent: March 8, 2005Assignee: AmberWave Systems CorporationInventor: Eugene A. Fitzgerald
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Patent number: 6855570Abstract: A compound semiconductor laser of a III group nitride semiconductor of the present invention includes a first cladding layer 104 of a first conduction type formed on a substrate 101, an active layer 106 formed on the first cladding layer, a second cladding layer 108 of a second conduction type formed on the active layer 106, and a buried layer 110 formed on the second cladding layer 108, the buried layer having an opening portion for constricting a current in a selected region of the active layer, wherein an upper portion of the second cladding layer 108 has a ridge portion, the ridge portion residing in the opening portion of the buried layer 110, and the buried layer 110 does not substantially absorb light output from the active layer 106, and the buried layer has a refractive index which is approximately identical with that of the second cladding layer 108.Type: GrantFiled: June 18, 2003Date of Patent: February 15, 2005Assignee: Sharp Kabushiki KaishaInventor: Kunihiro Takatani
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Patent number: 6853011Abstract: A light emitting epi-layer structure contains a temporary substrate of absorption light type on one side. The other side thereof is then adhered to a transparent substrate of light absorption free by BCB bonding layer. After that, the light absorption substrate portion is removed. The resulted light emitting structure is then patterned to form a connection channel to connect the first ohmic contact electrode and form an isolation trench to separate the active layer of the light emitting structure into two parts. Thereafter, a second ohmic contact electrode on the cladding layer and a bonding metal layer filled in the first channel and on second ohmic contact electrode are successively formed. The resulted LED structure is hence convenient for flip-chip package since two bonding metal layers have the same altitude.Type: GrantFiled: January 30, 2003Date of Patent: February 8, 2005Assignee: United Epitaxy Co., Ltd.Inventor: Jin-Ywan Lin
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Patent number: 6841409Abstract: An AlGaInP layer is formed on a substrate made of GaAs, and an AlGaAs layer is formed on the AlGaInP layer via a buffer layer therebetween. The buffer layer has a thickness of about 1.1 nm and is made of AlGaInP whose Ga content is smaller than that of the AlGaInP layer. The buffer layer may alternatively be made of AlGaAs whose Al content is smaller than that of the AlGaAs layer.Type: GrantFiled: January 15, 2003Date of Patent: January 11, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Toshikazu Onishi
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Patent number: 6806502Abstract: Provide is a 3-5 group compound semiconductor having a concentration of a p-type dopant of 1×1017 cm− or more and 1×1021 cm−3 or less, which can be laminated to control the carrier concentration of an InGaAlN-type mixed crystal in a low range with high reproducibility. Also provided is a 3-5 group compound semiconductor in which the carrier concentration of an InGaAlN-type mixed crystal is controlled in a low range with high reproducibility, and a light emitting device having high light emitting efficiency.Type: GrantFiled: November 15, 2001Date of Patent: October 19, 2004Assignee: Sumitomo Chemical Company, LimtedInventors: Yasushi Iyechika, Yoshihiko Tsuchida, Yasuyuki Kurita
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Patent number: 6774389Abstract: A semiconductor optical device with improved optical gain and enhanced switching characteristics. The semiconductor optical device includes positive and negative electrodes for providing holes and electrons, respectively. The semiconductor optical device also includes an active layer between the positive and negative electrodes. The active layer includes a multiple quantum well structure having p-type quantum well layers and barrier layers. The quantum well layers are doped with an impurity that diffuses less than zinc so that trapping holes are produced and excessive electrons contributing no light emission are quenched by the trapping holes. The impurity can be beryllium, magnesium, or carbon.Type: GrantFiled: November 8, 2002Date of Patent: August 10, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Yoshihiko Hanamaki
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Publication number: 20040140477Abstract: A semiconductor light emitting device includes a semiconductor substrate; a stacked semiconductor structure formed on the semiconductor substrate; a striped ridge structure; and a semiconductor current confinement layer provided on a side surface of the striped ridge structure. The stacked semiconductor structure includes a first semiconductor clad layer, a semiconductor active layer, a second semiconductor clad layer, and a semiconductor etching stop layer. The striped ridge structure includes a third semiconductor clad layer, a semiconductor intermediate layer, and a semiconductor cap layer. The striped ridge structure is provided on the semiconductor etching stop layer. An interface between the semiconductor current confinement layer and the semiconductor etching stop layer and an interface between the semiconductor current confinement layer and the striped ridge structure each have a content of impurities of less than 1×1017/cm3.Type: ApplicationFiled: July 22, 2003Publication date: July 22, 2004Inventor: Kentaro Tani
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Patent number: 6759312Abstract: Non-alloyed, low resistivity contacts for semiconductors using Group III-V and Group II-VI compounds and methods of making are disclosed. Co-implantation techniques are disclosed.Type: GrantFiled: October 16, 2002Date of Patent: July 6, 2004Assignee: The Regents of the University of CaliforniaInventors: Wladyslaw Walukiewicz, Kin M. Yu
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Patent number: 6727109Abstract: The present invention relates to a method of fabricating vertical-cavity surface emitting lasers being watched as a light source for long wavelength communication. The present invention includes forming a layer having a high resistance near the surface by implanting heavy ions such as silicon (Si), so that the minimum current injection diameter is made very smaller unlike implantation of a proton. Further, the present invention includes regrowing crystal so that current can flow the epi surface in parallel to significantly reduce the resistance up to the current injection part formed by silicon (Si) ions. Therefore, the present invention can not only effectively reduce the current injection diameter but also significantly reduce the resistance of a device to reduce generation of a heat. Further, the present invention can further improve dispersion of a heat using InP upon regrowth and thus improve the entire performance of the device.Type: GrantFiled: July 31, 2002Date of Patent: April 27, 2004Assignee: Electronics and Telecommunications Research InstituteInventors: Young Gu Ju, Won Seok Han, O Kyun Kwon, Jae Heon Shin, Byueng Su Yoo, Jung Rae Ro
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Patent number: 6720196Abstract: A thin nitride-based semiconductor layer having a low dislocation density is formed by laterally growing a nitride-based semiconductor layer on the upper surface of an underlayer and forming quantum dots on the laterally grown nitride-based semiconductor layer. The number of dislocations is reduced by a single lateral growth and is further reduced due to a dislocation loop effect by the quantum dots, without repeating lateral growth.Type: GrantFiled: May 6, 2002Date of Patent: April 13, 2004Assignee: Sanyo Electric Co., Ltd.Inventors: Tatsuya Kunisato, Yasuhiko Nomura, Takashi Kano, Hiroki Ohbo, Masayuki Hata
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Patent number: 6716654Abstract: The present invention discloses a light-emitting diode with enhanced brightness and a method for fabricating the same. The light-emitting diode comprises: an epitaxial LED structure having at least one lighting-emitting active layer with a plurality of spacers inside the lighting-emitting active layer; at least one conductive contact, formed on the bottom surface where no spacer is formed inside the lighting-emitting active layer; a transparent material layer formed in the spacers; an adhesion layer formed between the transparent material layer and a permanent substrate; a bottom electrode formed on the bottom surface of the permanent substrate; and an opposed electrode formed on the top surface of the epitaxial LED structure.Type: GrantFiled: March 12, 2002Date of Patent: April 6, 2004Assignee: Opto Tech CorporationInventors: Jung-Kuei Hsu, Hsueh-Chih Yu, Chia-Liang Hsu, Hung-Yuan Lu, Yen-Hu Chu, Chui-Chuan Chang, Kwang-Ru Wang, Chang-Da Tsai, San Bao Lin, Yung-Chiang Hwang, Ming-Der Lin
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Patent number: 6716655Abstract: An object of the invention is to produce, at high efficiency, semiconductor elements which are formed of a high-quality crystalline semiconductor having no cracks and a low dislocation density and which have excellent characteristics. Specifically, a mask formed from SiO2 film is provided on the Si(111) plane of an n-type silicon substrate, and a window portion (crystal growth region) in the shape of an equilateral triangle having a side of approximately 300 &mgr;m is formed through the mask. The three sides of the equilateral triangle are composed of three edges; each edge defined by the (111) plane and another crystal plane that is cleavable. Subsequently, a multi-layer structure of semiconductor crystals in an LED is formed through crystal growth of a Group III nitride compound semiconductor. Thus, limiting the area of one crystal growth region to a considerably small area weakens a stress applied to a semiconductor layer, thereby readily producing semiconductor elements having excellent crystallinity.Type: GrantFiled: June 4, 2002Date of Patent: April 6, 2004Assignee: Toyoda Gosei Co., Ltd.Inventors: Seiji Nagai, Masayoshi Koike, Kazuyoshi Tomita
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Patent number: 6689626Abstract: The invention relates to a substrate comprising a glass sheet (1) having a thickness which is smaller than or equal to 0.1 mm, the glass sheet (1) being provided with a layer of a synthetic resin material (2) having a thickness which is smaller than or equal to that of the glass sheet (1). This substrate proves to be flexible. In addition, the substrate cracks less easily, so that it can be processed more readily. The substrate may be used, for example, in light-emitting devices, such as a poly-LED or PALC.Type: GrantFiled: July 10, 2001Date of Patent: February 10, 2004Assignee: Koninklijke Philips Electronics N.V.Inventors: Marcellinus P. C. M. Krijn, Marinus J. J. Dona, Johannes M. M. Swinkels, Jeroen J. M. Vleggaar
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Patent number: 6653158Abstract: A vertical cavity surface emitting laser (VCSEL) includes a semiconductor device having a pair of mirror portions, an active region, a tunnel junction, a pair of cladding layers and a substrate. Heat generated by the VCSEL dissipates through the cladding layers, which utilize an indium phosphide material. The VCSEL also includes selective etches that are used to aperture the active region to allow electric current to be injected into the active region.Type: GrantFiled: August 21, 2001Date of Patent: November 25, 2003Assignee: The Regents of the University of CaliforniaInventors: Eric M. Hall, Shigeru M. Nakagawa, Larry A. Coldren
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Publication number: 20030215971Abstract: A method and apparatus for fabricating a metamorphic long-wavelength, high-speed photodiode, wherein a buffer layer matching a substrate lattice constant is formed at normal growth temperatures and a thin grading region which grades past the desired lattice constant is configured at a low temperature. A reverse grade back is performed to match a desired lattice constant. Thereafter, a thick layer is formed thereon, based on the desired lattice constant. Annealing can then occur to isolate dislocated material in a grading layer and a reverse grading layer. Thereon a strained layer superlattice substrate is created upon which a high-speed photodiode can be formed. Implant or diffusion layers grown in dopants can be formed based on materials, such as Be, Mg, C, Te, Si, Se, Zn, or others. A metal layer can be formed over a cap above a P+ region situated directly over an N-active region. The active region also includes a p-doped region.Type: ApplicationFiled: April 14, 2003Publication date: November 20, 2003Inventors: Ralph H. Johnson, James K. Guenter, James R. Biard
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Patent number: 6627469Abstract: A lens is formed out of semiconductor material. The semiconductor produces light which is coupled to the lens. The lens focuses the light and also minimizes refractive reflection. The lens is formed by a graded aluminum alloy, which is oxidized in a lateral direction. The oxidation changes the effective shape of the device according to the grading.Type: GrantFiled: April 10, 2001Date of Patent: September 30, 2003Assignee: California Institute of TechnologyInventors: John O'Brien, Chuan-cheng Cheng, Axel Scherer, Amnon Yariv, Yong Xu
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Patent number: 6623998Abstract: A method of manufacturing a group III nitride compound semiconductor device, includes providing a substrate, forming a group III nitride compound semiconductor layer having a device function, and forming an undercoat layer between the substrate and the group III nitride semiconductor layer, the undercoat layer having a surface of a peak and trough structure.Type: GrantFiled: November 26, 2002Date of Patent: September 23, 2003Assignee: Toyoda Gosei Co., Ltd.Inventors: Naoki Shibata, Toshiaki Chiyo, Masanobu Senda, Jun Ito, Hiroshi Watanabe, Shinya Asami, Shizuyo Asami
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Patent number: 6617188Abstract: The present invention provides a novel technique based on gray scale mask patterning (110), which requires only a single lithography and etching step (110, 120) to produce different thickness of SiO2 implantation mask (13) in selected regions followed by a one step IID (130) to achieve selective area intermixing. This novel, low cost, and simple technique can be applied for the fabrication of PICs in general, and WDM sources in particular. By applying a gray scale mask technique in IID in accordance with the present invention, the bandgap energy of a QW material can be tuned to different degrees across a wafer (14). This enables not only the integration of monolithic multiple-wavelength lasers but further extends to integrate with modulators and couplers on a single chip. This technique can also be applied to ease the fabrication and design process of superluminescent diodes (SLDs) by expanding the gain spectrum to a maximum after epitaxial growth.Type: GrantFiled: March 8, 2001Date of Patent: September 9, 2003Assignee: NTU Ventures PTE LtdInventors: Boon Siew Ooi, Yee Loy Lam, Yuen Chuen Chan, Yan Zhou, Siu Chung Tam
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Patent number: 6599133Abstract: A method for fabricating p-type, i-type, and n-type III-V compound materials using HVPE techniques is provided. If desired, these materials can be grown directly onto the surface of a substrate without the inclusion of a low temperature buffer layer. By growing multiple layers of differing conductivity, a variety of different device structures can be fabricated including simple p-n homojunction and heterojunction structures as well as more complex structures in which the p-n junction, either homojunction or heterojunction, is interposed between a pair of wide band gap material layers. The provided method can also be used to fabricate a device in which a non-continuous quantum dot layer is grown within the p-n junction. The quantum dot layer is comprised of a plurality of quantum dot regions, each of which is typically between approximately 20 and 30 Angstroms per axis.Type: GrantFiled: May 18, 2001Date of Patent: July 29, 2003Assignee: Technologies and Devices International, Inc.Inventors: Audrey E. Nikolaev, Yuri V. Melnik, Konstantin V. Vassilevski, Vladimir A. Dmitriev
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Patent number: 6597017Abstract: Provided is a semiconductor device that has pseudo lattice matched layers with good crystallinity, formed with lattice mismatched materials. Tensile-strained n-type Al0.5Ga0.5N layers (lower side) and compressive-strained n-type Ga0.9In0.1N layers (upper side) are grown on a GaN crystal layer substrate in 16.5 periods to form an n-type DBR mirror; an undoped GaN spacer layer and an active region are grown on the n-type DBR mirror; and an undoped a GaN spacer layer is grown on the active region. Further, tensile-strained p-type Al0.5Ga0.5N layers (lower side) and compressive-strained p-type Ga0.9In0.1N layers (upper side) are grown on the spacer layer in 12 periods to form a p-type DBR mirror and eventually complete a surface emitting semiconductor laser.Type: GrantFiled: March 7, 2000Date of Patent: July 22, 2003Assignee: Fuji Xerox Co., Ltd.Inventors: Yasuji Seko, Akira Sakamoto
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Publication number: 20030132431Abstract: One aspect of the present invention has an object to provide a semiconductor optical device with an improved optical gain and an enhanced switching characteristics one aspect of the present invention is to provide a semiconductor optical device including a positive and negative electrodes for providing holes and electrons, respectively. The semiconductor optical device also includes an active layer provided between the positive and negative electrodes. The active layer includes a multiple quantum well structure having a plurality of quantum well layers and barrier layers. The quantum well layers are doped with a p-type impurity less diffusible than zinc so that a plurality of trapping holes are produced and a plurality of excessive electrons contributing no light emission are quenched by the trapping holes. The p-type impurity can be beryllium, magnesium, or carbon.Type: ApplicationFiled: November 8, 2002Publication date: July 17, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Yoshihiko Hanamaki
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Patent number: 6589808Abstract: A GaN type semiconductor layer having a new structure is provided which incorporates a substrate having surface which is opposite to a GaN type semiconductor layer and which is made of Ti.Type: GrantFiled: October 10, 2001Date of Patent: July 8, 2003Assignee: Toyoda Gosei Co., Ltd.Inventors: Toshiaki Chiyo, Shizuyo Noiri, Naoki Shibata, Jun Ito
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Publication number: 20030113948Abstract: A semiconductor structure and method of processing same including a substrate, a lattice-mismatched first layer deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, and a second layer deposited on the first layer with a greater lattice mismatch to the substrate than the first semiconductor layer. In another embodiment there is provided a semiconductor graded composition layer structure on a semiconductor substrate and a method of processing same including a semiconductor substrate, a first semiconductor layer having a series of lattice-mismatched semiconductor layers deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, a second semiconductor layer deposited on the first semiconductor layer with a greater lattice mismatch to the substrate than the first semiconductor layer, and annealed at a temperature greater than 100° C.Type: ApplicationFiled: October 9, 2002Publication date: June 19, 2003Applicant: AmberWave Systems CorporationInventor: Eugene A. Fitzgerald
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Publication number: 20030092210Abstract: A method for producing a semiconductor light emitting device, including at least one first column-like multi-layer structure provided on a substrate and containing gallium nitride-based semiconductor compound semiconductor layers represented by the general formula InxGayAlzN (where x+y+z=1, 0≦x≦1, 0≦y≦1, 0 ≦z≦1), includes a first step of forming a plurality of grooves in the substrate; and a second step of forming a plurality of first column-like multi-layer structures on the substrate so as to be separated by the grooves.Type: ApplicationFiled: November 1, 2002Publication date: May 15, 2003Inventor: Norikatsu Koide
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Patent number: 6558973Abstract: A method and apparatus for fabricating a metamorphic long-wavelength, high-speed photodiode, wherein a buffer layer matching a substrate lattice constant is formed at normal growth temperatures and a thin grading region which grades past the desired lattice constant is configured at a low temperature. A reverse grade back is performed to match a desired lattice constant. Thereafter, a thick layer is formed thereon, based on the desired lattice constant. Annealing can then occur to isolate dislocated material in a grading layer and a reverse grading layer. Thereon a strained layer superlattice substrate is created upon which a high-speed photodiode can be formed. Implant or diffusion layers grown in dopants can be formed based on materials, such as Be, Mg, C, Te, Si, Se, Zn, or others. A metal layer can be formed over a cap above a P+ region situated directly over an N-active region. The active region also includes a p-doped region.Type: GrantFiled: January 22, 2001Date of Patent: May 6, 2003Assignee: Honeywell International Inc.Inventors: Ralph H. Johnson, James K. Guenter, James R. Biard