Graded Composition Patents (Class 438/37)
  • Publication number: 20030042496
    Abstract: A method of forming a partially etched nitride-based compound semiconductor crystal layer includes the following steps. A non-crystal layer of a nitride-based compound semiconductor is formed. At least a part of the non-crystal layer is then etched to form a partially etched non-crystal layer before the partially etched non-crystal layer is crystallized to form a partially etched nitride-based compound semiconductor crystal layer.
    Type: Application
    Filed: August 30, 2002
    Publication date: March 6, 2003
    Applicant: NEC CORPORATION
    Inventor: Chiaki Sasaoka
  • Patent number: 6514784
    Abstract: To shift the bandgap of a quantum well microstructure, the surface of the microstructure is selectively irradiated in a pattern with ultra violet radiation to induce alteration of a near-surface region of said microstructure. Subsequently the microstructure is annealed to induce quantum well intermixing and thereby cause a bandgap shift dependent on said ultra violet radiation.
    Type: Grant
    Filed: September 1, 2000
    Date of Patent: February 4, 2003
    Assignee: National Research Council of Canada
    Inventor: Jan J. Dubowski
  • Publication number: 20030008430
    Abstract: With use of MOCVD method, there are grown in sequence on an n-type GaAs substrate 11, an n-type lower clad 12, an active layer 13, and a p-type upper cladding layer 14 to constitute a light emitting portion. On top of the light emitting portion, there are grown in sequence a p-type intermediate layer 15 and a p-type current diffusion layer 16 made of AlGaInP semiconductor. The intermediate layer 15 made of AlGaInP semiconductor is provided with a growth rate of 1 &mgr;m/h or less and a lattice match ratio &Dgr;a/a against GaAs of −3.2% or more and −2.5% or less. A V/III ratio of the intermediate layer 15 in growth and a V/III ratio of the current diffusion layer 16 in growth are so set that a number of crystal defects observed on the crystal surface is 20 or less per semiconductor light-emitting device. Thus-fabricated semiconductor light-emitting device is high in intensity and small in power consumption, and enables enhancement of productivity.
    Type: Application
    Filed: July 8, 2002
    Publication date: January 9, 2003
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Junichi Nakamura, Kazuaki Sasaki
  • Patent number: 6503773
    Abstract: A semiconductor structure and method of processing same including a substrate, a lattice-mismatched first layer deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, and a second layer deposited on the first layer with a greater lattice mismatch to the substrate than the first semiconductor layer. In another embodiment there is provided a semiconductor graded composition layer structure on a semiconductor substrate and a method of processing same including a semiconductor substrate, a first semiconductor layer having a series of lattice-mismatched semiconductor layers deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, a second semiconductor layer deposited on the first semiconductor layer with a greater lattice mismatch to the substrate than the first semiconductor layer, and annealed at a temperature greater than 100° C.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: January 7, 2003
    Assignee: AmberWave Systems Corporation
    Inventor: Eugene A. Fitzgerald
  • Publication number: 20030003617
    Abstract: A redundancy fuse is made up of a Cu—Al alloy film and a TiN film covering the surrounding surface of this Cu—Al alloy film. When this fuse is cut, the Cu—Al alloy film in the cut portion thermally diffuses by an abrupt temperature rise, and Al preferentially combines with oxygen because Al is baser than Cu. Al oxidizes in the atmosphere, and AlOX as the stable metal oxide produced sticks to the cut surfaces of the redundancy fuse to form a film in self-alignment. This film functions as a protective film to prevent the generation of corrosion.
    Type: Application
    Filed: December 10, 2001
    Publication date: January 2, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Masanobu Ikeda, Satoshi Otsuka
  • Publication number: 20020171092
    Abstract: A smoothing structure containing indium is formed between the substrate and the active region of a III-nitride light emitting device to improve the surface characteristics of the device layers. In some embodiments, the smoothing structure is a single layer, separated from the active region by a spacer layer which typically does not contain indium. The smoothing layer contains a composition of indium lower than the active region, and is typically deposited at a higher temperature than the active region. The spacer layer is typically deposited while reducing the temperature in the reactor from the smoothing layer deposition temperature to the active region deposition temperature. In other embodiments, a graded smoothing region is used to improve the surface characteristics. The smoothing region may have a graded composition, graded dopant concentration, or both.
    Type: Application
    Filed: March 29, 2001
    Publication date: November 21, 2002
    Inventors: Werner K. Goetz, Michael D. Camras, Nathan F. Gardner, R. Scott Kern, Andrew Y. Kim, Stephen A. Stockman
  • Publication number: 20020167018
    Abstract: A semiconductor device includes a substrate, a multi-layer structure provided on the substrate, a first-conductive-type etch stop layer of a III nitride provided on the multi-layer structure, and a second-conductive-type first semiconductor layer of a III nitride provided on the etch stop layer. A molar fraction of Al is lower in a composition of the III nitride included in the first semiconductor layer than in a composition of the III nitride included in the etch stop layer.
    Type: Application
    Filed: October 20, 1999
    Publication date: November 14, 2002
    Inventors: SHINJI NAKAMURA, MASAAKI YURI, KENJI ORITA
  • Patent number: 6468818
    Abstract: A semiconductor light-emitting device has a light-emitting section comprised of at least a lower clad layer, an active layer and an upper clad layer which are formed on a compound semiconductor substrate and a layer grown on the upper clad layer of the light-emitting section. When growing the current diffusion layer from a crystal interface on the upper clad layer in a lattice mismatching state in which the absolute value of a lattice matching factor &Dgr;a/a is not lower than 0.25% with respect to the upper clad layer at a crystal interface where the crystal composition changes on the upper clad layer of the light-emitting section, the growth rate at least at the start time of growth is made to be 1.0 &mgr;m/h or less.
    Type: Grant
    Filed: January 25, 2000
    Date of Patent: October 22, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Junichi Nakamura, Hiroshi Nakatsu, Kazuaki Sasaki
  • Publication number: 20020117680
    Abstract: The semiconductor laser device has a lower clad layer, an active layer, an upper clad layer, a forward mesa forming layer, a contact layer and an insulating film, sequentially formed on the semiconductor substrate. The upper clad layer, the forward mesa forming layer, the contact layer and the insulating film form a ridge. The etching speed of the forward mesa forming layer is higher than that of the upper clad layer and lower than that of the contact layer. Because of such etching speeds, the ridge having a forward mesa structure is formed.
    Type: Application
    Filed: October 23, 2001
    Publication date: August 29, 2002
    Inventors: Keiichi Yabusaki, Michio Ohkubo
  • Publication number: 20020110946
    Abstract: A method and apparatus for fabricating a metamorphic long-wavelength, high-speed photodiode, wherein a buffer layer matching a substrate lattice constant is formed at normal growth temperatures and a thin grading region which grades past the desired lattice constant is configured at a low temperature. A reverse grade back is performed to match a desired lattice constant. Thereafter, a thick layer is formed thereon, based on the desired lattice constant. Annealing can then occur to isolate dislocated material in a grading layer and a reverse grading layer. Thereon a strained layer superlattice substrate is created upon which a high-speed photodiode can be formed. Implant or diffusion layers grown in dopants can be formed based on materials, such as Be, Mg, C, Te, Si, Se, Zn, or others. A metal layer can be formed over a cap above a P+region situated directly over an N-active region. The active region also includes a p-doped region.
    Type: Application
    Filed: January 22, 2001
    Publication date: August 15, 2002
    Inventors: Ralph H. Johnson, James K. Guenter, James R. Biard
  • Patent number: 6410943
    Abstract: A light emitting device and method of fabricating a light emitting device. The device contains a light emitting junction, such as a pn junction. Contacts (11, 15) to the junction are designed to have substantially the same spreading resistance to produce a substantially uniform voltage across the light emitting junction. This will produce substantially light emission by the junction. The contacts can include contact layers (11, 15) whose spreading resistances are substantially matched by controlling the doping, thickness and/or composition of the layers.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: June 25, 2002
    Assignee: Research Triangle Institute
    Inventor: Paul M. Enquist
  • Patent number: 6363092
    Abstract: High power edge emitting semiconductor lasers are formed to emit with very narrow spectral width at precisely selected wavelengths. An epitaxial structure is grown on a semiconductor substrate, e.g., GaAs, and includes an active region at which light emission occurs, upper and lower confinement layers and upper and lower cladding layers. A distributed feedback grating is formed in an aluminum free section of the upper confinement layer to act upon the light generated in the active region to produce lasing action and emission of light from an edge face of the semiconductor laser. Such devices are well suited to being formed to provide a wide stripe, e.g., in the range of 50 to 100 &mgr;m or more, and high power, in the 1 watt range, at wavelengths including visible wavelengths.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: March 26, 2002
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Dan Botez, Thomas L Earles, Luke J. Mawst
  • Patent number: 6342453
    Abstract: A method and system for controlling the introduction of a species according to a determined concentration profile of a film comprising the species introduced on a substrate. In one aspect, the method comprises controlling the flow rate of a species according to a determined concentration profile of a film introduced on a substrate, and introducing a film on a substrate, the film comprising the species at a first concentration at a first point in the film and a second concentration different than the first concentration at a second point in the film. Also, a bipolar transistor including a collector layer of a first conductivity type, a base layer of a second conductivity type forming a first junction with the collector layer, and an emitter layer of the first conductivity type forming a second junction with the base layer. An electrode configured to direct carriers through the emitter layer to the base layer and into the collector layer is also included.
    Type: Grant
    Filed: December 3, 1999
    Date of Patent: January 29, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Shahab Khandan, Christopher T. Fulmer, Lori D. Washington, Herman P. Diniz, Lance A. Scudder, Arkadii V. Samoilov
  • Publication number: 20010035531
    Abstract: In the manufacture of a semiconductor laser device, sequentially grown on a sapphire substrate in the following order are a buffer layer, a first undoped GaN layer, a first super lattice defect reducing layer, a second undoped GaN layer, a second super lattice defect reducing layer, a third undoped GaN layer, a third super lattice defect reducing layer and a fourth undoped GaN layer. A device structure is then formed thereon. The first to third super lattice defect reducing layers each include five pairs of InGaN and AlGaN films alternately placed on one another in this order.
    Type: Application
    Filed: March 21, 2001
    Publication date: November 1, 2001
    Applicant: Sanyo Electric Co., Ltd.,
    Inventors: Takashi Kano, Hiroki Ohbo
  • Publication number: 20010036681
    Abstract: A method for manufacturing a semiconductor optical waveguide comprises the steps of forming a core layer having an Al content which monotonically increases from the central part thereof to the film surface, and selectively oxidizing the core layer to obtain a peripheral, oxidized region and a central, non-oxidized region acting as a waveguide. The waveguide is tapered to have a circular mode field at the distal end thereof for efficiently coupling with an optical fiber.
    Type: Application
    Filed: June 25, 2001
    Publication date: November 1, 2001
    Inventors: Norihiro Iwai, Kazuaki Nishikata, Akihiko Kasukawa
  • Patent number: 6306672
    Abstract: A Group III-V complex vertical cavity surface emitting laser (VCSEL) diode manufactured using GaN-system III-V nitride, and a method of manufacturing the same, are provided. The Group III-V complex surface emitting laser diode can obtain a sufficient reflectance even with a small number of pairs of a distributed bragg reflector (DBR), by forming DBRs including air layers. Thus, the crystal growth problem is solved. Also, current confinement and waveguiding are realized by AIN lateral oxidation or etching.
    Type: Grant
    Filed: July 23, 1998
    Date of Patent: October 23, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Taek Kim
  • Publication number: 20010012640
    Abstract: A lens is formed out of semiconductor material. The semiconductor produces light which is coupled to the lens. The lens focuses the light and also minimizes refractive reflection. The lens is formed by a graded aluminum alloy, which is oxidized in a lateral direction. The oxidation changes the effective shape of the device according to the grading.
    Type: Application
    Filed: April 10, 2001
    Publication date: August 9, 2001
    Applicant: California Institute of Technology, California non-profit organization
    Inventors: John O'Brien, Chuan-Cheng Cheng, Axel Scherer, Amnon Yariv, Yong Xu
  • Patent number: 6258616
    Abstract: A semiconductor device having a buried doped layer of semiconductor material and a non-alloyed contact to the buried doped layer. The non-alloyed contact is made ohmic by the presence of an underlying delta-doped monolayer. The semiconductor device is made by placing a stop-etch layer on top of a buried doped layer and forming at least one delta-doped monolayer in either the stop-etch layer or the buried doped layer. Layers of semiconductor material disposed above the stop-etch layer are removed with an etchant to define an active region of the semiconductor device. The stop-etch layer prevents the etchant from removing the delta-doped monolayer. A non-alloyed metal film is then deposited over the delta-doped monolayer to form an ohmic contact to the buried doped layer.
    Type: Grant
    Filed: May 22, 1998
    Date of Patent: July 10, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: John Edward Cunningham, Keith Wayne Goossen
  • Patent number: 6221684
    Abstract: An n-cap layer is formed on a top surface of p-type clad layers, the p-type clad layer is a top layer of a stacked structure having a pn-junction for emitting carriers into light-emitting region of a GaN based light-emitting device, thus increasing the activation ratio of acceptor impurities in the p-type clad layers. The n-cap layer is used also as a current blocking layer, thereby constructing a current-blocked structure. The n-cap layer should preferably be made of InuAlvGa1−u−vN (0<u, v<1) deposited as thick as 1.0 micron or more. The present invention will easily provide a high luminous efficiency GaN based semiconductor light-emitting device without using any complicated processes such as electron-beam irradiation or thermal annealing.
    Type: Grant
    Filed: December 9, 1999
    Date of Patent: April 24, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideto Sugawara, Masayuki Ishikawa
  • Patent number: 6194742
    Abstract: In the present invention, an interfacial layer is added to a light-emitting diode or laser diode structure to perform the role of strain engineering and impurity gettering. A layer of GaN or AlxInyGal1-x-yN (0≦x≦1, 0≦y≦1) doped with Mg, Zn, Cd can be used for this layer. Alternatively, when using AlxInyGa1-x-yN (x>0), the layer may be undoped. The interfacial layer is deposited directly on top of the buffer layer prior to the growth of the n-type (GaN:Si) layer and the remainder of the device structure. The thickness of the interfacial layer varies from 0.01-10.0 &mgr;m.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: February 27, 2001
    Assignee: LumiLeds Lighting, U.S., LLC
    Inventors: R. Scott Kern, Changhua Chen, Werner Goetz, Chihping Kuo
  • Patent number: 6124147
    Abstract: The present invention relates to a semiconductor device and, more particularly, to a short-wavelength optoelectronic device and a method for fabricating the same. The optoelectronic device according to the present invention doesn't have to employ an ion implantation process and an ohmic contact to make the n-p junction in the WB compound semiconductor, providing a sufficient efficiency for display. The method according to the present invention comprises the step of a) forming a SiC:AlN super lattice multilayer by alternately forming a SiC epitaxial film and an AlN epitaxial film on a substrate, wherein the AlN film is formed and the SiC film is formed using a single source gas of 1,3disilabutane in an nitrogen plasma-assisted metalorganic molecular beam epitaxy system; and b) applying a thermal treatment to the SiC:AlN super lattice multilayer, thereby a mixed crystal compound having (SiC).sub.x (AlN).sub.1-x quantum wells obtained by a diffusion of SiC film and AlN.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: September 26, 2000
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Kyu Hwan Shim, Mun Cheol Paek, Kyoung Ik Cho
  • Patent number: 6121638
    Abstract: At an n--n hetero-interface in a GaN-based or ZnSe-based multilayered semiconductor laser and light-emitting diode, an excessive voltage drop causing the operating voltage to increased is reduced, thereby lengthening the service life of the device. A single or plurality of n-type intermediate layers are provided in the n--n hetero-interface region where the excessive voltage drop develops. The excessive voltage drop developing at the n--n hetero-interface is decreased by setting the energy value at the edge of the conduction band of each intermediate layer to a mid-value between the energy values at the edges of the conduction bands of the n-type compound semiconductors adjoining both sides of the intermediate layer. The configuration of a GaN-based MQW laser including the intermediate layer formed on sapphire substrate is shown.
    Type: Grant
    Filed: October 22, 1997
    Date of Patent: September 19, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: John Rennie, Genichi Hatakoshi, Shinji Saito
  • Patent number: 6110757
    Abstract: A method of forming an epitaxial wafer for a light-emitting device by sequentially growing a lower cladding layer of Al.sub..alpha. Ga.sub..beta. N (0.ltoreq..alpha., .beta..ltoreq.1, .alpha.+.beta.=1), an AlGaInN active layer, and an upper cladding layer of Al.sub..alpha. Ga.sub..beta. N (0.ltoreq..alpha., .beta..ltoreq.1, .alpha.+.beta.=1) on a single-crystal substrate, wherein the AlGaInN active layer is formed by epitaxially growing an active layer of Al.sub.a Ga.sub.b In.sub.c N (wherein 0.ltoreq.a, b, c.ltoreq.1, a+b+c=1) on the lower cladding layer at a temperature of from 650.degree. C. to 950.degree. C., elevating the temperature of the active layer at a rate of not less than 30.degree. C./min until reaching a temperature range of from more than 950.degree. C. to not more than 1200.degree. C., and when the prescribed temperature is reached, primarily cooling the resultant layer to 950.degree. C. within 60 minutes at not less than 20.degree. C.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: August 29, 2000
    Assignee: Showa Denko K. K.
    Inventor: Takashi Udagawa
  • Patent number: 6088376
    Abstract: A semiconductor light-emitting device having an optical cavity with a fiber grating. A vertical-cavity-surface-emitting laser can be constructed to produce single-mode tunable laser oscillation and signal wavelength conversion.
    Type: Grant
    Filed: March 16, 1998
    Date of Patent: July 11, 2000
    Assignee: California Institute of Technology
    Inventors: John O'Brien, Philip Platzman, Amnon Yariv, Axel Scherer, William Marshall
  • Patent number: 6071751
    Abstract: Channel-hot-carrier reliability can be improved by deuterium sintering. However, the benefits obtained by deuterium sintering can be greatly reduced or destroyed by thermal processing steps which break Si--H and Si--D bonds. A solution is to increase the deuterium concentration near the interface to avoid subsequent depletion of deuterium due to diffusion. By using a rapid quench of a sintered wafer, the deuterium concentration near the interface is increased, because the rapid quench impedes the ability of the deuterium to diffuse away from the gate oxide interface.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: June 6, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Robert M. Wallace, Kenneth C. Harvey
  • Patent number: 6036772
    Abstract: A method for making a semiconductor device comprises: depositing at least one Group II-VI compound semiconductor layer comprising at least one Group II element selected from the group consisting of zinc, magnesium, manganese, beryllium, cadmium and mercury and at least one Group VI element selected from the group consisting of oxygen, sulfur, selenium and tellurium onto a Group III-V compound semiconductor layer comprising at least one Group III element selected from the group consisting of gallium, aluminum, boron and indium and at least one Group V element selected from the group consisting of nitrogen, phosphorus, arsenic, antimony and bismuth; whereinbefore depositing the Group II-VI compound semiconductor layer, a particle beam composed of at least one Group II element selected from the group consisting of zinc, magnesium, beryllium, cadmium and mercury is radiated onto the Group III-V compound semiconductor layer in a dose of 8.times.10.sup.-4 Torr.multidot.sec or more.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: March 14, 2000
    Assignee: Sony Corporation
    Inventors: Tomonori Hino, Satoshi Taniguchi, Satoshi Ito
  • Patent number: 6033929
    Abstract: A II-VI group compound semiconductor device includes a semiconductor substrate, a Zn.sub.X Mg.sub.1-X S.sub.Y Se.sub.1-Y (0.ltoreq.X.ltoreq.1, 0.ltoreq.Y.ltoreq.1) semiconductor layer formed on the semiconductor substrate, and an electrode layer formed on the semiconductor layer, the electrode layer containing an additive element of Cd or Te and a metal which can form a eutectic alloy with the additive element, thus achieving an electrode layer having a small contact resistance, especially an electrode layer with an ohmic contact.
    Type: Grant
    Filed: March 22, 1996
    Date of Patent: March 7, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masanori Murakami, Yasuo Koide, Nobuaki Teraguchi
  • Patent number: 6013539
    Abstract: An edge emitting LED comprises a semiconductor substrate having a main surface, an active layer formed over the main surface, and the active layer having a light emitting region, an optical absorption region having a bandgap energy smaller than that of the light emitting region, and a composition change region formed between the light emitting region and the optical absorption region, the composition change region having the bandgap energy continuously changes. Accordingly, an edge emitting LED is able to produce a stable, spontaneous emission of a light under a wide range of operating conditions.
    Type: Grant
    Filed: January 7, 1998
    Date of Patent: January 11, 2000
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yasumasa Kashima, Tsutomu Munakata
  • Patent number: 5937273
    Abstract: A fabricating method of compound semiconductor device is proposed which has a step of varying selective growth ratio of crystal by changing either a mean free path of material gas in gas atmosphere for use in crystal growth or a thickness of a stagnant layer of the material gas, using selective growth mask having opening portion consisting of first region having a narrow width and second region having a wide width.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: August 10, 1999
    Assignee: Fujitsu Limited
    Inventors: Takuya Fujii, Mitsuru Ekawa, Tsuyoshi Yamamoto, Hirohiko Kobayashi
  • Patent number: 5900662
    Abstract: A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body region a respective lightly doped region of the second conductivity type is provided having a second resistivity value higher than the first resistivity value.
    Type: Grant
    Filed: November 4, 1996
    Date of Patent: May 4, 1999
    Assignees: SGS Thomson Microelectronics S.r.l., Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Ferruccio Frisina, Giuseppe Ferla, Salvatore Rinaudo
  • Patent number: 5783839
    Abstract: Disclosed is a semiconductor device, which is used as an optical detector and has: a photodiode section which has a first silicon layer, a light-absorbing layer and a second silicon layer which are in turn layered on a silicon substrate; wherein the light-absorbing layer is formed as a single silicon-germanium epitaxial layer and the single silicon-germanium epitaxial layer has a germanium concentration distribution which provides germanium concentrations of zero at its interfaces to the first silicon layer and the second silicon layer and provides a triangle-shaped concentration profile that a peak concentration value is provided in the middle of the single silicon-germanium epitaxial layer.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: July 21, 1998
    Assignee: NEC Corporation
    Inventors: Takenori Morikawa, Tsutomu Tashiro
  • Patent number: 5776792
    Abstract: On an n-type semiconductor substrate, a buffer layer and a cladding layer are formed. On the cladding layer, an active layer made of Ga.sub.1-X Al.sub.X As is formed. On the active layer, an n-type first optical guiding layer made of Ga.sub.1-Y1 Al.sub.Y1 As is formed, and on the first optical guiding layer, an n-type second optical guiding layer made of Ga.sub.1-Y2 Al.sub.Y2 As is formed in stripe. On the first optical guiding layer and the second optical guiding layer, an n-type cladding layer made of Ga.sub.1-Y3 Al.sub.Y3 As is formed. The interface resistance between the first optical guiding layer and the cladding layer is larger than both the interface resistance between the first optical guiding layer and the second optical guiding layer and the interface resistance between the second optical guiding layer and the cladding layer.
    Type: Grant
    Filed: March 3, 1997
    Date of Patent: July 7, 1998
    Assignee: Matsushita Electronics Corporation
    Inventors: Hiroki Naito, Masahiro Kume
  • Patent number: 5658825
    Abstract: InAsSb/InAsSbP/InAs Double Heterostructures (DH) and Separate Confinement Heterostructure Multiple Quantum Well (SCH-MQW) structures are taught wherein the ability to tune to a specific wavelength within 3 .mu.m to 5 .mu.m is possible by varying the ratio of As:Sb in the active layer.
    Type: Grant
    Filed: September 20, 1996
    Date of Patent: August 19, 1997
    Assignee: Northwestern University
    Inventor: Manijeh Razeghi
  • Patent number: 5263793
    Abstract: Turbulence in a wall-bounded fluid flow field having a turbulent wall region characterized by a system of roll pairs extending in the direction of flow, and propagating structures interacting with the system of roll pairs, is controlled by introducing into the turbulent flow, a disturbance that changes the character of the propagating structures directed at an inclined angle to the direction of flow. Where the disturbance increases the amplitudes of the propagating structure, turbulent mixing or heating is increased; and when the disturbance decreases the amplitude of the propagating structure, the turbulent drag is decreased.
    Type: Grant
    Filed: November 19, 1991
    Date of Patent: November 23, 1993
    Assignee: Ormat Industries, Ltd.
    Inventors: Lawrence Sirovich, Eugene Levich