Abstract: A method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact, using a hard mask with a corresponding mask opening.

Abstract: Ultra-high-density data-storage media employing indium chalcogenide, gallium chalcogenide, and indium-gallium chalcogenide films to form bit-storage regions that act as photoconductive, photovoltaic, or photoluminescent semiconductor devices that produce electrical signals when exposed to electromagnetic radiation, or to form bit-storage regions that act as cathodoconductive, cathodovoltaic, or cathodoluminescent semiconductor devices that produce electrical signals when exposed to electron beams. Two values of a bit are represented by two solid phases of the data-storage medium, a crystalline phase and an amorphous phase, with transition between the two phases effected by heating the bit storage region.

Abstract: A method and structure for a composite trench fill for silicon electronic devices. On a planar silicon substrate having a first deposited layer of oxide and a second deposited layer of polysilicon, a trench is etched. Deposition and etch processes using a combination of oxide and polysilicon are used to fabricate a composite trench fill. The trench bottom and a lower portion of the walls are covered with oxide. The remaining portion of the trench volume is filled with polysilicon. The method may be used for junction field effect transistors (JFETs) and metal oxide semiconductor field effect transistors (MOSFETs).

Abstract: A method of fabricating a deep trench capacitor is provided. A substrate with a deep trench thereon is provided. A bottom electrode is formed at a bottom of the deep trench and a capacitor dielectric layer, a first conductive layer, a protective layer and a collar layer are sequentially formed on the surface of the deep trench. The protective layer and the collar oxide layer on the surface of the first conductive layer are removed, material is deposited into the deep trench to form a material layer. A portion of the material layer is removed to form a first opening. Thereafter, collar oxide layer and the protective layer not covered by the material layer is removed. A portion of the mask layer and the protective layer on the sidewall of the first opening is removed to form a second opening. After removing the material layer, a second conductive layer and a third conductive layer are sequentially formed in the deep trench.

Abstract: A method for fabricating trench capacitors having trenches with mesopores, the trench capacitors being suitable both for discrete capacitors and for integrated semiconductor memories, significantly increases the surface area for electrodes of the capacitors and, hence, the capacitance thereof. The mesopores, which are small woodworm-hole-like channels having diameters from approximately 2 to 50 nm, are fabricated electrochemically. It is, thus, possible to produce capacitances with a large capacitance-to-volume ratio. Growth of the mesopores stops, at the latest, when the mesopores reach a minimum distance from another mesopore or adjacent trench (self-passivation). As such, the formation of “short circuits” between two adjacent mesopores can be avoided in a self-regulated manner. Furthermore, a semiconductor device is provided including at least one trench capacitor on the front side of a semiconductor substrate fabricated by the method according to the invention.

Abstract: Described is a method for fabricating a capacitor of a semiconductor device. The method includes the steps of forming an insulating interlayer including a storage node contact hole on a semiconductor substrate, forming a polysilicon layer on the insulating interlayer including the storage node contact hole, and forming a sacrificial resist layer on the polysilicon layer, thereby filling the storage node contact hole with the sacrificial resist layer.

Abstract: A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and being spaced apart from other islands by a bottom surface on the substrate, a capacitor formed contiguous with the sidewall portion, and a transistor formed on the top portion of the island, the transistor including a gate oxide layer formed on a surface of the top portion, a gate formed on the gate oxide layer, and a first and a second diffused regions formed in the top portion, the first diffused region being spaced apart from the second diffused region.

Abstract: A method of controlling the top width of a deep trench. A conductive layer is formed on the trench over a substrate of polysilicon with a recessed structure. An additional layer of amorphous silicon (?-Si) is deposited onto the polysilicon. After subsequent oxidation, the amorphous silicon is converted to SiO2. According to the invention, the top width of a deep trench is controlled, protecting bit lines from sub-threshold leakage.

Abstract: A method for removal of hemispherical grained silicon (HSG) in a deep trench is described. A buried silicon germanium (SiGe) layer serving as an etch stop layer is formed in the collar region of the trench, followed by depositing a HSG layer. The HSG layer is then successfully striped by wet etching with a potassium hydroxide/propanone/water etchant, that is, without damage to the trench sidewalls, since a good etch rate selectivity between the HSG layer and the SiGe layer is obtained by the wet etchant. In addition, no etch stop layer exists between the HSG layer and the bottom of the trench when manufacturing trench capacitors in accordance with the method; capacitance degradation is therefore not of concern.

Abstract: A method of forming a memory cell with a single sided buried strap. A collar oxide layer is formed on the sidewall of a trench. A conductive layer fills the trench. The conductive layer and the collar oxide layer are partially removed to form an opening having first and second sidewalls. The remaining collar oxide layer is lower than the remaining conductive layer. An angle implantation with F ions is performed on the first sidewall. A thermal oxidation process is performed to form a first oxide layer on the first sidewall and a second oxide layer on the second sidewall. The first oxide layer is thicker than the second oxide layer. The second oxide layer is removed to expose the second sidewall. A buried strap is formed at the bottom of the opening, insulated from the first sidewall by the first oxide layer.

Abstract: A method of fabricating a deep trench capacitor is described. A substrate having a deep trench therein is provided. A doped region is formed in the substrate at the bottom of the deep trench, a dielectric layer is formed on the bottom surface of the deep trench, and a first conductive layer is formed on the dielectric layer. A collar oxide layer is formed on sidewalls of the deep trench that are not covered by the first conductive layer. A material layer is formed covering the first conductive layer and exposing a portion of the collar oxide layer. The exposed collar oxide layer is removed to expose the substrate. Then, the material layer is removed, and a second conductive layer is formed in the deep trench covering the first conductive layer and the collar oxide layer. In this invention, only the second conductive layer is formed on the first conductive layer for electrically connecting the capacitor and an active device, hence the method is more simple.

Abstract: A semiconductor Dynamic Random Access Memory (DRAM) cell is fabricated using a vertical access transistor and a storage capacitor formed in a vertical trench. A Shallow Trench Isolation (STI) region is used as a masking region to confine the channel region of the access transistor, the first and second output regions of the access transistor, and a strap region connecting the second output region to the storage capacitor, to a narrow portion of the trench. The so confined second output region of the access transistor has reduced leakage to similar second output regions of adjacent memory cells. Adjacent memory cells can then be placed closer to one another without an increase in leakage and cross-talk between adjacent memory cells.

Abstract: A first insulating layer is formed on semiconductor substrate, and a trench is formed in the first insulating layer. An amorphous silicon layer doped with impurities is formed on a side and bottom walls of the trench. Next, a resist material is partially filled in the trench so that an upper portion of the amorphous silicon layer is exposed. The exposed portion is implanted with impurity ions. After removal of the resist material, the amorphous silicon layer is heat treated so as to grow hemispherical grains on its surface.

Abstract: A trench capacitor, in particular for use in a semiconductor memory cell, has a trench formed in a substrate; an insulation collar formed in an upper region of the trench; an optional buried plate in the substrate region serving as a first capacitor plate; a dielectric layer lining the lower region of the trench and the insulation collar as a capacitor dielectric; a conductive second filling material filled into the trench as a second capacitor plate; and a buried contact underneath the surface of the substrate. The substrate has, underneath its surface in the region of the buried contact, a doped region introduced by implantation, plasma doping and/or vapor phase deposition. A tunnel layer, in particular an oxide, nitride or oxinitride layer, is preferably formed at the interface of the buried contact. A method for producing a trench capacitor is also provided.

Abstract: A trench capacitor includes an electrode having a first conductive area formed in a trench provided in a substrate, and a second conductive area extending from a bottom of the trench, the second conductive area being electrically coupled to the first conductive area and spaced apart from the first conductive area; a storage node having a first conductive extension extending into a first dielectric space provided between the first conductive area and the second conductive area of the electrode, and a second conductive extension extending into a second dielectric space provided within the second conductive area of the electrode; and a dielectric layer electrically insulating the electrode from the storage node.

Abstract: This invention pertains to a method for making a trench capacitor of DRAM devices. A portion of the collar oxide layer is masked after the second polysilicon deposition and recess etching process. Subsequently, the un-masked collar oxide layer is etched away to form an asymmetric collar oxide structure. The third polysilicon deposition and recess etching process is then carried out to form a third polysilicon stud atop the second polysilicon layer. The asymmetric collar oxide structure has a lower annular portion wrapping the second polysilicon layer and insulating the second polysilicon layer from the substrate, and an upper portion serving as a single-sided spacer for blocking diffusion of dopants from the third polysilicon stud to the substrate.

Abstract: The present invention refers to a method of forming a silicon dioxide layer by thermally oxidizing at least one monocrystalline silicon surface region on a semiconductor substrate. The silicon surface region has a curved surface. The method can include providing a semiconductor substrate having at least one monocrystalline silicon surface region having a curved surface, roughening the surface of the at least one monocrystalline silicon surface region to produce a layer of porous silicon, and thermally oxidizing the at least one roughened monocrystalline silicon surface.

Abstract: A method for forming a vertical transistor and a trench capacitor. A semiconductor substrate having a pad stacked layer on the surface and a trench formed therein is provided. A capacitor is formed at the bottom part of the trench and a portion of the upper sidewall of the trench is exposed. A conductive wire is then formed on the capacitor, followed by forming a dielectric layer on the exposed sidewalls of the trench. A trench top dielectric is then formed by liquid phase deposition on the conductive wire. A transistor is then formed on the trench top dielectric, which isolates the transistor from the capacitor.

Abstract: A method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact, using a hard mask with a corresponding mask opening.

Abstract: A 3D microelectronic structure is provided which includes a substrate having at least one opening present therein, the at least one opening having sidewalls which extend to a common bottom wall; and a thermal nitride layer present on at least an upper portion of each sidewall of openings. A method for fabricating the above-mentioned 3D microelectronic structure is also provided. Specifically, the method includes a step of selectively forming a thermal nitride layer on at least an upper portion of each sidewall of an opening formed in a substrate.

Abstract: Provided is a method of manufacturing a semiconductor device includes forming an interlayer insulating film above a silicon (semiconductor) substrate, forming an lower layer of a lower-electrode conductive film on the interlayer insulating film while keeping the substrate temperature at a temperature higher than room temperature and lower than 300° C., forming an upper layer of the lower-electrode conductive film on the lower layer and setting the upper and lower layers as the lower-electrode conductive film, forming a ferroelectric film on the lower-electrode conductive film, forming an upper-electrode conductive film on the ferroelectric film, and forming a ferroelectric capacitor by patterning the upper-electrode conductive film, the ferroelectric film, and the lower-electrode conductive film.

Abstract: In a process of fabricating a narrow channel width PMOSFET device, the improvement of affecting reduction of negative bias temperature instability by use of F2 side wall implantation, comprising: a) forming a shallow trench isolation (STI) region in a substrate; b) forming a gate on a gate oxide in the substrate; c) forming a liner layer in said shallow trench isolation region and subjecting the liner layer to oxidation to form a STI liner oxidation layer; d) implanting F2 into side walls of the STI liner oxidation layer at a large tilted angle in sufficient amounts to affect reduction of negative bias temperature instability after a high density plasma fill of the STI F2 implanted liner oxidation layer; and e) filling the STI F2 implanted structure from step d) with a high density plasma (HDP) fill to affect reduction of negative bias temperature instability.

Abstract: A trench capacitor has an insulation collar that is formed non-conformally in the upper region of a trench in such a way that a layer thickness in an upper section of the insulation collar is greater than a layer thickness in a lower section of the insulation collar. This results in a trench capacitor having improved leakage current properties. A simplified and cost-effective method of fabricating a trench capacitor is also provided.

Abstract: A method for forming a trench with a buried plate includes the steps of forming a trench in a substrate, depositing a non-doped silicate oxide in the trench and placing a doped silicate glass filling thereon. A buried trench plate is formed around the lower region of the trench in the substrate.

Abstract: The present invention provides a method for manufacturing semiconductors with trench capacitors having a low-resistance buried strap, comprising providing a substrate, forming a trench in the substrate, forming a glass doping layer with a first predetermined depth at the bottom of the trench, wherein the glass doping layer is doped with an n-type dopant, forming a first dielectric layer covering the glass doping layer in the trench, diffusing the n-type dopant of the glass doping layer to the substrate by annealing to form a buried plate, removing the first dielectric layer and the glass doping layer, sequentially forming a second dielectric layer and a first conductive layer having depths approximately equal to the first predetermined depth in the trench, wherein the region above the first conductive region is defined as the collar region, forming a U-shaped insulating layer in the collar region, forming a collar conductive layer at the bottom of the U-shaped insulation layer in the collar region, removing t

Abstract: In fabricating a shallow trench isolation (STI), a silicon oxide layer, a silicon nitride layer and a moat pattern is sequentially deposited on a silicon substrate. Next, the silicon nitride layer and the silicon oxide layer is etched using the moat pattern as a mask to thereby partially expose the silicon substrate and then the moat pattern is removed. Ion implanting process is performed into the silicon substrate using the silicon nitride layer as a mask, adjusting a dose of an implanted ion and an implant energy, to thereby form an isolation region. And then, the isolation region to form a porous silicon and to form an air gap in the porous silicon is anodized, wherein a porosity of the porous silicon is determined by the dose of the implanted ion. Next, the porous silicon is oxidized through an oxidation process. Finally, the silicon nitride layer is removed.

Abstract: In a method for forming a trench capacitor a first layer of silicon oxide is deposited in a storage trench and a layer of silicon is deposited over the first layer by a chemical vapor deposition process. A layer of an oxidizable metal is deposited over the layer of silicon. The layer of silicon and the layer of the oxidizable metal are subsequently oxidized to form a layer of silicon oxide and metal oxide.

Abstract: In a method of forming a DRAM cell in a semiconductor substrate, the improvement of maintaining a substantially full trench opening during trench processing comprising: a) forming a pad nitride on the surface of the substrate and reactive ion etching (RIE) a trench vertically to a first depth; b) depositing a nitride layer in the trench; c) filling the trench with a poly silicon fill; d) recess etching the fill to the collar depth; e) oxidizing to transform the exposed nitride layer into a nitrided oxide collar or depositing an oxide on the layer of nitride; f) reactive ion etching to open the bottom oxide; g) stripping the poly fill trench, and performing a nitride etch selective to oxide; h) expanding the trench horizontally by etching lower trench sidewalls and bottom while masking the upper sidewalls; i) forming a buried plate at the bottom of the trench sidewalls; j) forming the node dielectric in the deep trench to grow a collar oxide that consists of a nitrided oxide and a layer of node nitride; k) fil

Abstract: A plasma photoresist hardening technique is provided to improve the etch resistance of a photoresist mask 26. The technique involves the formation of a thin passivation layer 26b on the photoresist mask 26 which substantially slows down the etching rate of the photoresist material 26a. Advantageously, this technique allows preservation of critical dimension features such as via hole openings and transmission lines. The technique hardens the surface of the photoresist film 26 by both chemically and physically bonding halogenated hydrocarbons with cross linked photoresist polymer. This results in a passivation layer 26b which is highly resistant to harsh plasma etch environments.

Abstract: A method for fabricating trench capacitors having trenches with mesopores, the trench capacitors being suitable both for discrete capacitors and for integrated semiconductor memories, significantly increases the surface area for electrodes of the capacitors and, hence, the capacitance thereof. The mesopores, which are small woodworm-hole-like channels having diameters from approximately 2 to 50 nm, are fabricated electrochemically. It is, thus, possible to produce capacitances with a large capacitance-to-volume ratio. Growth of the mesopores stops, at the latest, when the mesopores reach a minimum distance from another mesopore or adjacent trench (self-passivation). As such, the formation of “short circuits” between two adjacent mesopores can be avoided in a self-regulated manner. Furthermore, a semiconductor device is provided including at least one trench capacitor on the front side of a semiconductor substrate fabricated by the method according to the invention.

Abstract: In a vertical-transistor based semiconductor structure, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a sacrificial insulator layer, forming a vertical hardmask on the inner trench walls above the sacrificial insulator, then stripping the insulator to expose the substrate walls; diffusing dopant into the substrate walls to form a self-aligned extension of the buried strap; depositing the final gate insulator; and then forming the upper portion of the vertical transistor.

Abstract: An insulating layer having a BPSG layer, a semiconductor device and methods for fabricating them. After preparing an oxidizing atmosphere using an oxygen gas, a first seed layer is formed with a tetraethylorthosilicate (TEOS) and the oxygen gas. Thereafter, a second seed layer, used to form an insulating layer capable of controlling an amount of a boron, is formed by means of using a triethylborate (TEB), the TEOS and the oxygen gas. Then, the insulating layer having a BPSG layer is formed using the TEB, a triethylphosphate, the TEOS and an ozone gas. About 5.25 to 5.75% by weight of the boron and about 2.75 to 4.25% by weight of the phosphorous are added to the insulating layer.

Abstract: A method is provided of fabricating a semiconductor device that includes forming a silicon oxide film on a semiconductor substrate. A silicon nitrite film may be formed on the silicon oxide film. A portion of the silicon nitrite film and the silicon oxide film may be removed at a desired portion. Additionally, a groove may be formed in the semiconductor substrate in the portion in which the silicon oxide film is removed. A part of the silicon oxide film may be etched back around the groove with hydrofluoric acid type at the portion in which the silicon nitrite film is located above. Additionally, an oxidized film may be formed in the groove of the semiconductor substrate and the groove may be oxidized.

Abstract: A trench capacitor for use in a semiconductor memory cell is formed in a substrate. The trench capacitor includes a trench having an upper region and a lower region, an insulation collar formed in the upper region on a trench wall of the trench, and a buried well, through which the lower region of the trench at least partly extends. The trench capacitor further includes, as an outer capacitor electrode, a conductive layer lining the lower region of the trench and the insulation collar, a dielectric layer lining the conductive layer, and a conductive trench filling which is filled into the trench as an inner capacitor electrode. A method of fabricating a trench capacitor is also provided.

Abstract: The vertical DRAM capacitor with a buried LOCOS collar characterized by: a self-aligned bottle and gas phase doping; no consumption of silicon at the depth of the buried strap; no reduction of trench diameter; and a nitride layer to protect trench sidewalls during gas phase doping.

Abstract: The present invention provides a method for manufacturing semiconductors with trench capacitors having a low-resistance buried strap, comprising providing a substrate, forming a trench in the substrate, forming a glass doping layer with a first predetermined depth at the bottom of the trench, wherein the glass doping layer is doped with an n-type dopant, forming a first dielectric layer covering the glass doping layer in the trench, diffusing the n-type dopant of the glass doping layer to the substrate by annealing to form a buried plate, removing the first dielectric layer and the glass doping layer, sequentially forming a second dielectric layer and a first conductive layer having depths approximately equal to the first predetermined depth in the trench, wherein the region above the first conductive region is defined as the collar region, forming a U-shaped insulating layer in the collar region, forming a collar conductive layer at the bottom of the U-shaped insulation layer in the collar region, removing t

Abstract: A method for fabricating a trench capacitor for a semiconductor memory includes forming a masking layer in a trench that is disposed in a substrate. Nanocrystallites, which are used to pattern the masking layer, are deposited on the masking layer. Microtrenches are etched into the substrate in a lower region of the trench by the patterned masking layer. The microtrenches form a roughened trench sidewall. As a result, the outer capacitor electrode is formed with a larger surface area, allowing the trench capacitor to have a higher capacitance.

Abstract: A method for increasing a trench capacitance in deep trench capacitors is described, in which, in a standard method, after the etching of the arsenic glass, a wet-chemical etching is additionally performed. An n+-doped substrate results from the driving-out of the arsenic glass being widened in the trench, by about 20 nm, selectively both with respect to the lightly doped substrate and with respect to the oxide layer and with respect to the nitride layer.

Abstract: A method of improving planarity of a photoresist. Before coating the photoresist over a silicon oxide layer, modifying a surface of the silicon oxide layer to enhance an adhesion between the silicon oxide layer and the photoresist. The photoresist flows into trenches of the silicon oxide layer, then the photoresist has good planarity, even after performing a baking process.

Abstract: According to the present method of manufacturing a semiconductor device, since a contact hole has its opening gradually and continuously made smaller toward the lower interconnection layer, a cavity, which has been produced conventionally, would not be produced in a barrier metal layer and a metal interconnection layer formed along the side wall of the contact hole. As a result, even when the reduction in size of the semiconductor has progressed, it is possible to provide a method of manufacturing semiconductor device having its contact hole in a proper shape, and to provide such a semiconductor device.

Abstract: A trench is formed in a substrate with an upper region and a lower region. The trench is subsequently widened in its upper region and in its lower region by isotropic etching. In the upper region, an insulating collar is formed that is designated as a buried insulating collar due to the widened trench. The insulating collar is removed in the vicinity of the surface of the substrate, through which the substrate is exposed in this region. Here, a selective epitaxial layer is subsequently grown in the trench, through which a subsequently formed selection transistor can be formed in perpendicular fashion over the trench, or very close to the trench. In addition, through the widened trench the electrode surface of the capacitor electrodes is enlarged, which ensures an increased storage capacity.

Abstract: A method for fabricating DRAM and flash memory cells on a single chip includes providing a silicon substrate, forming a trench capacitor for each of the DRAM cells in the silicon substrate, forming isolation regions in the silicon substrate which are electrically isolated from each other, forming first type wells for DRAM and flash memory cells at first predetermined regions of the silicon substrate by implanting a first type impurity in the first predetermined regions, forming second type wells for DRAM and flash memory cells at second predetermined regions in the first type wells by implanting a second type impurity in the second predetermined regions, forming oxide layers for DRAM and flash memory cells on the second type wells, forming gate electrodes for DRAM and flash memory cells on the oxide layers for DRAM and flash memory cells, and forming source and drain regions for DRAM and flash memory cells in the respective second type wells for DRAM and flash memory cells, in which the source and drain regio

Abstract: An upper capacitor electrode of a trench capacitor of a DRAM memory cell is formed at least in part as a result of a plurality of metal-containing layers being deposited one on top of another and in each case being conditioned after they have been deposited. In this way, the internal stress of the electrode layer can be reduced, and therefore a breaking strength and a resistance to leakage currents of the trench capacitor can be increased.

Abstract: A capacitor for a memory device is formed with a conductive oxide for a bottom electrode. The conductive oxide (RuOx) is deposited under low temperatures as an amorphous film. As a result, the film is conformally deposited over a three dimensional, folding structure. Furthermore, a subsequent polishing step is easily performed on the amorphous film, increasing wafer throughput. After deposition and polishing, the film is crystallized in a non-oxidizing ambient.

Abstract: A method of using at least two insulative layers to form the isolation collar of a trench device, and the device formed therefrom. The first layer is preferably an oxide (e.g., silicon dioxide 116) formed on the trench substrate sidewalls, and is formed through a TEOS, LOCOS, or combined TEOS/LOCOS process. Preferably, both the TEOS process and the LOCOS process are used to form the first layer. The second layer is preferably a silicon nitride layer (114) formed on the oxide layer. The multiple layers function as an isolation collar stack for the trench. The dopant penetration barrier properties of the second layer permit the dielectric collar stack to be used as a self aligned mask for subsequent buried plate (120) doping.

Abstract: A method of doping trench sidewall and hemispherical-grained silicon in deep trench cells to increase surface area and storage capacitance while avoiding deformation of trenches and hemispherical-grained silicon, comprising: a) Etching a deep trench structure by reactive ion etching; b) Forming a LOCOS collar in an upper portion of the trench over a conformal layer of a silicon containing material, the collar leaving a lower portion of the trench exposed; c) Depositing a film of hemispherical-grained silicon (HSG-Si) at sidewalls of the deep trench; d) Plasma doping the hemispherical-grained silicon; and e) Depositing a node dielectric and filling the trench with polysilicon.

Abstract: A process for forming a sacrificial collar (116) on the top portion of a deep trench (114). A nitride layer (116) is deposited within the trench (114). A semiconductor layer (120) is deposited over the nitride layer (116). A top portion of the semiconductor layer (120) is doped to form doped semiconductor layer (124). Undoped portions (120) of the semiconductor layer are removed, and the doped semiconductor layer (124) is used to pattern the nitride layer (116), removing the lower portion of nitride layer (116) from within deep trenches (114) and leaving a sacrificial collar (116) at the top of the trenches (114).

Abstract: A method for fabricating a trench capacitor, that includes steps of: providing a silicon substrate; forming a trench, having a lower region and a surface, in the silicon substrate; and forming a doped layer in the silicon substrate in the lower region of the trench. In addition, a roughened silicon layer that has silicon grains with a diameter ranging from essentially 10 to 100 nm is produced in the lower region of the trench. A dielectric intermediate layer is applied on the roughened silicon layer, and the trench is filled with a doped layer.

Abstract: A trench is formed in a substrate with an upper region and a lower region. The trench is subsequently widened in its upper region and in its lower region by isotropic etching. In the upper region, an insulating collar is formed that is designated as a buried insulating collar due to the widened trench. The insulating collar is removed in the vicinity of the surface of the substrate, through which the substrate is exposed in this region. Here, a selective epitaxial layer is subsequently grown in the trench, through which a subsequently formed selection transistor can be formed in perpendicular fashion over the trench, or very close to the trench. In addition, through the widened trench the electrode surface of the capacitor electrodes is enlarged, which ensures an increased storage capacity.

Abstract: A method for etching features in an integrated circuit wafer, the wafer incorporating at least one dielectric layer is provided. Generally, the wafer is disposed within a reaction chamber. An etchant gas comprising a hydrocarbon additive and an active etchant is flowed into the reaction chamber. A plasma is formed from the etchant gas within the reaction chamber. The feature is etched in at least a portion of the dielectric layer.