Stacked Capacitor Patents (Class 438/396)
  • Patent number: 11476253
    Abstract: A semiconductor memory device includes a capacitor on a substrate. The capacitor includes a first electrode, a second electrode on the first electrode, and a dielectric layer between the first electrode and the second electrode. The second electrode includes a first layer, a second layer, and a third layer. The first layer is adjacent to the dielectric layer, and the third layer is spaced apart from the first layer with the second layer interposed therebetween. A concentration of nickel in the third layer is higher than a concentration of nickel in the first layer.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: October 18, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyooho Jung
  • Patent number: 11437312
    Abstract: A metal insulator metal capacitor and method for fabricating a metal insulator metal capacitor (MIMcap) are disclosed. A first level metal pattern is embedded in a first dielectric layer over a substrate. The first level metal pattern has a top surface co-planar with a top surface of the first dielectric layer. In a selected etch step, either one of the first metal pattern or the first dielectric is etched to form a stepped top surface. A conformal insulating layer on the stepped top surface. The MIMcap is formed on the conformal insulating layer in a conformal manner.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: September 6, 2022
    Assignee: International Business Machines Corporation
    Inventors: Jim Shih-Chun Liang, Naftali E Lustig, Atsushi Ogino, Nan Jing
  • Patent number: 11424205
    Abstract: A semiconductor device includes a first interconnect structure over first substrate, a first bonding layer over the first interconnect structure, multiple first bonding pads disposed in a first region of the first bonding layer, the first bonding pads having a first pitch, and multiple second bonding pads disposed in a second region of the first bonding layer, the second region extending between a first edge of the first bonding layer and the first region, the second bonding pads having the first pitch, the multiple second bonding pads including multiple pairs of adjacent second bonding pads, wherein the second bonding pads of each respective pair are connected by a first metal line.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: August 23, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jie Chen, Hsien-Wei Chen
  • Patent number: 11417724
    Abstract: A capacitor includes a lower electrode, a first dielectric layer provided on the lower electrode including a perovskite structure, an upper electrode including a perovskite structure, a first dielectric layer between provided on the lower electrode and the upper electrode; and a second dielectric layer, having a band gap energy greater than that of the first dielectric layer, provided between on the first dielectric layer and the upper electrode, the capacitor may have a low leakage current density and stable crystallinity, thereby suppressing a decrease in a dielectric constant.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: August 16, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeongil Bang, Seungwoo Jang, Hyosik Mun, Younggeun Park, Jooho Lee
  • Patent number: 11395632
    Abstract: The invention concerns an implementable semiconductor device that includes an electrode configured to be in contact with biological tissue and at least one capacitor, and wherein the capacitor includes a capacitor electrode having a first surface facing and in contact with the electrode configured to be in contact with biological tissue.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: July 26, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Nicolas Normand, Stéphane Bouvier
  • Patent number: 11348924
    Abstract: A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: May 31, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Hoon Kim, Kwang-Ho Park, Yong-Hoon Son, Hyunji Song, Gyeonghee Lee, Seungjae Jung
  • Patent number: 11296099
    Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Yu Chen, Kuo-Chi Tu, Fu-Chen Chang, Chih-Hsiang Chang, Sheng-Hung Shih
  • Patent number: 11289340
    Abstract: A dry etching method according to the present invention includes etching silicon nitride by bringing a mixed gas containing hydrogen fluoride and a fluorine-containing carboxylic acid into contact with the silicon nitride in a plasma-less process at a temperature lower than 100° C. Preferably, the amount of the fluorine-containing carboxylic acid contained is 0.01 vol % or more based on the total amount of the hydrogen fluoride and the fluorine-containing carboxylic acid. Examples of the fluorine-containing carboxylic acid are monofluoroacetic acid, difluoroacetic acid, trifluoroacetic acid, difluoropropionic acid, pentafluoropropionic acid, pentafluorobutyric acid and the like. This dry etching method enables etching of the silicon nitride at a high etching rate and shows a high selectivity ratio of the silicon nitride to silicon oxide and polycrystalline silicon while preventing damage to the silicon oxide.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: March 29, 2022
    Assignee: Central Glass Company, Limited
    Inventors: Shoi Suzuki, Akifumi Yao
  • Patent number: 11251262
    Abstract: A capacitor and a manufacturing method thereof are provided. The capacitor includes a cup-shaped lower electrode, a capacitive dielectric layer, an upper electrode, and a support layer. The support layer includes an upper support layer surrounding an upper portion of the cup-shaped lower electrode, a middle support layer surrounding a middle portion of the cup-shaped lower electrode, and a lower support layer surrounding a lower portion of the cup-shaped lower electrode. Surfaces of the upper support layer, the middle support layer, and the lower support layer are covered by the capacitive dielectric layer.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: February 15, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Yu-Ping Hsiao, Wei-Chao Chou, Ming-Tang Chen, Cheol Soo Park
  • Patent number: 11244946
    Abstract: Semiconductor device may include a landing pad and a lower electrode that is on and is connected to the landing pad and includes an outer portion and an inner portion inside the outer portion. The outer portion includes first and second regions. The semiconductor devices may also include a dielectric film on the first region of the outer portion on the lower electrode and an upper electrode on the dielectric film. The first region of the outer portion of the lower electrode may include a silicon (Si) dopant, the dielectric film does not extend along the second region of the outer portion. A concentration of the silicon dopant in the first region of the outer portion is different from a concentration of the silicon dopant in the second region of the outer portion and is higher than a concentration of the silicon dopant in the inner portion.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: February 8, 2022
    Inventors: Chang Mu An, Sang Yeol Kang, Young-Lim Park, Jong-Bom Seo, Se Hyoung Ahn
  • Patent number: 11205696
    Abstract: An integrated circuit has an isolation capacitor structure that reduces the risk of breakdown from high electric fields at the edge of the top metal plate of the capacitor. The capacitor structure includes a bottom metal plate above a substrate. A first dielectric layer of a first dielectric material is formed between the bottom metal plate and the top metal plate. The capacitor structure also includes a thin narrow ring formed of a second dielectric material located under a portion of the top metal plate. The second dielectric material has a higher dielectric constant than the first dielectric material. The thin narrow ring follows the shape of the edge of the top metal plate with a portion of the ring underneath the top metal plate and a portion outside the edge of the top metal plate to thereby be located at a place of the maximum electric field.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: December 21, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventors: Dan B. Kasha, Russell Croman, Stefan N. Mastovich, Thomas C. Fowler
  • Patent number: 11152391
    Abstract: A method of producing a semiconductor memory device includes, when three directions crossing each other are set to first, second, and third directions, respectively, laminating a plurality of first laminates and a plurality of second laminates on a semiconductor substrate in the third direction. The method further includes forming ends of the plurality of first laminates in shapes of steps extending in the first direction, and forming ends of the plurality of second laminates in shapes of steps extending in both directions of the first direction and the second direction.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: October 19, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tadashi Iguchi, Murato Kawai, Toru Matsuda, Hisashi Kato, Megumi Ishiduki
  • Patent number: 11133248
    Abstract: A semiconductor structure and a method of fabricating the same is disclosed. The semiconductor structure includes an interconnect structure that comprises: a plurality of conductive features over a substrate arranged separately adjacent one another; a liner conformally formed over and between the plurality of conductive features and defining a trench having a first depth between adjacent pair of the conducive features, wherein a horizontal coverage of the liner over respective top surfaces of the conductive features has thickness lower than that of a vertical coverage over respective sidewalls of the conductive features; and a dielectric layer on the liner over top surfaces of the conductive features, wherein the dielectric layer seals the respective trench and forms a void between adjacent pair of the conductive features.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: September 28, 2021
    Assignee: XIA TAI XIN SEMICONDUCTOR (QING DAO) LTD.
    Inventors: Hyunyoung Kim, Dowon Kwak, Kang-Won Seo
  • Patent number: 11107820
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a plurality of capacitor contacts positioned over the substrate, at least one of the plurality of capacitor contacts having a neck portion and a head portion over the neck portion, wherein an upper width of the head portion is larger than an upper width of the neck portion; a plurality of bit line contacts positioned over the substrate and a plurality of bit lines positioned over the plurality of bit line contacts, wherein at least one of the plurality of bit line is a wavy line extending between two adjacent capacitor contacts; and a capacitor structure positioned over the head portion.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: August 31, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Wei Huang
  • Patent number: 11101284
    Abstract: A method of forming a semiconductor structure includes providing a dopant species selected from carbon, boron, nitrogen or oxygen into an upper portion of a semiconductor region to form a doped etch stop semiconductor material portion over a remaining semiconductor material portion, forming an overlying material portion over the etch stop semiconductor material portion, etching through the overlying material portion by an etch process that removes the overlying material portion selective to a material of the etch stop semiconductor material portion, and depositing at least one fill material over the etch stop semiconductor material portion.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: August 24, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jayavel Pachamuthu, Hiroyuki Kinoshita, Masaaki Higashitani, Makoto Dei, Junji Oh
  • Patent number: 11011381
    Abstract: There is provided a method of patterning platinum on a substrate. A platinum layer is deposited on the substrate, and a patterned photoresist layer is formed over the platinum layer leaving partly exposed regions of the platinum layer. An aluminum layer is deposited over the partly exposed regions of the platinum layer. An alloy is formed of aluminum with platinum from the partly exposed regions. The platinum aluminum alloy is etched away leaving a remaining portion of the platinum layer to form a patterned platinum layer on the substrate. In an embodiment, a thin hard mask layer is deposited on the platinum layer on the semiconductor substrate before the patterned photoresist layer is formed.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: May 18, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sebastian Meier, Helmut Rinck
  • Patent number: 10964475
    Abstract: Methods, apparatuses, and systems related to forming a capacitor using a sacrificial material are described. An example method includes forming a first silicate material on a substrate. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes forming a sacrificial material on the second nitride material. The method further includes forming a column of capacitor material through the first silicate material, the first nitride material, the second silicate material, the second nitride material, and the sacrificial material. The method further includes removing the sacrificial material to expose a top portion of the capacitor material.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: March 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Devesh Dadhich Shreeram, Sevim Korkmaz, Jian Li, Sanjeev Sapra, Dewali Ray
  • Patent number: 10957587
    Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a conductive feature over a semiconductor substrate and forming a dielectric layer over the conductive feature. The method also includes forming an opening in the dielectric layer to expose the conductive feature. The method further includes forming a conductive material to overfill the opening. In addition, the method includes thinning the conductive material using a chemical mechanical polishing process. A slurry used in the chemical mechanical polishing process includes an iron-containing oxidizer that oxidizes a portion of the conductive material.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: March 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Chieh Wu, Kuo-Hsiu Wei, Kei-Wei Chen, Tang-Kuei Chang, Chia Hsuan Lee, Jian-Ci Lin
  • Patent number: 10903314
    Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: January 26, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Shen Li, Ching-Yang Wen, Purakh Raj Verma, Xingxing Chen, Chee-Hau Ng
  • Patent number: 10770230
    Abstract: A multilayer ceramic capacitor includes a body including a dielectric layer and first and second internal electrodes, and external electrodes disposed on at least one surface of the body. The external electrodes each includes an electrode layer in contact with the first or second internal electrodes, an intermediate layer disposed on the electrode layer and including a first intermetallic compound, and a conductive resin layer disposed on the intermediate layer and including a plurality of metal particles, a second intermetallic compound and a base resin.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: September 8, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Kun Hoi Koo, Bon Seok Koo, Jung Min Kim, Jun Hyeon Kim, Hae Sol Kang, Soung Jin Kim, Ji Hye Han, Byung Woo Kang, Chang Hak Choi
  • Patent number: 10741488
    Abstract: A semiconductor structure includes a capacitor including a first electrode and a second electrode disposed over and electrically insulated from the first electrode. The semiconductor structure also includes a first conductive via extending through the first electrode and contacting a planar surface of the first electrode. The semiconductor structure further includes a second conductive via extending through the second electrode and contacting a planar surface of the second electrode.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Chung-Yen Chou
  • Patent number: 10734330
    Abstract: A semiconductor device includes a substrate and a metallization layer. The substrate has an active region that includes opposite first and second edges. The metallization layer is disposed above the substrate, and includes a pair of metal lines and a metal plate. The metal lines extend from an outer periphery of the active region into the active region and toward the second edge of the active region. The metal plate interconnects the metal lines and at least a portion of which is disposed at the outer periphery of the active region.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Yi-Feng Chang
  • Patent number: 10707297
    Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey Alan West, Thomas D. Bonifield, Byron Lovell Williams
  • Patent number: 10700084
    Abstract: A vertical memory device includes a substrate including a cell region and a peripheral circuit region, gate electrodes sequentially stacked on the cell region of the substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel on the cell region and extending through the gate electrodes in the vertical direction, a first lower contact plug on the peripheral circuit region and extending in the vertical direction, a second lower contact plug on the peripheral circuit region adjacent to the first lower contact plug and extending in the vertical direction, and a first upper wiring electrically connected to the first lower contact plug. The first upper wiring is configured to and apply an electrical signal to the first lower contact plug. The second lower contact plug is not electrically connected to an upper wiring configured to apply an electrical signal.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: June 30, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Hoon Kim, Hong-Soo Kim, Ju-Yeon Lee
  • Patent number: 10686214
    Abstract: In some embodiments, an electrode can include a first and second conductive layer. At least one of the first and second conductive layers can include porosity configured to allow electrolyte to flow therethrough. The electrode can also include an electrochemically active layer having electrochemically active material sandwiched between the first and second conductive layers. The electrochemically active layer can be in electrical communication with the first and second conductive layers.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: June 16, 2020
    Assignee: Enevate Corporation
    Inventors: Xiaohua Liu, Giulia Canton, David J. Lee, Shiang Teng, Benjamin Yong Park
  • Patent number: 10665663
    Abstract: An integrated circuit (IC) includes a semiconductor surface layer on a substrate including functional circuitry having circuit elements configured together with a metal-to-polysilicon capacitor on the semiconductor surface layer for realizing at least one circuit function. The metal-to-polysilicon capacitor includes a bottom plate including polysilicon, a capacitor dielectric including at least one capacitor dielectric layer on the bottom plate, a top plate on the capacitor dielectric, and contacts through a pre-metal dielectric layer that contact the top plate and contact the bottom plate. In lateral regions relative to the capacitor the capacitor dielectric layer has a thickness in a range between about 5% and about 50% of a thickness of the capacitor dielectric of the metal-to-polysilicon capacitor.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: May 26, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Poornika Fernandes, Bhaskar Srinivasan, Guruvayurappan Mathur, Abbas Ali, David Matthew Curran, Neil L. Gardner
  • Patent number: 10601424
    Abstract: A semiconductor device includes first, second and third semiconductor regions, each surrounded by an element isolation layer, first and second transistors of the first semiconductor region connected in parallel between first and second nodes, a third transistor of the second semiconductor region between the second node and the first transistor, and a fourth transistor of the third semiconductor region between the second node and the second transistor. Gates of the first and second transistors extend in a first direction and are spaced from each other in a second direction. A first distance which is equal to a longer of two distances between the element isolation layer and the gate electrode of the first transistor in the second direction, is greater than a second distance which is equal to a longer of two distances between the element isolation layer and the gate electrode of the third transistor in the second direction.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: March 24, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Naoaki Kanagawa
  • Patent number: 10593542
    Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes: carrying a substrate alternately stacked an electrode layer and an insulation layer into a chamber; increasing the temperature in the chamber to a predetermined temperature; and supplying hydrogen and material gas including metal simultaneously into the chamber, and supplying oxidizing gas the partial pressure ratio of which to the hydrogen is set so as to provide an atmosphere of reducing the electrode layer, by using an ALD method, and thereby forming, on a surface of the electrode layer and a surface of the insulation layer, a metal oxide layer obtained by oxidizing the metal.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: March 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Furuhashi, Masayuki Tanaka, Shinji Mori, Kenichiro Toratani
  • Patent number: 10586652
    Abstract: A multilayer ceramic capacitor includes a ceramic body including dielectric layers and first and second internal electrodes disposed to face each other with each of the dielectric layers interposed therebetween, and first and second external electrodes disposed on external surfaces of the ceramic body and electrically connected to the first and second internal electrodes, respectively. The ceramic body includes an active portion in which capacitance is formed and cover portions disposed above and below the active portion. Each of the cover portions includes a first region adjacent to an external side surface of the ceramic body and a second region adjacent to an outermost internal electrode and disposed between the first region and the active region. A density of a dielectric material included in the second region is higher than a density of a dielectric material included in the first region.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: March 10, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hyung Soon Kwon, Kyoung Jin Cha, Ji Hong Jo
  • Patent number: 10553673
    Abstract: A method used in forming at least a portion of at least one conductive capacitor electrode of a capacitor that comprises a pair of conductive capacitor electrodes having a capacitor insulator there-between comprises forming an insulative first material comprising an amorphous insulative metal oxide. The amorphous insulative metal oxide is reduced in a reducing-ambient to form a conductive second material from the insulative first material. Such reducing in the reducing-ambient both (a) removes oxygen from and changes the stoichiometry of the metal oxide, and (b) crystallizes the metal oxide into a crystalline state that is conductive.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: February 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Manuj Nahar, Vassil N. Antonov
  • Patent number: 10535660
    Abstract: The present disclosure provides a DRAM cell structure. The DRAM cell structure includes a substrate, a gate structure disposed in the substrate, a first source/drain region and a second source/drain region disposed in the substrate respectively at two sides of the gate structure, a landing pad disposed over the second source/drain region, a plurality of conductive pillars disposed on the landing pad, a conductive layer disposed over the plurality of conductive pillars, and a dielectric layer disposed between the conductive layer and the plurality of conductive pillars. The plurality of conductive pillars have at least a first width and a second width, and the first width and the second width are different from each other.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: January 14, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Da-Zen Chuang, Sheng-Tsung Chen
  • Patent number: 10522415
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, an isolation structure, and a source/drain region. The semiconductor substrate includes a fin. The gate structure is disposed on the fin and is disposed straddling the fin. The isolation structure covers a sidewall and a top surface of the fin. The source/drain region is disposed in the fin and extends beyond the top surface of the fin.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: December 31, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Yu-Cheng Tung, Chih-Wei Yang
  • Patent number: 10510665
    Abstract: A diffusion barrier and a method to form the diffusion bather are disclosed. A trench structure is formed in an Inter Layer Dielectric (ILD). The ILD comprises a dielectric matrix having a first density. A dopant material layer is formed on the trench structure in which the dopant material layer comprises atoms of at least one of a rare-earth element. The ILD and the trench structure are annealed to form a dielectric matrix comprising a second density in one or more regions of the ILD on which the dopant material layer was formed that is greater than the first density. After annealing, the dielectric matrix comprising the second density includes increased bond lengths of oxygen-silicon bonds and/or oxygen-semiconductor bonds, increased bond angles of oxygen-silicon bonds and/or oxygen-semiconductor material bonds, and pores in the dielectric matrix are sealed compared to the dielectric matrix comprising the first density.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: December 17, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ganesh Hegde, Mark Rodder, Jorge Kittl, Chris Bowen
  • Patent number: 10475975
    Abstract: A frame includes first and second leads and a body. The first and second leads contain a metal material. The body contains a non-metal material and has first and second side surfaces. The first and second leads are covered with the body. The first and second leads extend in a first direction to outwardly protrude from the body. The first and second side surfaces are respectively abutted against two ends of the protruding first lead and respectively slanted to the two ends of the protruding first lead by a first angle ?1 and a second angle ?2, which are defined by the following relationship, ?1?0° and the ?1?180°, and the ?2?0° and the ?2?180°. The substance between any two points in each of the first and second side surfaces is non-metal.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: November 12, 2019
    Assignee: LEXTAR ELECTRONICS CORPORATION
    Inventors: Dao-Wei Chen, Huang-Yi Lin, Kun-Jung Wu
  • Patent number: 10438803
    Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: October 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. Gambino, Thomas J. Hartswick, Zhong-Xiang He, Anthony K. Stamper, Eric J. White
  • Patent number: 10312242
    Abstract: A semiconductor memory device is provided, and which includes a substrate, plural gates, plural plugs, a capacitor structure and a conducting cap layer. The gates are disposed within the substrate, and the plugs are disposed on the substrate, with each plug electrically connected to two sides of each gate on the substrate. The capacitor structure is disposed on the substrate, and the capacitor structure includes plural capacitors, with each capacitor electrically connected to the plugs respectively. The conducting cap layer covers the top surface and sidewalls of the capacitor structure. Also, the semiconductor memory device further includes an adhesion layer and an insulating layer. The adhesion layer covers the conducting cap layer and the capacitor structure, and the insulating layer covers the adhesion layer.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: June 4, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tzu-Chieh Chen, Pin-Hong Chen, Chih-Chieh Tsai, Chia-Chen Wu, Yi-An Huang, Kai-Jiun Chang, Tsun-Min Cheng, Yi-Wei Chen
  • Patent number: 10304809
    Abstract: Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the stack, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die and a second semiconductor die stacked over the first semiconductor die. The first semiconductor die includes an upper surface having a first capacitor plate formed thereon, and the second semiconductor die includes a lower surface facing the upper surface of the first semiconductor die and having a second capacitor plate formed thereon. A dielectric material is formed at least partially between the first and second capacitor plates. The first capacitor plate, second capacitor plate, and dielectric material together form a capacitor that stores charge locally within the stack, and that can be accessed by the first and/or second semiconductor dies.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: May 28, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Anthony D. Veches
  • Patent number: 10256289
    Abstract: Methods of forming capacitors include forming a self-assembled pattern of periodic first and second domains using first and second block copolymer materials over a substrate. The second block copolymer material is etched away. Material from the substrate is etched based on a pattern defined by the first block copolymer material to form cavities in the substrate. A capacitor stack is conformally deposited over the substrate, such that the capacitor stack is formed on horizontal surfaces of the substrate and vertical surfaces of the cavities.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kisup Chung, Isabel C. Estrada-Raygoza, Hemanth Jagannathan, Chi-Chun Liu, Yann A. M. Mignot, Hao Tang
  • Patent number: 10153092
    Abstract: A thin-film capacitor including a stacked body having a lower electrode layer, a plurality of dielectric layers stacked on the lower electrode layer, one or more internal electrode layers interposed between the dielectric layers, and an upper electrode layer that is stacked on the opposite side of the lower electrode layer with the dielectric layers and the internal electrode layers interposed between, and a cover layer that covers the stacked body. The stacked body includes opening portions that have the lower electrode layer, opens upward in a stacking direction, and has a side surface formed to include an inclined surface. The cover layer is stacked on the inclined surface of the stacked body. A curved surface with a predetermined shape is formed on the inclined surface for each pair of layers including the dielectric layer forming the inclined surface and the electrode layer, forming the inclined surface.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: December 11, 2018
    Assignee: TDK CORPORATION
    Inventors: Michihiro Kumagae, Akifumi Kamijima, Norihiko Matsuzaka, Junki Nakamoto, Kazuhiro Yoshikawa, Kenichi Yoshida
  • Patent number: 10134712
    Abstract: Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the stack, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die and a second semiconductor die stacked over the first semiconductor die. The first semiconductor die includes an upper surface having a first capacitor plate formed thereon, and the second semiconductor die includes a lower surface facing the upper surface of the first semiconductor die and having a second capacitor plate formed thereon. A dielectric material is formed at least partially between the first and second capacitor plates. The first capacitor plate, second capacitor plate, and dielectric material together form a capacitor that stores charge locally within the stack, and that can be accessed by the first and/or second semiconductor dies.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: November 20, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Anthony D. Veches
  • Patent number: 10090283
    Abstract: Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the stack, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die and a second semiconductor die stacked over the first semiconductor die. The first semiconductor die includes an upper surface having a first capacitor plate formed thereon, and the second semiconductor die includes a lower surface facing the upper surface of the first semiconductor die and having a second capacitor plate formed thereon. A dielectric material is formed at least partially between the first and second capacitor plates. The first capacitor plate, second capacitor plate, and dielectric material together form a capacitor that stores charge locally within the stack, and that can be accessed by the first and/or second semiconductor dies.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: October 2, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Anthony D. Veches
  • Patent number: 10026555
    Abstract: A device and method for providing electrical energy storage of high specific energy density. The device contains one or more layers of high dielectric constant material, such as Barium Titanate or Hexagonal Barium Titanate, sandwiched between electrode layers made up of a variety of possible conducting materials. The device includes additional insulating layers including carbon, such as carbon formed into diamond or a diamond-like arrangement for providing between the electrodes and the dielectric layer to provide for very high breakdown voltages. The layers can be created by a variety of methods including laser deposition and assembled to form a capacitor device provides the high energy density storage.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: July 17, 2018
    Inventors: Martin A. Stuart, Stephen L. Cunningham
  • Patent number: 9997591
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and capacitor electrically connected to the substrate. The capacitor includes a lower electrode, a dielectric layer disposed on the lower electrode, and an upper electrode disposed on the dielectric layer. The upper electrode includes a first electrode on the dielectric layer and a second electrode on the first electrode, such that the first electrode is disposed between the dielectric layer and the second electrode. The first electrode contains metal oxynitride having a formula of MxOyNz, in which an atomic ratio (y/x) of oxygen (O) to metallic element (M) is a value in the range from 0.5 to 2.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: June 12, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-su Lee, Gihee Cho, Dongkyun Park, Hyun-Suk Lee, Heesook Park, Jongmyeong Lee
  • Patent number: 9923077
    Abstract: A method of curing a dielectric layer, such as a dielectric layer that has a relatively small thickness and/or a narrow width or a complicated shape, is provided. The method of curing a dielectric layer for the manufacture of a semiconductor device includes providing the dielectric layer, wherein the dielectric layer is on a semiconductor layer; forming a first metal-containing layer on the dielectric layer; forming a curing atom screening region in an upper portion of the first metal-containing layer by injecting screening atoms onto an upper surface of the first metal-containing layer; injecting curing atoms into the first metal-containing layer through the upper surface of the first metal-containing layer; and flowing the curing atoms into the dielectric layer in an atmosphere at a first temperature.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: March 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoon-tae Hwang, Ki-joong Yoon, Moon-kyu Park, Sang-jin Hyun, Hoon-joo Na
  • Patent number: 9917007
    Abstract: A method of forming an opening pattern including the following steps is provided. An ultra low dielectric constant layer, a dielectric hard mask layer and a patterned metal hard mask layer are sequentially formed on a substrate. A portion of the dielectric hard mask layer is removed to form a patterned dielectric hard mask layer by using the patterned metal hard mask layer as a mask. The patterned metal hard mask layer is removed after forming the patterned dielectric hard mask layer. A portion of the ultra low dielectric constant layer is removed to form a first opening by using the patterned dielectric hard mask layer as a mask.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: March 13, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Yi-Yu Wu, Bin-Siang Tsai
  • Patent number: 9881865
    Abstract: A method of forming a composite dielectric material can be provided by performing a first deposition cycle to form a first dielectric material and performing a second deposition cycle to form a second dielectric material on the first dielectric material, wherein the first and second dielectric materials comprise different dielectric materials selected from a list consisting of a transition metal nitride, a transition metal oxide, a transition metal carbide, a transition metal silicide, a post-transition metal nitride, a post-transition metal oxide, a post-transition metal carbide, a post-transition metal silicide, a metalloid nitride, a metalloid oxide, and a metalloid carbide.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: January 30, 2018
    Assignees: Samsung Electronics Co., Ltd., The Board of Trustees of the Leland Stanford Junior University
    Inventors: Ki-Hyun Kim, Friedrich B. Prinz, Jinsung Kang, Youngdong Lee, John Provine, Peter Schindler, Stephen P. Walch, Yongmin Kim, Hyo Jin Kim
  • Patent number: 9806328
    Abstract: Electrodes and methods of forming electrodes are described herein. The electrode can be an electrode of an electrochemical cell or battery. The electrode includes a current collector and a film in electrical communication with the current collector. The film may include a carbon phase that holds the film together. The electrode further includes an electrode attachment substance that adheres the film to the current collector.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: October 31, 2017
    Assignee: Enevate Corporation
    Inventors: Benjamin Yong Park, Ian R. Browne, Stephen W. Schank, Steve Pierce
  • Patent number: 9716013
    Abstract: A method of etching a metal containing layer including a metal including material includes providing a substrate including a top semiconductor surface having the metal containing layer thereon. A photoresist pattern is formed from a photoresist layer on the metal containing layer including forming sloped edge regions of the photoresist layer, wherein the sloped edge regions have an average angle over a full length of the sloped edge regions of from ten (10) to fifty (50) degrees. The metal containing layer is dry etched using the photoresist pattern, wherein the sloped edge regions of the photoresist layer reduce deposition and growth of an etch byproduct including the metal including material into sidewalls of the photoresist layer (metal/polymer sidewall defect) as compared to a conventional vertical (or near-vertical) edge of the photoresist layer.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: July 25, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Elizabeth Costner Stewart, Neng Jiang, Yung Shan Chang, Ricky Alan Jackson
  • Patent number: 9685498
    Abstract: To form a dielectric layer, an organometallic precursor is adsorbed on a substrate loaded into a process chamber. The organometallic precursor includes a central metal and ligands bound to the central metal. An inactive oxidant is provided onto the substrate. The inactive oxidant is reactive with the organometallic precursor. An active oxidant is also provided onto the substrate. The active oxidant has a higher reactivity than that of the inactive oxidant.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: June 20, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Yeol Kang, Suk-Jin Chung, Youn-Soo Kim, Jae-Hyoung Choi, Jae-Soon Lim, Min-Young Park
  • Patent number: RE46798
    Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: April 17, 2018
    Assignee: Longitude Semiconductor S.a.r.l.
    Inventor: Toshiyuki Hirota