Abstract: A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer.

Abstract: A method of forming a capacitor comprises forming a first electrode of the capacitor over a substrate. The first electrode includes a bottom conductive plane and a plurality of first vertical conductive structures on the bottom conductive plane. The method also comprises forming an insulating structure over the first electrode. The method further comprises forming a second electrode of the capacitor over the insulating structure. The second electrode includes a top conductive plane and a plurality of second vertical conductive structures under the top conductive plane. The first vertical conductive structures of the plurality of first vertical conductive structures and the second vertical conductive structures of the plurality of second vertical conductive structures are interlaced with each other.

Abstract: Embodiments of MIM capacitors may be embedded into a thick IMD layer with enough thickness (e.g., 10 K?˜30 K?) to get high capacitance, which may be on top of a thinner IMD layer. MIM capacitors may be formed among three adjacent metal layers which have two thick IMD layers separating the three adjacent metal layers. Materials such as TaN or TiN are used as bottom/top electrodes & Cu barrier. The metal layer above the thick IMD layer may act as the top electrode connection. The metal layer under the thick IMD layer may act as the bottom electrode connection. The capacitor may be of different shapes such as cylindrical shape, or a concave shape. Many kinds of materials (Si3N4, ZrO2, HfO2, BST . . . etc.) can be used as the dielectric material. The MIM capacitors are formed by one or two extra masks while forming other non-capacitor logic of the circuit.

Abstract: Techniques and structure are disclosed for providing a MIM capacitor having a generally corrugated profile. The corrugated topography is provisioned using sacrificial, self-organizing materials that effectively create a pattern in response to treatment (heat or other suitable stimulus), which is transferred to a dielectric material in which the MIM capacitor is formed. The self-organizing material may be, for example, a layer of directed self-assembly material that segregates into two alternating phases in response to heat or other stimulus, wherein one of the phases then can be selectively etched with respect to the other phase to provide the desired pattern. In another example case, the self-organizing material is a layer of material that coalesces into isolated islands when heated. As will be appreciated in light of this disclosure, the disclosed techniques can be used, for example, to increase capacitance per unit area, which can be scaled by etching deeper capacitor trenches/holes.

Abstract: A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.

Abstract: A method of fabricating a semiconductor device is provided and includes forming one or more molding layers on a substrate, forming a silicon mask layer, first and second mask layers, and a mask pattern having a different etch selectivity to be vertically aligned on the molding layer, patterning the second mask layer with a second mask pattern using the mask pattern as an etching mask, patterning the first mask layer with a first mask pattern using the second mask pattern as an etching mask, patterning the silicon mask layer with a silicon mask pattern using the first mask pattern as an etching mask, changing the silicon mask pattern to a hard mask pattern having an improved etch selectivity by doping impurities into the silicon mask pattern, forming a hole having a high aspect ratio contact (HARC) structure vertically passing through the molding layer using the hard mask pattern as an etching mask, and removing the hard mask pattern.

Abstract: The embodiments describe methods and apparatuses for combinatorial optimization of interlayer parameters for capacitor stacks. The capacitor stacks may include a substrate, an insulating layer disposed on the substrate, a ruthenium disposed electrode on the insulating layer, and an interlayer disposed on the ruthenium electrode, where the interlayer is configured to prevent etching of the electrode when growing a high-k dielectric using an ozone-based precursor. The parameters for forming the interlayer may include interlayer thickness, precursor chemistry, oxidant strength, precursor purge times, oxidant purge times, and other suitable parameters. Each of these parameters may be evaluated through deposition of the capacitor stacks through a combinatorial optimization process. Thus, a plurality of different parameters may be evaluated with a single substrate to ascertain associated properties of Ruthenium electrode etching in a combinatorial manner.

Abstract: A semiconductor device comprises a conductor film and a capacitor comprising a lower electrode provided on the conductor film. The conductor film includes a first conductive film containing a first metal, a second conductive film containing a second metal on the first conductive film, and an oxide film of the second metal on the second conductive film. The oxide film of the second metal has a lower electric resistivity than an oxide film of the first metal.

Abstract: A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.

Abstract: A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.

Abstract: A capacitor of a semiconductor device includes a capacitor structure configured to include electrode layers and dielectric layers alternately stacked, edge regions each stepwise patterned, and a central region disposed between the edge regions, sacrificial layers disposed within the respective electrode layers in the edge regions of the capacitor structure, and support plugs formed in the central region of the capacitor structure and configured to penetrate the electrode layers and the dielectric layers.

Abstract: A method for fabricating passive devices such as resistors and capacitors for a 3D non-volatile memory device. In a peripheral area of a substrate, alternating layers of a dielectric such as oxide and a conductive material such as heavily doped polysilicon or metal silicide are provided in a stack. The substrate includes one or more lower metal layers connected to circuitry. One or more upper metal layers are formed above the stack. Contact structures are formed which extend from the layers of conductive material to portions of the one or more upper metal layers so that the layers of conductive material are connected to one another in parallel or serially by the contact structures and the at least one upper metal layer. Additional contact structures can connect the circuitry to the one or more upper metal layers. The passive device can be fabricated concurrently with a 3D memory array using common processing steps.

Abstract: A device manufacturing method includes: sequentially forming a first sacrificial film, a first support film, a second sacrificial film, and a second support film on a semiconductor substrate; forming a hole to pass through these films; forming a crown-shaped electrode covering an inner surface of the hole and connected to the second support film and the first support film; forming a first opening in the second support film into a first pattern designed such that the connection between the crown-shaped electrode and the second support film is at least partially maintained; removing at least a part of the second sacrificial film through the first opening; forming a second opening in the first support film with use of the first opening; and removing the first sacrificial film through the second opening. This method is able to prevent misalignment of openings between the support films.

Abstract: A semiconductor construct includes a semiconductor substrate and connection pads provided on the semiconductor substrate. Some of the connection pads are connected to a common wiring and at least one of the remaining of the connection pads are connected to a wiring. The construct also includes a first columnar electrode provided to be connected to the common wiring and a second columnar electrode provided to be connected to a connection pad portion of the wiring.

Abstract: A method of forming a non-volatile memory device, includes forming a first electrode above a substrate, forming a dielectric layer overlying the first electrode, forming an opening structure in a portion of the dielectric layer to expose a surface of the first electrode having an aspect ratio, forming a resistive switching material overlying the dielectric layer and filling at least a portion of the opening structure using a deposition process, the resistive switching material having a surface region characterized by a planar region and an indent structure, the indent structure overlying the first electrode, maintaining a first thickness of resistive switching material between the planar region and the first electrode, maintaining a second thickness of resistive switching material between the indent structure and the first electrode, wherein the first thickness is larger than the second thickness, and forming a second electrode overlying the resistive switching material including the indent structure.

Abstract: A semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, the semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film.

Abstract: A manufacturing method of a semiconductor device includes the following steps. Firstly, a lower electrode is formed over a substrate (semiconductor substrate). Successively, the lower electrode is primarily crystallized. Successively, a capacitance dielectric layer is formed over the lower electrode after primarily crystallized. Successively, the capacitance dielectric layer is secondarily crystallized. Then, an upper electrode is formed over the capacitance dielectric layer.

Abstract: An integrated circuit device includes a substrate, and a first interlayer dielectric layer on the substrate that includes a first conductive layer and a second conductive layer. The integrated circuit device also includes a first conductive stack including a third conductive layer coupled to a portion of the second conductive layer with a first via. The integrated circuit device further includes a second conductive stack comprising a fourth conductive layer directly on a portion of the third conductive layer that is isolated from the substrate. The integrated circuit device also includes a second interlayer dielectric layer surrounding the third conductive layer and the fourth conductive layer.

Abstract: A method of forming a hydrophobic surface on a semiconductor device structure. The method comprises forming at least one structure having at least one exposed surface comprising titanium atoms. The at least one exposed surface of at least one structure is contacted with at least one of an organo-phosphonic acid and an organo-phosphoric acid to form a material having a hydrophobic surface on the at least one exposed surface of the least one structure. A method of forming a semiconductor device structure and a semiconductor device structure are also described.

Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a low band gap dielectric layer disposed between two higher band gap dielectric layers. The high band gap dielectric layers can be doped with doping materials to form traps at energy levels higher than the operating voltage of the memory device.

Abstract: Disclosed are a semiconductor device comprising a capacitor and a double-layer metal contact and a method fabricating the same. The method comprising: forming a gate of a peripheral transistor for a peripheral circuit; forming a first contact and a first peripheral circuit wiring layer pattern on a first interlayer insulating layer; forming a second contact and a second peripheral circuit wiring layer pattern; selectively removing a portion of the second interlayer insulating layer in a cell region; forming a mold layer covering the second peripheral circuit wiring layer pattern; forming storage nodes passing through the mold layer; removing the mold layer; forming a dielectric layer and a plate node, which cover the storage nodes; forming a third interlayer insulating layer; and forming third contacts passing through the third interlayer insulating layer.

Abstract: Disclosed herein is a method includes: forming first and second cavities, the first cavity having a first width, each of the second cavities having a second width narrower than the first width; forming a first conductive layer buried in the second cavities and formed on bottom and side surface of the semiconductor substrate defined by the first cavity so that a third cavity is defined by the first conductive layer formed on the bottom and side surface of the semiconductor substrate; subjecting an etch back process to the first conductive layer so that a first conductive portion is formed at a bottom corner of the first cavity, further a fourth cavity is formed on the semiconductor substrate uncovered with the first conductive portion in the first cavity; and forming a first insulating layer in the fourth cavity and in the second cavity.

Abstract: A concentric capacitor structure generally comprising concentric capacitors is disclosed. Each concentric capacitor comprises a first plurality of perimeter plates formed on a first layer of a substrate and a second plurality of perimeter plates formed on a second layer of the substrate. The first plurality of perimeter plates extend in a first direction and the second plurality of perimeter plates extend in a second direction different than the first direction. A first set of the first plurality of perimeter plates is electrically coupled to a first set of the second plurality of perimeter plates and a second set of the first plurality of perimeter plates is electrically coupled to a second set of the second plurality of perimeter plates. A plurality of capacitive cross-plates are formed in the first layer such that each cross-plate overlaps least two of the second plurality of perimeter plates.

Abstract: A method for producing an integrated device including an MIM capacitor. The method includes the steps of providing a functional substrate including functional circuits of the integrated device, forming a first conductive layer including a first plate of the capacitor on the functional substrate; the first plate has a first melting temperature. The method further includes depositing a layer of insulating material including a dielectric layer of the capacitor on a portion of the first conductive layer corresponding to the first plate; the layer of insulating material is deposited at a process temperature being lower than the first melting temperature. The method further includes forming a second conductive layer including a second plate of the capacitor on a portion of the layer of insulating material corresponding to the dielectric layer. In the solution according to an embodiment of the invention, the first melting temperature is higher than 500° C.

Abstract: Capacitor structures capable of providing both low-voltage capacitors and high-voltage capacitors are described herein. In one embodiment, a capacitor structure comprises a low-voltage capacitor and a high-voltage capacitor. The low-voltage capacitor comprises a first electrode formed from a first metal layer, a second electrode formed from a second metal layer, a third electrode formed from a third metal layer, a first dielectric layer between the first and second electrodes, and a second dielectric layer between the second and third electrodes. The high-voltage capacitor comprises a fourth electrode formed from the first metal layer, a fifth electrode formed from the third metal layer, and a third dielectric layer between the fourth and fifth electrodes, wherein the third dielectric layer is thicker than either the first dielectric layer or the second dielectric layer.

Abstract: A semiconductor device includes a substrate and a plurality of storage nodes on the substrate and extending in a vertical direction relative to the substrate. A lower support pattern is in contact with the storage nodes between a bottom and a top of the storage nodes, the lower support pattern spaced apart from the substrate in the vertical direction, and the lower support pattern having a first maximum thickness in the vertical direction. An upper support pattern is in contact with the storage nodes above the lower support pattern relative to the substrate, the upper support pattern spaced apart from the lower support pattern in the vertical direction, and the lower support pattern having a second maximum thickness in the vertical direction that is greater than the first maximum thickness of the lower support pattern.

Abstract: Embodiments of integrated passive devices (e.g., metal insulator metal, or MIM, capacitors) and methods of their formation include depositing a composite electrode over a semiconductor substrate (e.g., on a dielectric layer above the substrate surface), and depositing an insulator layer over the composite electrode. The composite electrode includes an underlying electrode and an overlying electrode deposited on a top surface of the underlying electrode. The underlying electrode is formed from a first conductive material (e.g., AlCuW), and the overlying electrode is formed from a second, different conductive material (e.g., AlCu). The top surface of the underlying electrode may have a relatively rough surface morphology, and the top surface of the overlying electrode may have a relatively smooth surface morphology. For high frequency, high power applications, both the composite electrode and the insulator layer may be thicker than in some conventional integrated passive devices.

Abstract: The present invention relates to an electronic component, that comprises, on a substrate, at least one integrated MIM capacitor, (114) an electrically insulating first cover layer (120) which partly or fully covers the top capacitor electrode (118) and is made of a lead-containing dielectric material, and a top barrier layer (122) on the first cover layer. The top barrier layer serves for avoiding a reduction of lead atoms comprised by the first cover layer under exposure of the first cover layer to a reducing substance. An electrically insulating second cover layer (124) on the top barrier layer has a dielectric permittivity smaller than that of the first cover layer establishes a low parasitic capacitance of the cover-layer structure. The described cover-layer structure with the intermediate top barrier layer allows to fabricate a high-accuracy resistor layer (126.1) on top.

Abstract: An integrated circuit and a manufacturing method thereof are provided. A chip size can be reduced by forming a memory device in which a ferroelectric capacitor region is laminated on a DRAM. The integrated circuit includes a cell array region having a capacitor, a peripheral circuit region, and a ferroelectric capacitor region being formed on an upper layer of the cell array region and the peripheral circuit region, and having a ferroelectric capacitor device.

Abstract: A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.

Abstract: Methods and devices related to a plurality of high breakdown voltage embedded capacitors are presented. A semiconductor device may include gate material embedded in an insulator, a plurality of metal contacts, and a plurality of capacitors. The plurality of capacitors may include a lower electrode, a dielectric formed so as to cover a surface of the lower electrode, and an upper electrode formed on the dielectric. Further, the plurality of contacts may connect each of the lower electrodes of the plurality of capacitors to the gate material. The plurality of capacitors may be connected in series via the gate material.

Abstract: In accordance with the teachings described herein, a multi-level thin film capacitor on a ceramic substrate and method of manufacturing the same are provided. The multi-level thin film capacitor (MLC) may include at least one high permittivity dielectric layer between at least two electrode layers, the electrode layers being formed from a conductive thin film material. A buffer layer may be included between the ceramic substrate and the thin film MLC. The buffer layer may have a smooth surface with a surface roughness (Ra) less than or equal to 0.08 micrometers (um).

Abstract: The present invention provides a semiconductor structure for testing MIM capacitors. The semiconductor structure comprises: a first metal layer comprising at least a first circuit area and a second circuit area; a second metal layer located below the first metal layer with a first dielectric layer lying therebetween and connected with the second circuit area; a top plate located within the first dielectric layer closer to the first metal layer and connected with the first circuit area; a bottom plate located within the first dielectric layer closer to the second metal layer and separated from the top plate with an insulation layer therebetween and connected with the second circuit area. The second metal layer is connected with the substrate through a first electric pathway so as to form a second electric pathway from the top plate to the substrate when an electric leakage region exists in the insulation layer.

Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.

Abstract: A manufacturing method for a semiconductor device, the method including forming a thin film transistor by forming a polysilicon thin film on an insulating substrate, forming a gate electrode via a gate insulating film, and forming source/drain regions and a channel region by ion implantation in the polysilicon thin film by using the gate electrode as a mask, forming an interconnection layer on an interlayer dielectric film covering this thin film transistor and forming a first contact to be connected to the thin film transistor through the interlayer dielectric film, forming a silicon hydronitride film on the interlayer dielectric film so as to cover the interconnection layer, forming a lower electrode on this silicon hydronitride film and forming a second contact to be connected to the interconnection layer through the silicon hydronitride film, and forming a ferroelectric layer on the lower electrode.

Abstract: Disclosed herein is a composite material comprising a relaxor ferroelectric material and a hydrazine-reduced graphene oxide, wherein the weight ratio of the composite material to the hydrazine-reduced graphene oxide is 9:1 to 200:1. The composite materials have high dielectric permittivity and low dielectric losses and can be used to manufacture various high dielectric permittivity components.

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of an compound high k dielectric material. The dielectric material further comprises a dopant. One component of the compound high k dielectric material is present in a concentration between about 30 atomic % and about 80 atomic and more preferably between about 40 atomic % and about 60 atomic %. In some embodiments, the compound high k dielectric material comprises an alloy of TiO2 and ZrO2 and further comprises a dopant of Al2O3. In some embodiments, the compound high k dielectric material comprises an admixture of TiO2 and HfO2 and further comprises a dopant of Al2O3.

Abstract: A CMOS device for reducing a radiation-induced charge collection and a method for fabricating the same. In the CMOS device, a heavily doped charge collection-suppressed region is disposed directly under the source region and the drain region. The region has a doping type opposite that of the source region and the drain region, and has a doping concentration not less than that of the source region and the drain region. The charge collection-suppressed region has a lateral part slightly less than or equal to that of the source region and the drain region, and has a lateral range toward to the channel not exceed the edges of the source region and the drain region. The CMOS device may greatly reduce a range of the funnel that appears under the action of a single particle, so that charges collected instantaneously under a force of an electric field may be reduced.

Abstract: Some implementations provide an integrated device that includes a capacitor and an inductor. The inductor is electrically coupled to the capacitor. The inductor and the capacitor are configured to operate as a filter for an electrical signal in the integrated device. The inductor includes a first metal layer of a printed circuit board (PCB), a set of solder balls coupled to the PCB, and a second metal layer in a die. In some implementations, the capacitor is located in the die. In some implementations, the capacitor is a surface mounted passive device on the PCB. In some implementations, the first metal layer is a trace on the PCB. In some implementations, the inductor includes a third metal layer in the die. In some implementations, the second metal layer is an under bump metallization (UBM) layer of the die, and the third metal is a redistribution layer of the die.

Abstract: A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.

Abstract: Provided is a method for fabricating a phase change memory device. The method includes forming a plurality of bottom electrodes on a substrate, forming a first mold layer on the substrate to extend in a first direction where the bottom electrodes are exposed, forming a second mold layer on the substrate, the second mold layer extending in a second direction orthogonal to the first direction to expose parts of the bottom electrodes, forming a phase change material layer on the first and second mold layers to be connected to parts of the bottom electrodes dividing the phase change material layer as a plurality of phase change layers respectively connected to the parts of the bottom electrodes and forming a plurality of top electrodes on the phase change layers.

Abstract: A stacked capacitor structure of the instant disclosure comprises a substrate and a plurality of stacked capacitors. The substrate has an insulating layer formed thereon and a plurality of contact plugs in the insulating layer, wherein the contact plugs are exposed on the upper surface of the insulating layer. Specially, each of the stacked capacitors comprises a lower electrode, a dielectric layer, and an upper electrode. The lower electrode is arranged on one of the contact plugs and has a columnar base portion and a crown shaped upper portion. The dielectric layer is arranged on the lower electrode and covers the outer surface of the lower electrode. The upper electrode is arranged above the lower electrode, wherein the dielectric layer is intermediately between the upper electrode and the lower electrode.

Abstract: An integrated circuit structure includes one or more external contact pads with decoupling capacitors, such as metal-insulator-metal (MIM) capacitors, formed directly thereunder. In an embodiment, the decoupling capacitors are formed below the first metallization layer, and in another embodiment, the decoupling capacitors are formed in the uppermost inter-metal dielectric layer. A bottom plate of the decoupling capacitors is electrically coupled to one of Vdd and Vss, and the top plate of the decoupling capacitors is electrically coupled to the other. The decoupling capacitors may include an array of decoupling capacitors formed under the external contact pads and may include one or more dummy decoupling capacitors. The one or more dummy decoupling capacitors are MIM capacitors in which at least one of the top plate and the bottom plate is not electrically coupled to an external contact pad.

Abstract: A method of forming a phase change material layer pattern includes forming a phase change material layer partially filling an opening through an insulating interlayer. A plasma treatment process is performed on the phase change material layer to remove an oxide layer on a surface of the phase change material layer. A heat treatment process is performed on the phase change material layer to remove a void or a seam in the phase change material layer, sufficiently filling the opening.

Abstract: As for a bypass capacitor, a first capacitor insulating film, together with a tunnel insulating film of a storage element, is formed of a first insulating film, a first electrode being a lower electrode, together with floating gate electrodes of the storage element, is formed of a doped·amorphous silicon film (a crystallized one), a second capacitor insulating film, together with a gate insulating film of transistors of 5 V in a peripheral circuit, is formed of a second insulating film, and a second electrode being an upper electrode, together with control gate electrodes of the storage element and gate electrodes of the transistors in the peripheral circuit, is formed of a polycrystalline silicon film.

Abstract: A capacitive element, includes: an active region parted by an element isolation region formed in a semiconductor substrate; a first electrode formed of a diffusion layer in the active region; an insulating layer formed on the first electrode; and a second electrode formed on a planar surface of the first electrode via the insulating layer, wherein the second electrode is formed within the active region and within the first electrode in a planar layout.

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current and low EOT involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited first dielectric layer. The first high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous, doped high k second dielectric material is form on the first dielectric layer. The dopant concentration and the thickness of the second dielectric layer are chosen such that the second dielectric layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the second dielectric layer is formed on the second dielectric layer.

Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.

Abstract: Capacitance blocks (first block and second block) respectively formed on two different adjacent common pad electrodes are electrically connected in series through an upper electrode. A distance between two adjacent capacitance blocks connected in series through an upper electrode film for the upper electrode corresponds to a distance between opposing lower electrodes disposed in an outermost perimeter of each capacitance block, and is two or less times than a total film thickness of the upper electrode film embedded between the two adjacent capacitance blocks.

Abstract: A dielectric wafer has, on top of its front face, a front electrical connection including an electrical connection portion. A blind hole passes through from a rear face of the wafer to at least partially reveal a rear face of the electrical connection portion. A through capacitor is formed in the blind hole. The capacitor includes a first conductive layer covering the lateral wall and the electrical connection portion (forming an outer electrode), a dielectric intermediate layer covering the first conductive layer (forming a dielectric membrane), and a second conductive layer covering the dielectric intermediate layer (forming an inner electrode). A rear electrical connection is made to the inner electrode.