Abstract: According to various aspects, a memory cell is provided, the memory cell including: a first electrode; a second electrode; and a memory structure disposed between the first electrode and the second electrode, the first electrode, the second electrode, and the memory structure forming a memory capacitor, wherein at least one of the first electrode or the second electrode includes: a first electrode layer including a first material having a first microstructure; a functional layer in direct contact with the first electrode layer; and a second electrode layer in direct contact with the functional layer, the second electrode layer including a second material having a second microstructure different from the first microstructure.

Abstract: Some embodiments include an integrated structure having a semiconductor base and an insulative frame over the semiconductor base. The insulative frame has vertically-spaced sheets of first insulative material, and pillars of second insulative material between the vertically-spaced sheets. The first and second insulative materials are different from one another. Conductive plates are between the vertically-spaced sheets and are directly against the insulative pillars. Some embodiments include capacitors, and some embodiments include methods of forming capacitors.

Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor is provided. The MIM capacitor includes a substrate, a first metal layer, a deposition structure, a dielectric layer and a second metal layer. The first metal layer is disposed on the substate and has a planarized surface. The deposition structure is disposed on the first metal layer, and at least a portion of the deposition structure extends into the planarized surface, wherein the first metal layer and the deposition structure have the same material. The dielectric layer is disposed on the deposition structure. The second metal layer is disposed on the dielectric layer.

Abstract: A method of making a semiconductor device includes steps related to forming source and drain wells of a transistor in a semiconductor substrate; forming a gate electrode of the transistor over the semiconductor substrate; forming an isolation structure in the semiconductor substrate adjacent to the transistor; and depositing a first inter-dielectric layer (ILD) material over the transistor and the isolation structure. The method also includes steps for depositing a capacitor film stack over the first ILD material, forming a pattern in the capacitor film stack over the isolation structure, and forming a capacitor plate by etching a conductive material of the capacitor film stack. Etching the conductive material includes performing a liquid etch process with a selectivity of at least 16 with regard to other materials in the capacitor film stack.

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

Abstract: A method for fabricating a crown capacitor includes: forming a first supporting layer over a substrate; forming a second supporting layer above the first supporting layer; alternatively stacking first and second sacrificial layers between the first and second supporting layers to collectively form a stacking structure; forming a recess extending through the stacking structure; performing an etching process to the first sacrificial layers at a first etching rate and the second sacrificial layers at a second etching rate greater than the first etching rate, such that each second sacrificial layer and immediately-adjacent two of the first sacrificial layers collectively define a concave portion; forming a first electrode layer over a surface of the recess in which the first electrode layer has a wavy structure; removing the first and second sacrificial layers; and forming a dielectric layer and a second electrode layer over the first electrode layer.

Abstract: A stacked capacitor includes a substrate having a first ILD layer thereon and a source conductive plate in the first ILD layer; a second ILD layer disposed on the first ILD layer; and a stacked capacitor area in the second ILD layer. The stacked capacitor area partially exposes the source conductive plate. A fin-shaped structure is disposed on the source conductive plate within the stacked capacitor area. The fin-shaped structure includes horizontal fins and vertical fins. A widened central hole penetrates through the fin-shaped structure and partially exposes the source conductive plate. A first conductive layer is disposed on the fin-shaped structure and the source conductive plate in the widened central hole. A capacitor dielectric layer is disposed on the first conductive layer. A second conductive layer is disposed on the capacitor dielectric layer.

Abstract: Methods, apparatuses, and systems related to forming a capacitor column using a sacrificial material are described. An example method includes patterning a surface of a semiconductor substrate having: a first silicate material over the substrate, a first nitride material over the first silicate material, a sacrificial material over the first nitride material, a second silicate material over the sacrificial material, and a second nitride material over the second silicate material. The method further includes forming a column of capacitor material in an opening through the first silicate material, the first nitride material, the sacrificial material, the second silicate material, and the second nitride material. The method further includes removing the sacrificial material.

Abstract: The present invention provides a semiconductor structure comprising a substrate, a cell region defined on the substrate, a plurality of lower electrodes of the capacitor structures located in the cell region, an top support structure, contacting a top region of the lower electrode structure, and at least one middle support structure located between the substrate and the top support structure, contacting a middle region of the lower electrode structure, wherein when viewed in a top view, the top support structure and the middle support structure do not completely overlapped with each other.

Abstract: A topically applied circulation enhancing agent suited for application over the entire body which has good transdermal absorptivity and causes little irritation is provided.

Abstract: A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane.

Abstract: Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material having a substrate surface and a plurality of hemispherical grained silicon (“HSG”) structures on the substrate surface of the substrate material. The solid state lighting device also includes a semiconductor material on the substrate material, at least a portion of which is between the plurality of HSG structures.

Abstract: The present disclosure relates to a method of gettering that provides for a high efficiency gettering process by depositing a gettering material on a roughened substrate surface, and an associated apparatus. In some embodiments, the method is performed by providing a substrate into a processing chamber having residual gases. One or more cavities are formed in the substrate at locations between bonding areas on a top surface of the substrate. Respective cavities have roughened interior surfaces that vary in a plurality of directions. A getter layer is deposited into the one or more cavities. The roughened interior surfaces of the one or more cavities enable the substrate to more effectively absorb the residual gases, thereby increasing the efficiency of the gettering process.

Abstract: A contact structure includes a permanent antireflection coating formed on a substrate having contact pads. A patterned dielectric layer is formed on the antireflective coating. The patterned dielectric layer and the permanent antireflective coating form openings. The openings correspond with locations of the contact pads. Contact structures are formed in the openings to make electrical contact with the contacts pads such that the patterned dielectric layer and the permanent antireflective coating each have a conductively filled region forming the contact structures.

Abstract: A method of forming a capacitor structure includes forming a mold layer on a substrate, in which the substrate includes a plurality of plugs therein, partially removing the mold layer to form a plurality of openings, in which the plugs are exposed by the openings, forming a plurality of lower electrodes filling the openings, in which the lower electrodes have a pillar shape, removing an upper portion of the mold layer to expose upper portions of the lower electrodes, forming a supporting pattern on exposed upper sidewalls of the lower electrodes and on the mold layer, removing the mold layer, and sequentially forming a dielectric layer and an upper electrode on the lower electrodes and the supporting pattern.

Abstract: Provided is a silicon structure with a three-dimensionally complex shape. Further provided is a simple and easy method for manufacturing the silicon structure with the use of a phenomenon in which an ordered pattern is formed spontaneously to form a nano-structure. Plasma treatment under hydrogen atmosphere is performed on an amorphous silicon layer and the following processes are performed at the same time: a reaction process for growing microcrystalline silicon on a surface of the silicon layer and a reaction process for etching the amorphous silicon layer which is exposed, so that a nano-structure including an upper structure in a microcrystalline state and a lower structure in an amorphous state, over the silicon layer is formed; accordingly, a silicon structure with a three-dimensionally complex shape can be provided.

Abstract: A method is provided for forming a nitrided high-k film in an atomic layer deposition process (ALD) process. The method includes receiving a substrate in a process chamber, maintaining the substrate at a temperature sufficient for ALD of a nitrided high-k film, and depositing the nitrided high-k film on the substrate by exposing the substrate to a gas pulse sequence that includes, in any order: a) exposing the substrate to a gas pulse comprising a metal-containing precursor, b) exposing the substrate to a gas pulse comprising an oxygen-containing gas, and c) exposing the substrate to a gas pulse comprising trisilylamine gas, where the exposing the substrate to the trisilylamine gas yields the nitrided high-k film that includes nitrogen and that is substantially free of silicon, and repeating the gas pulse sequence. A trisilylamine gas exposure may also be used to nitride a deposited high-k film.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer.

Abstract: The present invention relates to methods of making capacitors for use in surveillance/identification tags or devices, and methods of using such surveillance/identification devices. The capacitors manufactured according to the methods of the present invention and used in the surveillance/identification devices described herein comprise printed conductive and dielectric layers. The methods and devices of the present invention improve the manufacturing tolerances associated with conventional metal-plastic-metal capacitor, as well as the deactivation reliability of the capacitor used in a surveillance/identification tag or device.

Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.

Abstract: A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.

Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor or DRAM cell. In such a device, a high-K zirconia-based layer may be used as the primary dielectric together with a relatively inexpensive metal electrode based on titanium nitride. To prevent corruption of the electrode during device formation, a thin barrier layer can be used seal the electrode prior to the use of a high temperature process and a (high-concentration or dosage) ozone reagent (i.e., to create a high-K zirconia-based layer). In some embodiments, the barrier layer can also be zirconia-based, for example, a thin layer of doped or un-doped amorphous zirconia. Fabrication of a device in this manner facilitates formation of a device with dielectric constant of greater than 40 based on zirconia and titanium nitride, and generally helps produce less costly, increasingly dense DRAM cells and other semiconductor structures.

Abstract: The present disclosure describes methods of fabricating a semiconductor device. An exemplary method includes forming a metal pattern on a substrate and etching the metal pattern using an etchant including at least an alkaline solution and an oxidant to form a metal electrode, where at least a portion of the surface of the metal electrode is uneven.

Abstract: A method of forming a capacitor structure comprises: forming a doped polysilicon layer on an underlying dielectric layer; forming a dielectric stack on the doped polysilicon layer; forming a contact hole in the dielectric stack to expose a surface region of the doped polysilicon layer; forming a conductive contact plug that fills the contact hole and is in contact with the exposed surface of the doped polysilicon layer; forming a plurality of trenches in the dielectric stack such that each trench exposes a corresponding surface region of the doped polysilicon layer; forming a conductive bottom capacitor plate on exposed surfaces of the of the dielectric stack and on exposed surfaces of the doped polysilicon layer; forming a capacitor dielectric layer on the bottom capacitor plate; and forming a conductive top capacitor plate on the capacitor dielectric layer.

Abstract: Disclosed herein are embodiments of non-planar capacitor. The non-planar capacitor can comprise a plurality of fins above a semiconductor substrate. Each fin can comprise at least an insulator section on the semiconductor substrate and a semiconductor section, which has essentially uniform conductivity, stacked above the insulator section. A gate structure can traverse the center portions of the fins. This gate structure can comprise a conformal dielectric layer and a conductor layer (e.g., a blanket or conformal conductor layer) on the dielectric layer. Such a non-planar capacitor can exhibit a first capacitance, which is optionally tunable, between the conductor layer and the fins and a second capacitance between the conductor layer and the semiconductor substrate. Also disclosed herein are method embodiments, which can be used to form such a non-planar capacitor and which are compatible with current state of the art multi-gate non-planar field effect transistor (MUGFET) processing.

Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor or DRAM cell. In such a device, a high-K zirconia-based layer may be used as the primary dielectric together with a relatively inexpensive metal electrode based on titanium nitride. To prevent corruption of the electrode during device formation, a thin barrier layer can be used seal the electrode prior to the use of a high temperature process and a (high-concentration or dosage) ozone reagent (i.e., to create a high-K zirconia-based layer). In some embodiments, the barrier layer can also be zirconia-based, for example, a thin layer of doped or un-doped amorphous zirconia. Fabrication of a device in this manner facilitates formation of a device with dielectric constant of greater than 40 based on zirconia and titanium nitride, and generally helps produce less costly, increasingly dense DRAM cells and other semiconductor structures.

Abstract: A semiconductor contact structure and method provide contact structures that extend through a dielectric material and provide contact to multiple different subjacent materials including a silicide material and a non-silicide material such as doped silicon. The contact structures includes a lower composite layer formed using a multi-step ionized metal plasma (IMP) deposition operation. A lower IMP film is formed at a high AC bias power followed by the formation of an upper IMP film at a lower AC bias power. The composite layer may be formed of titanium. A further layer is formed as a liner over the composite layer and the liner layer may advantageously be formed using CVD and may be TiN. A conductive plug material such as tungsten or copper fills the contact openings.

Abstract: A method for forming a semiconductor structure includes forming an isolation region in a semiconductor substrate; forming a conductive layer over the isolation region; forming a first dielectric layer over the conductive layer; forming a plurality of conductive vias extending through the first dielectric layer to the conductive layer and electrically contacting the conductive layer; forming a second dielectric layer over the first dielectric layer; and forming a conductive ground plane in the second dielectric layer. Each of the plurality of conductive vias is in electrical contact with the conductive ground plane, and the conductive ground plane includes an opening, wherein the opening is located directly over the conductive layer. At least one interconnect layer may be formed over the second dielectric layer and may include a transmission line which transmits a signal having a frequency of at least 30 gigahertz.

Abstract: A method of manufacturing a semiconductor integrated circuit device having low depletion ratio capacitor comprising: forming hemispherical grains (HSG) on a poly-silicon; doping the hemispherical grained polysilicon in a phosphine gas; and rapid thermal oxidizing the doped hemispherical grained polysilicon at 850° C. for 10 seconds. The method further comprises nitridizing the rapid thermal oxidized hemispherical-grained polysilicon and depositing a alumina film on the silicon nitride layer. A semiconductor integrated circuit device having a low depletion ratio capacitor according to the disclosed manufacturing method is provided.

Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.

Abstract: A thin film transistor array substrate including a substrate, a gate line intersecting a data line to define a pixel region on the substrate, a switching element disposed at an intersection of the gate line and the data line, a plurality of pixel electrodes and a plurality of first common electrodes alternately arranged in the pixel region, a second common electrode overlapping the data line and interposed between a gate insulation film and a protective film, a first storage electrode on the substrate, a second storage electrode overlapping the first storage electrode, and an organic insulation film on the switching element, the second storage electrode, the data line, a gate pad, and a data pad, wherein the second common electrode covers the data line, the protective film, the organic insulation film, and the gate insulation film, and has inclined surfaces connected to the surface of the substrate.

Abstract: Some embodiments include capacitors. The capacitors may include container-shaped storage node structures that have, along a cross-section, a pair of upwardly-extending sidewalls. Individual sidewalls may have a narrower segment over a wider segment. Capacitor dielectric material and capacitor electrode material may be along the narrower and wider segments of the sidewalls. Some embodiments include methods of forming capacitors in which an initial container-shaped storage node structure is formed to have a pair of upwardly-extending sidewalls along a cross-section, with the sidewalls being of thickness that is substantially constant or increasing from a base to a top of the initial structure. The initial structure is then converted into a modified storage node structure by reducing thicknesses of upper segments of the sidewalls while leaving thicknesses of lower segments of the sidewalls substantially unchanged.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer.

Abstract: A variable resistance element capable of increasing stability of a resistance changing operation and reducing a current necessary for changing, to a low resistance state for the first time, the variable resistance element in an initial state immediately after manufacture. The variable resistance element includes: a first electrode (101); a memory cell hole (150) formed above the first electrode (101); a first variable resistance layer (201) covering a bottom of the memory cell hole (150) and an upper surface of the first electrode (101); a second variable resistance layer (202) formed on the first variable resistance layer (201); and a second electrode (102) formed on the memory cell hole (150), in which a thickness of the first variable resistance layer (201) at the bottom of the memory cell hole (150) gradually decreases toward an edge area of the memory cell hole (150) and has a local minimum value around the edge area of the memory cell hole (150).

Abstract: A method of structuring multicrystalline silicon surfaces comprises the provision of a texturing solution, the application of the texturing solution to a surface of a semiconductor substrate to be structured and the heating of the texturing solution to a texturing temperature, wherein the texturing solution comprises at least a portion of phosphoric acid.

Abstract: A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode.

Abstract: A Metal-Insulator-Metal (MIM) capacitor structure and method of fabricating the same in an integrated circuit improve capacitance density in a MIM capacitor structure by utilizing a sidewall spacer extending along a channel defined between a pair of legs that define portions of the MIM capacitor structure. Each of the legs includes top and bottom electrodes and an insulator layer interposed therebetween, as well as a sidewall that faces the channel. The sidewall spacer incorporates a conductive layer and an insulator layer interposed between the conductive layer and the sidewall of one of the legs, and the conductive layer of the sidewall spacer is physically separated from the top electrode of the MIM capacitor structure. In addition, the bottom electrode of a MIM capacitor structure may be ammonia plasma treated prior to deposition of an insulator layer thereover to reduce oxidation of the electrode.

Abstract: This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion.

Abstract: The present invention discloses a ferroelectric register and a method for manufacturing a capacitor of the same. The ferroelectric register is configured to reduce probability of data storage failure due to a weak state capacitor, by connecting a plurality of capacitors in parallel in a ferroelectric capacitor unit for storing data, instead of using a single capacitor, thereby improving storage reliability and stability. In addition, the ferroelectric register obtains a data sensing margin by pumping a cell plate signal into not a power voltage level but a pumping voltage level.

Abstract: A nonvolatile semiconductor memory device includes: a first semiconductor region having first conductivity; a channel formation region in which a channel inversion layer having second conductivity is formed; a second semiconductor region having the second conductivity; a third semiconductor region having the second conductivity; a laminated insulating film formed on the channel formation region; and a control electrode formed on the laminated insulating film. The laminated insulating film includes a first insulating film, a charge storage film, and a second insulating film in order from the channel formation region side. The control electrode extends to above one of the second semiconductor region and the third semiconductor region. The charge storage film present between an extended portion of the control electrode and the second semiconductor region or the third semiconductor region is removed and a portion where the charge storage film is removed is filled with a third insulating film.

Abstract: A METAL-INSULATOR-METAL structured capacitor is formed with polysilicon instead of an oxide film as a sacrificial layer material that defines a storage electrode region. A MPS (Meta-stable Poly Silicon) process is performed to increase the surface area of the sacrificial layer that defines the storage electrode region and also increase the area of the storage electrode formed over sacrificial layer. This process results in increasing the capacity of the capacitor in a stable manner.

Abstract: The present invention provides a method for making an electrode. Firstly, a conducting substrate is provided. Secondly, a plurality of nano-sized structures is formed on the conducting substrate by a nano-imprinting method. Thirdly, a coating is formed on the nano-sized structures. The nano-sized structures are configured for increasing specific surface area of the electrode.

Abstract: A semiconductor device has a semiconductor substrate, and a capacitor which is provided on the upper side of the semiconductor substrate and composed of a lower electrode, an upper electrode and a dielectric film, the dielectric film being placed in between the lower electrode and the upper electrode, the lower electrode including a noble metal film, and a plurality of conductive oxide films formed in an islands arrangement on the noble metal film.

Abstract: In a method of forming a capacitor, a seed stopper and a sacrificial layer is formed on an insulating interlayer having a plug therethrough. An opening is formed through the sacrificial layer and the seed stopper to expose the plug. A seed is formed on an innerwall of the opening. A lower electrode is formed covering the seed on the innerwall of the opening. The sacrificial layer and the seed are removed. A dielectric layer and an upper electrode are sequentially formed on the lower electrode.

Abstract: A method for forming an HSG (hemispherical grain) layer on a storage electrode of a capacitor formed on a substrate is provided. The method includes a step of introducing a source gas into a reacting chamber to deposit a small amount of HSG nuclei on a conductive layer pattern of a capacitor electrode during a step of stabilizing the substrate temperature. After the substrate temperature is stabilized, a larger amount of source gas is introduced into the chamber to form additional HSG nuclei. Thereafter, a step of annealing is performed to form the HSG layer.

Abstract: A method for fabricating a capacitor in a semiconductor device includes forming an insulation layer over a substrate, forming a storage node contact plug passing through the insulation layer and coupled to the substrate, recessing the storage node contact plug to a certain depth to obtain a sloped profile, forming a barrier metal over the surface profile of the recessed storage node contact plug, forming a sacrificial layer over the substrate structure, etching the sacrificial layer to form an opening exposing the barrier metal, forming a bottom electrode over the surface profile of the opening, and removing the etched sacrificial layer.

Abstract: A method of forming a semiconductor device, includes forming a lower electrode including a metal and a nitrogen on a semiconductor substrate, irradiating a reducing gas to a surface of the lower electrode, and irradiating a gas containing silicon to the surface of the lower electrode to form a projection containing silicide by reacting the metal with the silicon in an island shape on the surface of the lower electrode. Then, a capacitor film is formed on the lower electrode and the projection, and an upper electrode is formed on the capacitor film.

Abstract: A method of making a semiconductor device using a semiconductor substrate includes forming a first insulating layer having a first band energy over the semiconductor substrate. A first semiconductor layer having a second band energy is formed on the first insulating layer. The first semiconductor layer is annealed to form a plurality of first charge retainer globules from the first semiconductor layer. A first protective film is formed over each charge retainer globule of the plurality of first charge retainer globules. A second semiconductor layer is formed having a third band energy over the plurality of first charge retainer globules. The second semiconductor layer is annealed to form a plurality of storage globules from the second semiconductor layer over the plurality of first charge retainer globules. A magnitude of the second band energy is between a magnitude of the first band energy and a magnitude of the third band energy.

Abstract: A liquid crystal display array board includes a plurality of gate wiring lines formed on a substrate and a plurality of data wiring lines crossing the plurality of gate wiring lines, a plurality of thin film transistors formed in areas defined by crossings of the gate wiring lines and the data wiring lines, a plurality of storage capacitor first electrodes that run parallel to the gate wiring lines and patterned to have concavo-convex patterns, a plurality of storage capacitor second electrodes integrated with the drain electrodes of the thin film transistors and formed on the storage capacitor first electrodes, and a plurality of pixel electrodes electrically connected to the drain electrodes.

Abstract: A semiconductor device according to an embodiment of the present invention includes: a transistor including, a gate insulator formed of an insulating layer deposited on a substrate, and a gate electrode formed of an electrode layer deposited on the insulating layer; a capacitor including, a first capacitor electrode formed of the electrode layer, a first capacitor insulator formed on the first capacitor electrode, a second capacitor electrode formed on the first capacitor insulator, a second capacitor insulator formed on the second capacitor electrode, and a third capacitor electrode formed on the second capacitor insulator; and line patterns which are in contact with a contact plug for the transistor, a contact plug for the first capacitor electrode, a contact plug for the second capacitor electrode, and the third capacitor electrode.