Including Selectively Removing Material To Undercut And Expose Storage Node Layer Patents (Class 438/397)
  • Patent number: 9805934
    Abstract: In a method for manufacturing a semiconductor device, a substrate is provided, and a dielectric layer is formed to cover the substrate. A recess portion is formed in the dielectric layer. A spacer is formed on a side surface of the recess portion. The dielectric layer is etched through the recess portion to form a hole in the dielectric layer to expose a portion of the substrate.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: October 31, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Chung Jen, Yu-Hua Yen
  • Patent number: 9123891
    Abstract: A variable-resistance material memory (VRMM) device includes a container conductor disposed over an epitaxial semiconductive prominence that is coupled to a VRMM. A VRMM device may also include a conductive plug in a recess that is coupled to a VRMM. A VRMM array may also include a conductive plug in a surrounding recess that is coupled to a VRMM. Apparatuses include the VRMM with one of the diode constructions.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: September 1, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Michael P. Violette
  • Patent number: 9076757
    Abstract: A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes, an elevationally inner insulative retaining material received laterally about the capacitor electrodes, an elevationally outer insulative retaining material received laterally about the capacitor electrodes, a first material received laterally about the capacitor electrodes elevationally inward of the inner insulative retaining material, and a second material received laterally about the capacitor electrodes elevationally between the inner and outer insulative retaining materials. Openings are anisotropically etched to extend through the outer insulative retaining material and the second material. After the anisotropic etching, remaining of the second material is isotropically etched through the openings from being received laterally about the capacitor electrodes between the inner and outer insulative retaining materials.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: July 7, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Che-Chi Lee
  • Patent number: 9060144
    Abstract: An image sensor comprises an image sensing substrate that in turns includes an image sensing device, a first sensor pixel, a second sensor pixel, and a divider. The divider is between the first sensor pixel and the second sensor pixel.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: June 16, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yi-Sheng Liu, Yun-Wei Cheng, Volume Chien, Chi-Cherng Jeng, Hsin-Chi Chen
  • Publication number: 20150126016
    Abstract: A method of forming capacitors includes forming support material over a substrate. A first capacitor electrode is formed within individual openings in the support material. A first etching is conducted only partially into the support material using a liquid etching fluid to expose an elevationally outer portion of sidewalls of individual of the first capacitor electrodes. A second etching is conducted into the support material using a dry etching fluid to expose an elevationally inner portion of the sidewalls of the individual first capacitor electrodes. A capacitor dielectric is formed over the outer and inner portions of the sidewalls of the first capacitor electrodes. A second capacitor electrode is formed over the capacitor dielectric.
    Type: Application
    Filed: January 14, 2015
    Publication date: May 7, 2015
    Inventors: Joseph Neil Greeley, Prashant Raghu, Niraj B. Rana
  • Patent number: 8975135
    Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. A silicide-block film comprised of a layer of silicon dioxide underlying a top layer of silicon nitride blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit, such as polysilicon-to-metal capacitors, are silicide-clad. Following silicidation, a capacitor dielectric is deposited over the remaining polysilicon structures, followed by formation of an upper metal plate.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: March 10, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Kaiping Liu, Amitava Chatterjee, Imran Mahmood Khan
  • Patent number: 8957403
    Abstract: Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select devices may comprise, for example, a metal-insulator-insulator-metal (MIIM) diode. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: February 17, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Bhaskar Srinivasan, Gurtej S. Sandhu
  • Patent number: 8951832
    Abstract: Variable-resistance memory material cells are contacted by vertical bottom spacer electrodes. Variable-resistance material memory spacer cells are contacted along the edge by electrodes. Processes include the formation of the bottom spacer electrodes as well as the variable-resistance material memory spacer cells. Devices include the variable-resistance memory cells.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: February 10, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 8946047
    Abstract: A method for fabricating a capacitor includes: forming a storage node contact plug over a substrate; forming an insulation layer having an opening exposing a surface of the storage node contact plug over the storage contact plug; forming a conductive layer for a storage node over the insulation layer and the exposed surface of the storage node contact plug through two steps performed at different temperatures; performing an isolation process to isolate parts of the conductive layer; and sequentially forming a dielectric layer and a plate electrode over the isolated conductive layer.
    Type: Grant
    Filed: June 4, 2010
    Date of Patent: February 3, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jin-Hyock Kim, Seung-Jin Yeom, Ki-Seon Park, Han-Sang Song, Deok-Sin Kil, Jae-Sung Roh
  • Patent number: 8912629
    Abstract: A semiconductor device includes a substrate and a plurality of storage nodes on the substrate and extending in a vertical direction relative to the substrate. A lower support pattern is in contact with the storage nodes between a bottom and a top of the storage nodes, the lower support pattern spaced apart from the substrate in the vertical direction, and the lower support pattern having a first maximum thickness in the vertical direction. An upper support pattern is in contact with the storage nodes above the lower support pattern relative to the substrate, the upper support pattern spaced apart from the lower support pattern in the vertical direction, and the lower support pattern having a second maximum thickness in the vertical direction that is greater than the first maximum thickness of the lower support pattern.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: December 16, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: JungWoo Seo
  • Patent number: 8884288
    Abstract: The present invention provides a semiconductor structure for testing MIM capacitors. The semiconductor structure comprises: a first metal layer comprising at least a first circuit area and a second circuit area; a second metal layer located below the first metal layer with a first dielectric layer lying therebetween and connected with the second circuit area; a top plate located within the first dielectric layer closer to the first metal layer and connected with the first circuit area; a bottom plate located within the first dielectric layer closer to the second metal layer and separated from the top plate with an insulation layer therebetween and connected with the second circuit area. The second metal layer is connected with the substrate through a first electric pathway so as to form a second electric pathway from the top plate to the substrate when an electric leakage region exists in the insulation layer.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 11, 2014
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Qiang Li, Zhuanlan Sun, Changhui Yang
  • Patent number: 8883622
    Abstract: A method of fabricating a semiconductor memory device includes preparing a semiconductor substrate which is divided into a cell array region and a core and peripheral region adjacent to the cell array region. Signal lines may be formed in a lower layer in a cell region. An insulation layer may be formed on the lower layer. Signal lines connected to cell region signal lines may be formed on an insulation layer of the peripheral region. A capping layer may be formed on the insulation layer and the core and peripheral signal lines. The capping layer may be etched to expose the lower layer of the cell array region and an etch stop may be formed on the lower layer and the core and peripheral region.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-mo Park, Min-wk Hwang, Hyun-chul Kim
  • Publication number: 20140319658
    Abstract: Charge pump capacitor assemblies and methods of manufacturing the same. One charge pump capacitor assembly includes a charge pump capacitor and a silicon substrate. The charge pump capacitor includes: a silicon-based charge pump capacitor oxide layer, a first terminal on a first side of the silicon-based charge pump layer, a second terminal on a second side of the silicon-based charge pump capacitor oxide layer opposite the first side, and a field oxide layer mounted adjacent the second terminal. The charge pump capacitor is coupled to the silicon substrate. The silicon substrate is etched to reduce contact between the silicon substrate and the field oxide layer.
    Type: Application
    Filed: September 27, 2013
    Publication date: October 30, 2014
    Applicant: Robert Bosch GmbH
    Inventor: John M. Muza
  • Publication number: 20140319653
    Abstract: An integrated circuit includes a substrate. A fixed main capacitor electrode is disposed in a metal layer overlying the substrate. A second main capacitor electrode is disposed in a metal layer and spaced from the fixed main capacitor electrode. A movable capacitor electrode is disposed adjacent the fixed main capacitor electrode. The movable capacitor electrode is switchable between a first configuration in which the movable capacitor electrode and fixed main capacitor electrode are mutually spaced out in such a manner as to form an auxiliary capacitor electrically connected to the main capacitor. In a second configuration, the movable capacitor electrode and the fixed main capacitor electrode are in electrical contact in such a manner as to give a second capacitive value.
    Type: Application
    Filed: April 29, 2014
    Publication date: October 30, 2014
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Pascal Fornara, Christian Rivero
  • Patent number: 8871588
    Abstract: A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, H. Montgomery Manning
  • Patent number: 8865545
    Abstract: A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line hole disposed over the top portion of the semiconductor substrate; an oxide film disposed at sidewalls of the bit line hole; and a bit line conductive layer buried in the bit line hole including the oxide film. A bit line spacer is formed with an oxide film, thereby reducing a parasitic capacitance. A storage node contact is formed to have a line type, thereby securing a patterning margin. A storage node contact plug is formed with polysilicon having a different concentration, thereby reducing leakage current.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: October 21, 2014
    Assignee: SK Hynix Inc.
    Inventor: Se In Kwon
  • Patent number: 8853050
    Abstract: Some embodiments include methods of making stud-type capacitors utilizing carbon-containing support material. Openings may be formed through the carbon-containing support material to electrical nodes, and subsequently conductive material may be grown within the openings. The carbon-containing support material may then be removed, and the conductive material utilized as stud-type storage nodes of stud-type capacitors. The stud-type capacitors may be incorporated into DRAM, and the DRAM may be utilized in electronic systems.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: October 7, 2014
    Assignee: Micron Technology
    Inventors: Mark Kiehlbauch, Kevin R. Shea
  • Publication number: 20140256112
    Abstract: Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers.
    Type: Application
    Filed: February 28, 2014
    Publication date: September 11, 2014
    Inventors: Ki-Yeon Park, Jae-Hyoung Choi, Vladimir Urazaev, Jin-Ha Jeong
  • Patent number: 8809929
    Abstract: Memory devices comprise a lower layer that extends across a cell array region and across a peripheral region and that includes a flat outer surface from the cell array region to the peripheral region. A signal transfer conductor layer extends in the cell array region beneath the flat outer surface of the lower layer and extends in the peripheral region above the flat outer surface of the lower layer. An insulating layer is provided on the lower layer, including a flat outer surface from the cell array region to the peripheral region. A flat stopper layer is provided on the flat outer surface of the insulating layer and extending across the cell array region and the peripheral region. Related methods are also provided.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: August 19, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wonmo Park, Hyunchul Kim, Hyodong Ban, Hyunju Lee
  • Patent number: 8809160
    Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor or DRAM cell. In such a device, a high-K zirconia-based layer may be used as the primary dielectric together with a relatively inexpensive metal electrode based on titanium nitride. To prevent corruption of the electrode during device formation, a thin barrier layer can be used seal the electrode prior to the use of a high temperature process and a (high-concentration or dosage) ozone reagent (i.e., to create a high-K zirconia-based layer). In some embodiments, the barrier layer can also be zirconia-based, for example, a thin layer of doped or un-doped amorphous zirconia. Fabrication of a device in this manner facilitates formation of a device with dielectric constant of greater than 40 based on zirconia and titanium nitride, and generally helps produce less costly, increasingly dense DRAM cells and other semiconductor structures.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: August 19, 2014
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Hanhong Chen, Edward Haywood, Pragati Kumar, Sandra G Malhotra, Xiangxin Rui
  • Patent number: 8790975
    Abstract: When forming capacitive structures in a metallization system, such as in a dynamic RAM area, placeholder metal regions may be formed together with “regular” metal features, thereby achieving a very efficient overall process flow. At a certain manufacturing stage, the metal of the placeholder metal region may be removed on the basis of a wet chemical etch recipe followed by the deposition of the electrode materials and the dielectric materials for the capacitive structure without unduly affecting other portions of the metallization system. In this manner, very high capacitance values may be realized on the basis of a very efficient overall manufacturing flow.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: July 29, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Baars, Till Schloesser, Vivien Schroeder
  • Publication number: 20140197519
    Abstract: In a particular embodiment, a method of forming a metal-insulator-metal (MIM) capacitor includes removing, using a lithographic mask, a first portion of an optical planarization layer to expose a region in which the MIM capacitor is to be formed. A second portion of an insulating layer is formed on a first conductive layer that is formed on a plurality of trench surfaces within the region. The method further includes removing at least a third portion of the insulating layer according to a lift-off technique.
    Type: Application
    Filed: January 17, 2013
    Publication date: July 17, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Jihong Choi, John J. Zhu, PR Chidambaram, Bin Yang, Lixin Ge
  • Patent number: 8778755
    Abstract: A method for fabricating a metal-insulator-metal capacitor (MIMCap) is disclosed. A first metal layer is provided on top of an oxide layer. A nitride layer is then deposited on the first metal layer. The nitride layer and the first metal layer are etched to form a MIMCap metal layer. The gaps among the MIMCap metal layer are filled with a plasma oxide, and the excess plasma oxide is polished using the nitride layer a polish stop. After removing the nitride layer, a dielectric layer and a second metal layer are deposited on the MIMCap metal layer. Finally, the dielectric layer and the second metal layer are etched to form a set of MIMCap structures.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: July 15, 2014
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Jason F. Ross, Chi-Hua Yang, Thomas J. McIntyre
  • Patent number: 8753954
    Abstract: A semiconductor device containing a cylindrical shaped capacitor and a method for manufacturing the same is presented. The semiconductor device includes a plurality of storage nodes and a support pattern. The plurality of storage nodes is formed over a semiconductor substrate. The support pattern is fixed to adjacent storage nodes in which the support pattern has a flowable insulation layer buried within the support pattern. The buried flowable insulation layer direct contacts adjacent storage nodes.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: June 17, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung Min Park
  • Publication number: 20140162430
    Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.
    Type: Application
    Filed: February 13, 2014
    Publication date: June 12, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Kevin R. Shea, Thomas M. Graettinger
  • Patent number: 8679935
    Abstract: The present disclosure describes methods of fabricating a semiconductor device. An exemplary method includes forming a metal pattern on a substrate and etching the metal pattern using an etchant including at least an alkaline solution and an oxidant to form a metal electrode, where at least a portion of the surface of the metal electrode is uneven.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: March 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mongsup Lee, Inseak Hwang, Byoung-Yong Gwak, Sukhun Choi, Sang-Jun Lee
  • Patent number: 8673730
    Abstract: A method of manufacturing a charging capacity structure includes steps of: forming a first oxide layer, a support layer and a second oxide layer on a substrate in sequence; forming a plurality of etching holes on the surface of the second oxide layer in a matrix to run through the substrate that are spaced from each other at a selected distance; forming a plurality of pillar layers in the etching holes; removing the second oxide layer by etching; forming an etching protection layer on the surfaces of the support layer and pillar tubes that is formed at a thickness one half of the spaced distance between the etching holes such that the pillar tubes at diagonal locations form a self-calibration hole; and finally removing the first oxide layer from the self-calibration hole by etching. Through the self-calibration hole, the invention needn't to provide extra photoresists to form holes.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: March 18, 2014
    Assignee: Rexchip Electronics Corporation
    Inventors: Pei-Chun Hung, Li-Hsun Chen, Chien-hua Tsai, Masahiko Ohuchi, Sheng-chang Liang
  • Patent number: 8652926
    Abstract: A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support material contains polysilicon. The polysilicon-containing support material is dry isotropically etched selectively relative to the TiN-containing first capacitor electrodes using a sulfur and fluorine-containing etching chemistry. A capacitor dielectric is formed over sidewalls of the first capacitor electrodes and a second capacitor electrode is formed over the capacitor dielectric. Additional methods are disclosed.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: February 18, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Gurpreet Lugani, Kevin J. Torek
  • Patent number: 8637364
    Abstract: An amorphous carbon film and an interlayer insulation film are formed in a memory cell region and a peripheral circuit region, respectively. An insulating film is formed on the amorphous carbon film and the interlayer insulation film. A portion of the insulating film that corresponds to capacitors on the amorphous carbon film is removed so that lower electrodes of the capacitors are supported from opposite sides of the lower electrodes. An insulating film pattern continuously extends from the memory cell region to the peripheral circuit region wholly covered with the insulating film pattern. Subsequently, the amorphous carbon film is removed to leave the capacitors supported by the insulating film pattern on both sides of the lower electrodes.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: January 28, 2014
    Inventor: Yasuhiko Ueda
  • Patent number: 8609505
    Abstract: A capacitor structure includes a semiconductor substrate; a first capacitor plate positioned on the semiconductor substrate, the first capacitor plate including a polysilicon structure having a surrounding spacer; a silicide layer formed in a first portion of an upper surface of the first capacitor plate; a capacitor dielectric layer formed over a second portion of the upper surface of the first capacitor plate and extending laterally beyond the spacer to contact the semiconductor substrate; a contact in an interlayer dielectric (ILD), the contact contacting the silicide layer and a first metal layer over the ILD; and a second capacitor plate over the capacitor dielectric layer, wherein a metal-insulator-metal (MIM) capacitor is formed by the first capacitor plate, the capacitor dielectric layer and the second capacitor plate and a metal-insulator-semiconductor (MIS) capacitor is formed by the second capacitor plate, the capacitor dielectric layer and the semiconductor substrate.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: December 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Robert M. Rassel, Anthony K. Stamper
  • Patent number: 8580648
    Abstract: A capacitor includes an object or a substrate including an insulation layer having an opening, an electrode structure having conductive patterns, a dielectric layer and an upper electrode. The electrode structure may have a first conductive pattern including metal and a second conductive pattern including metal oxide generated from the first conductive pattern. The first conductive pattern may fill the opening and may protrude over the insulation layer. The second conductive pattern may extend from the first conductive pattern. The electrode structure may additionally include a third conductive pattern disposed on the second conductive pattern. The capacitor including the electrode structure may ensure improved structural stability and electrical characteristics.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: November 12, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-Hun Choi, Kyung-Hyun Kim, Chang-Sup Mun, Sung-Jun Kim, Jin-I Lee
  • Patent number: 8569817
    Abstract: A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line hole disposed over the top portion of the semiconductor substrate; an oxide film disposed at sidewalls of the bit line hole; and a bit line conductive layer buried in the bit line hole including the oxide film. A bit line spacer is formed with an oxide film, thereby reducing a parasitic capacitance. A storage node contact is formed to have a line type, thereby securing a patterning margin. A storage node contact plug is formed with polysilicon having a different concentration, thereby reducing leakage current.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: October 29, 2013
    Assignee: Hynix Semiconductor Inc
    Inventor: Se In Kwon
  • Patent number: 8558294
    Abstract: A semiconductor device includes a semiconductor substrate formed with an active element, an oxidation resistant film formed over the semiconductor substrate so as to cover the active element, a ferroelectric capacitor formed over the oxidation resistance film, the ferroelectric capacitor having a construction of consecutively stacking a lower electrode, a ferroelectric film and an upper electrode, and an interlayer insulation film formed over the oxidation resistance film so as to cover the ferroelectric capacitor, wherein there are formed, in the interlayer insulation film, a first via-plug in a first contact hole exposing the first electrode and a second via-plug in a second contact hole exposing the lower electrode, and wherein there is formed another conductive plug in the interlayer insulation film in an opening exposing the oxidation resistant film.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: October 15, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoya Sashida
  • Patent number: 8551857
    Abstract: The technique for manufacturing a high-capacitance and high-accuracy MIM electrostatic capacitor by a small number of steps is provided. After a lower electrode of the electrostatic capacitor and second wiring are formed at the same time on a first interlayer insulating film, an opening part is formed in a second interlayer insulating film deposited on the first interlayer insulating film. Next, a capacitance insulating film, a second metal film and a protective metal film are sequentially deposited on the second interlayer insulating film including the interior of the opening part, and the protective metal film, the second metal film and the capacitance insulating film on the second interlayer insulating film are polished and removed by a CMP method, thereby causing the capacitance insulating film, an upper electrode made of the second metal film and the protective metal film to remain in the opening part.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: October 8, 2013
    Assignees: Hitachi, Ltd., Asahi Kasei Microdevices Corporation
    Inventors: Yuji Imamura, Tsuyoshi Fujiwara, Toyohiko Kuno
  • Patent number: 8530322
    Abstract: This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor or DRAM cell. In such a device, a high-K zirconia-based layer may be used as the primary dielectric together with a relatively inexpensive metal electrode based on titanium nitride. To prevent corruption of the electrode during device formation, a thin barrier layer can be used seal the electrode prior to the use of a high temperature process and a (high-concentration or dosage) ozone reagent (i.e., to create a high-K zirconia-based layer). In some embodiments, the barrier layer can also be zirconia-based, for example, a thin layer of doped or un-doped amorphous zirconia. Fabrication of a device in this manner facilitates formation of a device with dielectric constant of greater than 40 based on zirconia and titanium nitride, and generally helps produce less costly, increasingly dense DRAM cells and other semiconductor structures.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: September 10, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Hanhong Chen, Edward Haywood, Pragati Kumar, Sandra Malhotra, Xiangxin Rui
  • Patent number: 8530324
    Abstract: Memory devices comprise a microelectronic substrate including a cell array region and a peripheral region adjacent the cell array region, the cell array region including therein an array of memory cells and the peripheral region including therein peripheral circuits for the array of memory cells, the microelectronic substrate including a lower layer that extends across the cell array region and across the peripheral region and that includes a flat outer surface from the cell array region to the peripheral region. A signal transfer conductor layer extends in the cell array region beneath the flat outer surface of the lower layer and extends in the peripheral region above the flat outer surface of the lower layer. An insulating layer is provided on the lower layer, the insulating layer extending across the cell array region and the peripheral region and also including a flat outer surface from the cell array region to the peripheral region.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: September 10, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wonmo Park, Hyunchul Kim, Hyodong Ban, Hyunju Lee
  • Patent number: 8518773
    Abstract: A method of fabricating a semiconductor capacitor includes forming a cavity in a first dielectric layer. Then, a nitride stack comprising a slow-etch nitride layer disposed between two fast-etch nitride layers is deposited in the cavity. Next, a portion of the nitride stack is etched within the cavity. Continuing, a metal plug is deposited in the cavity. The fast-etch nitride layers of the nitride stack are removed while preserving the slow-etch nitride layer of the nitride stack. A first metal layer is deposited over the slow-etch nitride layer, a second dielectric layer is deposited over the first metal layer, and a second metal layer is deposited over the second dielectric layer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 27, 2013
    Assignee: International Business Machines Corporation
    Inventors: David Vaclav Horak, Shom Ponoth, Hosadurga Shobha, Chih-Chao Yang
  • Patent number: 8497182
    Abstract: A memory device includes an array of electrodes that includes thin film plates of electrode material. Multilayer strips are arranged as bit lines over respective columns in the array of electrodes, including a layer of memory material and a layer of top electrode material. The multilayer strips have a primary body and a protrusion having a width less than that of the primary body and is self-aligned with contact surfaces on the thin film plates. Memory material in the protrusion contacts surfaces on the distal ends of thin film plates of electrodes in the corresponding column in the array. The device can be made using a damascene process in self-aligned forms over the contact surfaces.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: July 30, 2013
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Patent number: 8486801
    Abstract: A fabricating method of a DRAM structure includes providing a substrate comprising a memory array region and a peripheral region. A buried gate transistor is disposed within the memory array region, and a planar gate transistor is disposed within the peripheral region. Furthermore, an interlayer dielectric layer covers the memory array region, the buried gate transistor and the planar gate transistor. Then, a capping layer of the planar gate transistor and part of the interlayer dielectric layer are removed simultaneously so that a first contact hole, a second contact hole and a third contact hole are formed in the interlayer dielectric layer. A drain doping region of the buried gate transistor is exposed through the first contact hole, a doping region of the planar gate transistor is exposed through the second contact hole, and a gate electrode of the planar gate transistor is exposed through the third contact hole.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: July 16, 2013
    Assignee: Inotera Memories, Inc.
    Inventors: Tzung-Han Lee, Chung-Lin Huang, Ron Fu Chu
  • Patent number: 8476688
    Abstract: A semiconductor device that prevents the leaning of storage node when forming a capacitor having high capacitance includes a plurality of cylinder-shaped storage nodes formed over a semiconductor substrate; and support patterns formed to fix the storage nodes in the form of an ‘L’ or a ‘+’ when viewed from the top. This semiconductor device having support patterns in the form of an ‘L’ or a ‘+’ reduces stress on the storage nodes when subsequently forming a dielectric layer and plate nodes that prevents the capacitors from leaking.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: July 2, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ho Jin Cho, Cheol Hwan Park, Jae Wook Seo, Jong Kuk Kim
  • Patent number: 8461012
    Abstract: A method for forming a semiconductor structure includes forming an isolation region in a semiconductor substrate; forming a conductive layer over the isolation region; forming a first dielectric layer over the conductive layer; forming a plurality of conductive vias extending through the first dielectric layer to the conductive layer and electrically contacting the conductive layer; forming a second dielectric layer over the first dielectric layer; and forming a conductive ground plane in the second dielectric layer. Each of the plurality of conductive vias is in electrical contact with the conductive ground plane, and the conductive ground plane includes an opening, wherein the opening is located directly over the conductive layer. At least one interconnect layer may be formed over the second dielectric layer and may include a transmission line which transmits a signal having a frequency of at least 30 gigahertz.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: June 11, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Vishal P. Trivedi
  • Patent number: 8389374
    Abstract: The present invention is a method for producing a capacitor. The method includes applying a dielectric substance (ex.—silicon nitride) to a first gold seed layer, the first gold seed layer being formed on a wafer. A second gold seed layer is formed upon the dielectric substance and first gold seed layer. Gold is electroplated into a photoresist to form a first set of 3-D capacitor elements on the second gold seed layer. A first copper layer is electroplated onto the second gold seed layer. Gold is electroplated into a photoresist to form a second set of 3-D capacitor elements, the second set of 3-D elements being formed at least partially within the first copper layer and being connected to the first set of 3-D elements. A second copper layer is electroplated onto the first copper layer. Then, both copper layers are removed to provide (ex.—form) the capacitor.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: March 5, 2013
    Assignee: Rockwell Collins, Inc.
    Inventors: Nathan P. Lower, Mark M. Mulbrook, Robert L. Palandech
  • Patent number: 8389375
    Abstract: In a first aspect, a method of forming a memory cell is provided, the method including: (1) forming a pillar above a substrate, the pillar comprising a steering element and a metal hardmask layer; (2) selectively removing the metal hardmask layer to create a void; and (3) forming a carbon-based switching material within the void. Numerous other aspects are provided.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: March 5, 2013
    Assignee: SanDisk 3D LLC
    Inventor: Steven Maxwell
  • Patent number: 8343845
    Abstract: A capacitor structure includes a plurality of lower electrodes on a substrate, the lower electrodes having planar top surfaces and being arranged in a first direction to define a lower electrode column, a plurality of lower electrode columns being arranged in a second direction perpendicular to the first direction to define a lower electrode matrix, a plurality of supports on upper sidewalls of at least two adjacent lower electrodes, a dielectric layer on the lower electrodes and the supports, and an upper electrode on the dielectric layer.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: January 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Il Kim, Dae-Ik Kim, Yun-Sung Lee, Nam-Jung Kang
  • Publication number: 20120322225
    Abstract: A method is disclosed that includes forming a conductive logic contact in a logic area of a semiconductor device, forming a bit line contact and a capacitor contact in a memory array of the semiconductor device, and performing at least one first common process to form a first metallization layer comprising a first conductive line in the logic area that is conductively coupled to the conductive logic contact and a bit line in the memory array that is conductively coupled to the bit line contact. The method further includes performing at least one second common process to form a second metallization layer comprising a first conductive structure conductively coupled to the first conductive line in the logic area and a second conductive structure in the memory array that that is conductively coupled to the capacitor contact.
    Type: Application
    Filed: June 20, 2011
    Publication date: December 20, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Till Schloesser, Peter Baars
  • Patent number: 8324069
    Abstract: A method of fabricating a high-performance capacitor that may be incorporated into a standard CMOS fabrication process suitable for submicron devices is described. The parameters used in the standard CMOS process may be maintained, particularly for the definition and etch of the lower electrode layer. To reduce variation in critical dimension width, an Anti-Reflective Layer (ARL) is used, such as a Plasma Enhanced chemical vapor deposition Anti-Reflective Layer (PEARL) or other Anti-Reflective Coatings (ARCS), such as a conductive film like TiN. This ARL formation occurs after the capacitor specific process steps, but prior to the masking used for defining the lower electrodes. A Rapid Thermal Oxidation (RTO) is performed subsequent to removing the unwanted capacitor dielectric layer from the transistor poly outside of the capacitor regions, but prior to the PEARL deposition.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: December 4, 2012
    Assignee: IXYS CH GmbH
    Inventors: Timothy K. Carns, John L. Horvath, Lee J. DeBruler, Michael J. Westphal
  • Patent number: 8324049
    Abstract: A semiconductor device and a method for fabricating a semiconductor device are provided. The method for fabricating a semiconductor device includes forming an isolation layer over a semiconductor substrate defining first and second regions, etching the isolation layer at an edge of the first region to form a guard ring pattern, forming a buried guard ring filling the guard ring pattern, selectively etching the isolation layer of the first region to form a plurality of patterns, forming a plurality of conductive patterns in the respective patterns, and completely removing the isolation layer of the first region through a dip-out process.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: December 4, 2012
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Jin-A Kim, Seok-Ho Jie
  • Patent number: 8278156
    Abstract: Systems and methods of semiconductor device fabrication and layout generation are disclosed. An exemplary method includes processes of depositing a layer of a first material and patterning the layer to form an initial pattern, wherein the initial pattern defines critical features of the layout elements using a single exposure; depositing spacer material over the first pattern on the substrate and etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of the first pattern; removing the initial pattern from the substrate while leaving the spacer material in a spacer pattern; filling the spacer pattern with final material; and trimming the tilled pattern to remove portions of the final material beyond dimensions of the layout elements.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: October 2, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventor: Christophe Pierrat
  • Patent number: 8268695
    Abstract: Some embodiments include methods of making stud-type capacitors utilizing carbon-containing support material. Openings may be formed through the carbon-containing support material to electrical nodes, and subsequently conductive material may be grown within the openings. The carbon-containing support material may then be removed, and the conductive material utilized as stud-type storage nodes of stud-type capacitors. The stud-type capacitors may be incorporated into DRAM, and the DRAM may be utilized in electronic systems.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: September 18, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Mark Kiehlbauch, Kevin R. Shea
  • Patent number: 8263457
    Abstract: A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive metal nitride-comprising material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Inner sidewalls of the conductive material within the trench are annealed in a nitrogen-comprising atmosphere. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area. The conductive material within the array area is incorporated into a plurality of capacitors.
    Type: Grant
    Filed: October 10, 2011
    Date of Patent: September 11, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Vishwanath Bhat, Kevin R. Shea