Abstract: Provided are semiconductor devices and methods of fabricating the same. The methods may include forming a molding layer on a semiconductor substrate. A storage electrode passing through the molding layer is formed. A part of the storage electrode is exposed by partially etching the molding layer. A sacrificial oxide layer is formed by oxidizing the exposed part of the storage electrode. The partially-etched molding layer and the sacrificial oxide layer are removed. A capacitor dielectric layer is formed on the substrate of which the molding layer and the sacrificial oxide layer are removed. A plate electrode is formed on the capacitor dielectric layers.

Abstract: To provide a transistor with stable electric characteristics, provide a transistor having a small current in a non-conductive state, provide a transistor having a large current in a conductive state, provide a semiconductor device including the transistor, or provide a durable semiconductor device, a semiconductor device includes a first insulator containing excess oxygen, a semiconductor over the first insulator, a second insulator over the semiconductor, and a conductor having a region overlapping with the semiconductor with the second insulator provided therebetween. A region containing boron or phosphorus is located between the first insulator and the semiconductor.

Abstract: A charge storage trench structure is provided underneath a body region of a field effect transistor to store electrical charges in a region spaced from the p-n junctions between the body region and the source and drain regions of a field effect transistor. The charge storage trench structure can be embedded in a dielectric material layer, and a semiconductor fin can be formed by attaching a semiconductor material layer to the top surface of the charge storage trench structure and by patterning the semiconductor material layer. The field effect transistor is formed such that the charge storage trench structure contacts a bottom surface of the body region of the field effect transistor, while not contacting any of the source and drain regions. The electrical charges stored in the charge storage trench structure are physically spaced from the p-n junctions, and are less prone to leakage through the p-n junctions.

Abstract: A method for fabricating a magnetic tunnel junction (MTJ) is disclosed. The process involves annealing a stack that includes a tunnel barrier layer and cooling the stack under vacuum immediately after annealing. At least one overlayer is deposited on the tunnel barrier layer to form the MTJ.

Abstract: According to one embodiment, a liquid crystal optical element includes: a pair of first and second substrates; a liquid crystal layer provided between the first and second substrates; first electrodes provided on the first substrate on the liquid crystal layer side and arranged along a first direction; second electrodes provided on the second substrate on the liquid crystal layer side and arranged along a second direction; and a driving unit configured to apply a voltage between the first electrodes and the second electrodes. The first electrodes are divided into electrode regions arranged along a third direction. The first electrodes included in each of the electrode regions are electrically connected to an extension line.

Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.

Abstract: A STT-MRAM comprises a method to form magnetic random access memory (MRAM) element array having ultra small dimensions using double photo exposures and etch of their hard masks. The memory cells are located at the cross section of two ultra-narrow photo-resist lines suspended between two large photo-resist bases. Array of MRAM cells with small dimension is formed by a third magnetic etch.

Abstract: A magnetization reversal device includes a ferromagnetic 12 body which is provided in an interconnection of a non-ferromagnetic dot 11 so that a part or a whole of the ferromagnetic dot is three-dimensionally buried in the interconnection of said non-ferromagnetic dot, and a spin injection source 13 which generates a spin-polarized pure spin current without a flow of charges, and which is provided in the interconnection of the non-ferromagnetic dot 11 to be in contact therewith so that the interconnection of the non-ferromagnetic dot serves as a common electrode, and the pure spin current flows into the ferromagnetic dot 2 through the interconnection of the non-magnetic body by the spin injection source 13 due to a diffusion current, to thereby reverse magnetization of the ferromagnetic dot 12.

Abstract: A method of minimizing imprint in a ferroelectric capacitor uses a gradually attenuated AC field to electrically depolarize the ferroelectric capacitor before being packaged. The AC field is linearly attenuated, and generated using a series of voltage pulses, down to a minimum allowed voltage. A final pulse is a positive voltage to minimize hydrogen degradation during packaging. Thermal depoling can also be used.

Abstract: Magnetic memory devices include a magnetoresistive cell including a free layer having a variable magnetization direction and a pinned layer having a fixed magnetization direction, a bit line on the magnetoresistive cell and including a spin Hall effect material layer exhibiting a spin Hall effect and contacting the free layer; and a lower electrode under the magnetoresistive cell. A voltage is applied between the bit line and the lower electrode so that current passes through the magnetoresistive cell.

Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a non-planar portion, a resistive material layer conformally covering the non-planar portion of the bottom electrode; and, a top electrode on the resistive material layer. The via portion of the bottom electrode is embedded in a first RRAM stop layer. The non-planar portion of the bottom electrode has an apex and is centered above the via portion.

Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.

Abstract: A magnetic memory according to an embodiment includes at least one MTJ element, the MTJ element including: a magnetic multilayer structure including a first magnetic layer in which a direction of magnetization is fixed, a second magnetic layer in which a direction of magnetization is changeable, and a tunnel barrier layer located between the first and second magnetic layers; a first electrode provided on a first surface of the magnetic multilayer structure; a second electrode provided on a second surface of the magnetic multilayer structure; an insulating film provided on a side surface of the magnetic multilayer structure; and a control electrode provided on the side surface of the magnetic multilayer structure with the insulating film located therebetween, a voltage being applied to the control electrode in a read operation, which increases an energy barrier for changing the magnetization of the second magnetic layer.

Abstract: The present disclosure provides one embodiment of a method to form an interconnect structure. The method includes forming a first dielectric material layer on a substrate; patterning the first dielectric material layer to form a plurality of vias therein; forming a metal layer on the first dielectric layer and the substrate, wherein the metal layer fills in the plurality of vias; and etching the metal layer such that portions of the metal layer above the first dielectric material layer are patterned to form a plurality of metal lines, aligned with plurality of vias, respectively.

Abstract: Multi-bit ferroelectric memory devices and methods of forming the same are provided. One example method of forming a multi-bit ferroelectric memory device can include forming a first ferroelectric material on a first side of a via, removing a material to expose a second side of the via, and forming second ferroelectric material on the second side of the via at a different thickness compared to the first side of the via.

Abstract: The mechanisms for forming an inductor structure are provided. The inductor structure includes a substrate and a first dielectric layer formed over the substrate. The inductor structure also includes a first metal layer formed in the first dielectric layer and a magnetic layer formed over the first dielectric layer, and the magnetic layer has edges more than four in a cross section view.

Abstract: A perpendicular magnetic tunnel junction (MTJ) apparatus includes a tunnel magnetoresistance (TMR) enhancement buffer layer deposited between the tunnel barrier layer and the reference layers An amorphous alloy spacer is deposited between the TMR enhancement buffer layer and the reference layers to enhance TMR The amorphous alloy spacer blocks template effects of face centered cubic (fcc) oriented pinned layers and provides strong coupling between the pinned layers and the TMR enhancement buffer layer to ensure full perpendicular magnetization.

Abstract: A magnetic field sensor for sensing an external magnetic field is disclosed. The magnetic field sensor includes at least two magnetic tunneling junction (MTJ) elements disposed on an underlying electrode. Each of the MTJ elements is formed by a synthetic antiferromagnetic layer, a barrier layer and a free layer sequentially stacked together. A top electrode is then connected to the free layers. The free layer can be a single free layer, a composite free layer, a synthetic antiferromagnetic free layer or an alloy free layer. When a current is applied to a metal circuit passing over or below the MTJ elements, free magnetic moments generated by the MTJ elements are anti-parallel to each other along a reference axis, and the angles between the magnetic moments created by the MTJ elements and the reference axis are 40 to 50 degrees and 130 to 140 degrees, respectively.

Abstract: An apparatus includes a structure that includes a bottom cap layer surrounding a metal pad. The apparatus also includes a magnetic tunnel junction (MTJ) device that includes a bottom electrode coupled to the structure. The MTJ device includes magnetic tunnel junction layers, a top electrode, and a logic cap layer. The MTJ device is offset with respect to the metal pad.

Abstract: A resistive switching device includes a first electrode and a transition metal oxide layer formed on the first electrode. An oxygen scavenging electrode is formed on the transition metal oxide wherein the oxygen scavenging electrode removes oxygen from the transition metal oxide layer to increase formation of oxygen vacancies in the transition metal oxide layer to enable a switching mode when a bias is applied between the first electrode and the oxygen scavenging electrode.

Abstract: A method of forming a semiconductor device that includes forming an at least partially relaxed semiconductor material, and forming a plurality of fin trenches in the partially relaxed semiconductor material. At least a portion of the plurality of fin trenches is filled with a first strained semiconductor material that is formed using epitaxial deposition. A remaining portion of the at least partially relaxed semiconductor material is removed to provide a plurality of fin structure of the first strained semiconductor material.

Abstract: A magnetic shift register includes a first supporting layer, a second supporting layer, a first pinning material layer, and at least one magnetic memory track. The first supporting layer has trenches on a first surface extending along a first direction. The second supporting layer is filled in the trenches, wherein the first support layer and the second support layer have at least a portion substantially equal in height. The first pinning material layer is disposed between the first supporting layer and the second supporting layer, wherein a plurality of end surfaces of the first pinning material layer are exposed on the first surface. The magnetic memory track extending along a second direction on the first surface is disposed over the first support layer, the first pinning material layer, and the second support layer, wherein the second direction is not the same or perpendicular to the first direction.

Abstract: A semiconductor device and a method for fabricating the same are provided to prevent a floating body effect and reduce coupling capacitance between buried bit lines. The semiconductor device comprises a first pillar disposed over a semiconductor substrate and including a vertical channel region, a bit line located in the lower portion of the vertical channel region inside the first pillar and a semiconductor layer extended from the semiconductor substrate to one sidewall of the first pillar.

Abstract: There is provided a semiconductor switch apparatus that can handle a wide range of input voltages. The switch apparatus includes a main switch that is provided between a first terminal and a second terminal, and a switch controller that, to turn on the main switch, supplies the same gate-source voltage to the main switch irrespective of a direction of a current flowing through the main switch. To turn on the main switch, the switch controller supplies the gate-source voltage that is determined based on at least one of a voltage of the first terminal and a voltage of the second terminal to a gate of the main switch.

Abstract: A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current density distribution around the first electrode.

Abstract: Embodiments of the present invention are directed to nanoscale memristor devices that provide nonvolatile memristive switching. In one embodiment, a memristor device includes an active region, a first electrode disposed on a first surface of the active region, and a second electrode disposed on a second surface of the active region, the second surface opposite the first surface. The first electrode is configured with a smaller width than the active region in a first direction, and the second electrode is configured with a larger width than the active region in a second direction. Application of a voltage to at least one of the electrodes produces an electric field across a sub-region within the active region between the first electrode and the second electrode.

Abstract: A method of manufacturing a magnetoresistive-based device having magnetic material layers formed between a first electrically conductive layer and a second electrically conductive layer, the magnetic materials layers including a tunnel barrier layer formed between a first magnetic materials layer and a second magnetic materials layer, including removing the first electrically conductive layer and the first magnetic materials layer unprotected by a first hard mask, to form a first electrode and a first magnetic materials, respectively; and removing the tunnel barrier layer, second magnetic materials layer, and second electrically conductive layer unprotected by the second hard mask to form a tunnel barrier, second magnetic materials, and a second electrode.

Abstract: Fabrication methods using Ion Beam Etching (IBE) for MRAM cell memory elements are described. In embodiments of the invention the top electrode and MTJ main body are etched with one mask using reactive etching such as RIE or magnetized inductively coupled plasma (MICP) for improved selectivity, then the bottom electrode is etched using IBE as specified in various alternative embodiments which include selection of incident angles, wafer rotational rate profiles and optional passivation layer deposited prior to the IBE. The IBE according to the invention etches the bottom electrode without the need for an additional mask by using the layer stack created by the first etching phase as the mask. This makes the bottom electrode self-aligned to MTJ. The IBE also achieves MTJ sidewall cleaning without the need for an additional step.

Abstract: A magnetoresistive element has a magnetic layer, an insulating layer and a magnetic layer, which are laminated on a base electrode, and side walls of the magnetic layers that are formed when the magnetic layers are processed. At least one element selected from the group of consisting He, C, N, O, F, Ne, Ti, V, Cu, Al, Si, P, S, Cl, Ar, Ge, As, Kr, Zr, In, Sn, Sb, Pb and Bi is injected into the side walls and edge portions of the magnetic layers to improve the magnetic characteristics of the first and second magnetic layers.

Abstract: MRAM cell comprising a magnetic tunnel junction comprising a storage layer having a net storage magnetization being adjustable when the magnetic tunnel junction is at a high temperature threshold and being pinned at a low temperature threshold; a sense layer having a reversible sense magnetization; and a tunnel barrier layer between the sense and storage layers; at least one of the storage and sense layer comprising a ferrimagnetic 3d-4f amorphous alloy material comprising a sub-lattice of 3d transition metals atoms providing a first magnetization and a sub-lattice of 4f rare-earth atoms providing a second magnetization, such that at a compensation temperature of said at least one of the storage layer and the sense layer, the first magnetization and the second magnetization are substantially equal. The disclosed MRAM cell can be written and read using a small writing and reading field, respectively.

Abstract: The present invention generally relates to a doped aluminum nitride hardmask and a method of making a doped aluminum nitride hardmask. By adding a small amount of dopant, such as oxygen, when forming the aluminum nitride hardmask, the wet etch rate of the hardmask can be significantly reduced. Additionally, due to the presence of the dopant, the grain size of the hardmask is reduced compared to a non-doped aluminum nitride hardmask. The reduced grain size leads to smoother features in the hardmask which leads to more precise etching of the underlying layer when utilizing the hardmask.

Abstract: A method for producing an electrical feedthrough in a substrate having an electrical feedthrough, including: forming an etch stop layer on the front side of the substrate; forming a mask on the back side of the substrate; forming an annular trench in the substrate, which trench extends from the back to the front side, by an etching process that stops at the etch stop layer, using the mask, the trench surrounding a substrate punch; depositing a metal layer over the back side of the substrate using the mask, the metal layer penetrating into the annular trench and being deposited on the substrate punch; forming a metal silicide layer on the substrate punch by at least partially converting the metal layer into the metal silicide layer on the substrate punch; selectively removing a remainder of the metal layer; and closing off the annular trench at the back side of the substrate.

Abstract: A semiconductor device includes: a lead frame; an IC element mounted on a main face of the lead frame; an inductor mounted on a back face of the lead frame; and a resin body configured to seal the lead frame, the IC element and the inductor, wherein the inductor and the lead frame are closely contacted with each other, wherein the IC element is disposed at a position corresponding to an center axis of the inductor, wherein the inductor and the IC element are electrically connected to each other, and wherein wiring of main current flowing through the IC element is disposed between terminals of the inductor.

Abstract: A step of forming a stacked film serving as a lower electrode, a step of forming an insulating film serving as a capacitive film on the stacked film, and a step of patterning the insulating film and the stacked film are performed. In the step of forming the stacked film, a film containing titanium, a film containing titanium and nitrogen, a main conductive film containing aluminum, a film containing titanium, and a film containing titanium and nitrogen are sequentially formed from below. The ratio of the surface roughness of the upper surface of the stacked film to the thickness of the insulating film is 14% or less.

Abstract: A semiconductor memory device includes a substrate including cell block, a balancing block, and a sense block. A plurality of cell bit lines are formed in the cell block of. A plurality of cell plugs are formed adjacent to side surfaces of the bit lines. Cell inner spacers, air spacers, and cell outer spacers are formed between the cell bit lines and the cell plugs. A plurality of balancing bit lines are formed in the balancing block. A plurality of balancing plugs are formed adjacent to side surfaces of the balancing bit lines. Balancing inner spacers and balancing outer spacers are formed between the balancing bit lines and the balancing plugs. The balancing bit lines and at least some of the cell bit lines are connected to the sense block.

Abstract: To improve productivity of a transistor that includes an oxide semiconductor and has good electrical characteristics. In a top-gate transistor including a gate insulating film and a gate electrode over an oxide semiconductor film, a metal film is formed over the oxide semiconductor film, oxygen is added to the metal film to form a metal oxide film, and the metal oxide film is used as a gate insulating film. After an oxide insulating film is formed over the oxide semiconductor film, a metal film may be formed over the oxide insulating film. Oxygen is added to the metal film to form a metal oxide film and added also to the oxide semiconductor film or the oxide insulating film.

Abstract: A method of forming a semiconductor structure. The semiconductor structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in Tinv and Vt of the pFET, while scaling Tinv and maintaining Vt for the nFET, resulting in the Vt of the pFET becoming closer to the Vt of a similarly constructed nFET with scaled Tinv values.

Abstract: A semiconductor device including: a semiconductor body having a first side and a second side opposite to one another; a first barrier element, which extends over the first side of the semiconductor body and is made of a first material configured to act as barrier against metal ions, for example chosen from among titanium, tantalum, titanium alloys or compounds, tantalum alloy; a magnetic element, which extends over the first barrier layer and is made of a second material having magnetic properties, for example a ferromagnetic material; a second barrier element, which extends over the magnetic layer and is made of a third material configured to act as barrier against metal ions, for example chosen from among titanium, tantalum, titanium alloys or compounds, tantalum alloys or compounds. The first and second barrier elements form a top encapsulating structure and a bottom encapsulating structure for the magnetic element.

Abstract: According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a sidewall of the trench.

Abstract: Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.

Abstract: The present invention discloses a discrete three-dimensional memory (3D-M). Its 3D-M arrays are located on at least one 3D-array die, while its read/write-voltage generator (VR/VW-generator) is located on a separate peripheral-circuit die. The VR/VW-generator generates at least a read and/or write voltage to the 3D-array die. A single VR/VW-generator die can support multiple 3D-array dies.

Abstract: The present inventive concept provides semiconductor devices that may include a capacitor including a lower electrode, a dielectric layer, and an upper electrode which are sequentially stacked. An electrode-protecting layer may be provided on the capacitor. The upper electrode may include a conductive metal oxide and the electrode-protecting layer may include a sacrificial reaction layer including a metal-hydrogen compound.

Abstract: Embodiments of the present disclosure are a method of forming a magnetic tunnel junction (MTJ) device and methods of forming a magnetic random access memory (MRAM) device. An embodiment is a method of forming a magnetic tunnel junction (MTJ) device, the method comprising forming an MTJ layer over a bottom electrode, forming a top electrode layer over the MTJ layer, and selectively etching the top electrode layer to form a top electrode over the MTJ layer. The method further comprises patterning an upper portion of the MTJ layer with an ion beam etch (IBE) process.

Abstract: A method of forming a conductive film, comprising the steps of: applying a composition comprising at least one metal compound selected from the group consisting of carboxylate salt, alkoxide, diketonato and nitrosylcarboxylate salt of a metal selected from among copper, palladium, rhodium, ruthenium, iridium, nickel and bismuth and a solvent to a substrate to form a coating film; and supplying a hydrogen radical to the coating film to carry out a hydrogen radical treatment.

Abstract: A method of a general biological approach to synthesizing compact nanotubes using a biological template is described.

Abstract: Embodiments are directed to STT MRAM devices. One embodiment of an STT MRAM device includes a reference layer, a tunnel barrier layer, a free layer and one or more conductive vias. The reference layer is configured to have a fixed magnetic moment. In addition, the tunnel barrier layer is configured to enable electrons to tunnel between the reference layer and the free layer through the tunnel barrier layer. The free layer is disposed beneath the tunnel barrier layer and is configured to have an adaptable magnetic moment for the storage of data. The conductive via is disposed beneath the free layer and is connected to an electrode. Further, the conductive via has a width that is smaller than a width of the free layer such that a width of an active STT area for the storage of data in the free layer is defined by the width of the conductive via.

Abstract: An embodiment of an integrated electronic device having a body, made at least partially of semiconductor material and having a top surface, a bottom surface, and a side surface, and a first antenna, which is integrated in the body and enables magnetic or electromagnetic coupling of the integrated electronic device with a further antenna. The integrated electronic device moreover has a coupling region made of magnetic material, which provides, in use, a communication channel between the first antenna and the further antenna.

Abstract: Methods and devices associated with phase change cell structures are described herein. In one or more embodiments, a method of forming a phase change cell structure includes forming a substrate protrusion that includes a bottom electrode, forming a phase change material on the substrate protrusion, forming a conductive material on the phase change material, and removing a portion of the conductive material and a portion of the phase change material to form an encapsulated stack structure.

Abstract: A mechanism is provided for a spin torque transfer random access memory device. A tunnel barrier is disposed on a reference layer, and a free layer is disposed on the tunnel barrier. The free layer includes an iron layer as a top part of the free layer. A metal oxide layer is disposed on the iron layer, and a cap layer is disposed on the metal oxide layer.

Abstract: A manufacturing method to form a memory device includes forming a hard mask on a magnetic stack. A first magnetic stack etch is performed to form exposed magnetic layers. A liner is applied to the exposed magnetic layers to form protected magnetic layers. A second magnetic stack etch forms a magnetic random access memory (MRAM) cell, where the liner prevents shunting between the protected magnetic layers.