Abstract: A method to make magnetic random access memory (MRAM), or integrated device in general, is provided. Oxygen ion implantation is used to convert the photolithography exposed areas into metal oxide dielectric matrix. To confine the oxygen ions within the desired region, heavy metals with large atomic number, such as Hf, Ta, W, Re, Os, Ir, Pt, Au is used as ion mask and bottom ion-stopping layer. An oxygen gettering material, selected from Mg, Zr, Y, Th, Ti, Al, Ba is added above and below the active device region to effectively capture the impinging oxygen. After a high temperature anneal, a buried metal oxide layer with sharp oxygen boundaries across the active device region can be obtained.

Abstract: A conductive via for connecting between a digit line and one side of the magnetic device is positioned beneath, and aligned with, each magnetic device. Other contacts may satisfy the same design rules, using the same process step. An electrode formed on the conductive via is polished to eliminate step functions or seams originating at the conductive via from propagating up through the various deposited layers. This integration approach allows for improved scaling of the MRAM devices to at least a 45 nanometer node, a cell packing factor approaching 6F2, and a uniform thickness of material between the bit lines and the underlying memory elements.

Abstract: A metal layer is deposited over a material layer. The metal layer includes an elemental metal that can be converted into a dielectric metal-containing compound by plasma oxidation or nitridation. A hard mask portion is formed over the metal layer. A plasma impermeable spacer is formed on at least one first sidewall of the hard mask portion, while at least one second sidewall of the hard mask portion is physically exposed. Plasma oxidation or nitridation is performed to convert physically exposed surfaces of the metal layer into the dielectric metal-containing compound. A sequence of a surface pull back of the hard mask portion, cavity etching, another surface pull back, and conversion of top surfaces into the dielectric metal-containing compound are repeated to form a hole pattern having a spacing that is not limited by lithographic minimum dimensions.

Abstract: Embodiments of mechanisms of forming an inductor structure are provided. The inductor structure includes a substrate and a first dielectric layer formed over the substrate. The inductor structure includes a first metal layer formed in the first dielectric layer and a second dielectric layer over the first metal layer. The inductor structure further includes a magnetic layer formed over the first dielectric layer, and the magnetic layer has a top surface, a bottom surface and sidewall surfaces between the top surface and the bottom surface, and the sidewall surfaces have at least two intersection points.

Abstract: A silicon precursor composition is described, including a silylene compound selected from among: silylene compounds of the formula: wherein each of R and R1 is independently selected from organo substituents; amidinate silylenes; and bis(amidinate) silylenes. The silylene compounds are usefully employed to form high purity, conformal silicon-containing films of Si02, Si3N4, SiC and doped silicates in the manufacture of microelectronic device products, by vapor deposition processes such as CVD, pulsed CVD, ALD and pulsed plasma processes. In one implementation, such silicon precursors can be utilized in the presence of oxidant, to seal porosity in a substrate comprising porous silicon oxide by depositing silicon oxide in the porosity at low temperature, e.g., temperature in a range of from 50° C. to 200° C.

Abstract: According to an embodiment, a magnetoresistive random access memory (MRAM) device comprises a bottom electrode, a stack, a dielectric material, a dielectric layer, and a conductive material. The bottom electrode is over a substrate, and the stack is over the bottom electrode. The stack comprises a magnetic tunnel junction (MTJ) and a top electrode. The dielectric material is along a sidewall of the stack, and the dielectric material has a height greater than a thickness of the MTJ and less than a stack height. The dielectric layer is over the stack and the dielectric material. The conductive material extends through the dielectric layer to the top electrode of the stack.

Abstract: An aspect of the present invention relates to ferroelectric ceramics including a stacked film formed on a Si substrate, a Pt film formed on the stacked film, a SrTiO3 film formed on the Pt film, and a PZT film formed on the SrTiO3, wherein the stacked film is formed by repeating sequentially N times a first ZrO2 film and a Y2O3 film, and a second ZrO2 film is formed on the film formed repeatedly N times, the N being an integer of 1 or more. It is preferable that a ratio of Y/(Zr+Y) of the stacked film is 30% or less.

Abstract: A method of forming a magnetic tunnel junction (MTJ) device includes forming a first MTJ cap layer on a MTJ structure. The first MTJ cap layer includes a first non-nitrified metal. The method also includes forming a second MTJ cap layer over the first MTJ cap layer. The second MTJ cap layer includes a second non-nitrified metal. The method further includes forming a top electrode layer over the second MTJ cap layer. The second MTJ cap layer is conductive and configured to reduce or prevent oxidation.

Abstract: A semiconductor memory storage array device comprises a first electrode layer, an oxide layer, a second electrode layer, a memory material layer and a first insulator layer. The oxide layer is disposed on the first electrode layer. The second electrode layer is disposed on the oxide layer. The memory material layer is disposed on the second electrode layer. The first insulator layer is disposed adjacent to two sidewalls of the first electrode layer, the oxide layer, the second electrode layer and the memory material layer, so to define a gap either between the first electrode layer and the oxide layer or between the second electrode layer and the oxide layer.

Abstract: It is possible to produce a ferroelectric thin film controlled to have the preferential crystal orientation in the (100) plane with a simple process without providing a seed layer or a buffer layer. A ferroelectric thin film is produced on a lower electrode by irradiating a surface of the lower electrode of a substrate having the lower electrode where the crystal plane is oriented in a (111) axis direction, with an atmospheric pressure plasma, coating a composition for forming a ferroelectric thin film on the lower electrode, and heating and crystallizing the coated composition.

Abstract: Described are embodiments to ensure that the equipment utilized to detect antigens is reliable and accurate. Accordingly, one embodiment of the invention includes a calibration assembly having nanoparticles, with known magnetic properties, spaced apart at known y-axis locations along the calibration assembly. In one embodiment, the calibration assembly may be used to calibrate a matched filter of the write and read circuitry. Because the calibration assembly comprises nanoparticles with known magnetic properties the read response of the read circuitry to a particular nanoparticle may be stored in the matched filter as an ideal signal for that nanoparticle. The ideal signal stored in the matched filter may then be utilized for reliably and accurately detecting antigens.

Abstract: A method to form small magnetic random access memory (MRAM) by dual ion implantation is provided. The first ion implantation add oxygen-gettering material surrounding the photo mask opened areas including sidewall followed by oxygen ion implantation to fully oxidize these oxygen-getter implanted areas into an electrically insulating layers to avoid current shunting during memory read/write time, and thus maximizing the tunneling magnetic resistance (TMR) signal. Such method is effective to repair the magnetic dead (weak or non magnetic but electrically conducting) layer on the sidewall.

Abstract: Methods of forming magnetic memory cells are disclosed. Magnetic and non-magnetic materials are formed into a primal precursor structure in an initial stress state of essentially no strain, compressive strain, or tensile strain. A stress-compensating material, e.g., a non-sacrificial, conductive material, is formed to be disposed on the primal precursor structure to form a stress-compensated precursor structure in a net beneficial stress state. Thereafter, the stress-compensated precursor structure may be patterned to form a cell core of a memory cell. The net beneficial stress state of the stress-compensated precursor structure lends to formation of one or more magnetic regions, in the cell core, exhibiting a vertical magnetic orientation without deteriorating a magnetic strength of the one or more magnetic regions. Also disclosed are memory cells, memory cell structures, semiconductor device structures, and spin torque transfer magnetic random access memory (STT-MRAM) systems.

Abstract: Voltage controlled magneto-electric tunnel junctions and memory devices are described which provide efficient high speed voltage switching of non-volatile magnetic devices (MeRAM) at high cell densities. A multi-bit-per-cell (MBPC) MeRAM is described which requires only a single transistor to write and read two data bits from the one MBPC MeRAM cell.

Abstract: A micro-electromechanical device and method of manufacture are disclosed. A sacrificial layer is formed on a silicon substrate. A metal layer is formed on a top surface of the sacrificial layer. Soft magnetic material is electrolessly deposited on the metal layer to manufacture the micro-electromechanical device. The sacrificial layer is removed to produce a metal beam separated from the silicon substrate by a space.

Abstract: A method for manufacturing a pattern multilayer body that has a plurality of pattern layers, and where a pattern is formed in each pattern layer, includes a step of forming an overlay pattern within an overlay pattern formation region, and in the step of forming the overlay pattern, a photoresist film is formed, and after a photoresist film is exposed via a main mask, a resist pattern is formed by exposing a sub mask(s). The main mask has a pattern light-shielding part that is commonly used for forming a pattern in each pattern layer, and each main light-shielding part for forming each overlay patter; and a sub mask has an opening part that is exposable to an unexposed region(s) within an overlay pattern formation region other than an unexposed region(s) on the photoresist film, which has been light-shielded by the main light-shielding part for forming a corresponding overlay pattern.

Abstract: A micro-electromechanical device and method of manufacture are disclosed. A sacrificial layer is formed on a silicon substrate. A metal layer is formed on a top surface of the sacrificial layer. Soft magnetic material is electrolessly deposited on the metal layer to manufacture the micro-electromechanical device. The sacrificial layer is removed to produce a metal beam separated from the silicon substrate by a space.

Abstract: Devices, methods and production devices that relate to the forming of a coil on a semiconductor substrate are provided. Arranged within the coil is a metal filling, for example with a density of less than 20%.

Abstract: The performance of an MR device has been improved by inserting one or more Magneto-Resistance Enhancing Layers (MRELs) into approximately the center of one or more of the magnetic layers such as an inner pinned (AP1) layer, spin injection layer (SIL), field generation layer (FGL), and a free layer. An MREL is a layer of a low band gap, high electron mobility semiconductor such as ZnO or a semimetal such as Bi. The MREL may further comprise a first conductive layer that contacts a bottom surface of the semiconductor or semimetal layer, and a second conductive layer that contacts a top surface of the semiconductor or semimetal layer.

Abstract: A semiconductor device includes a substrate, a multilayer wiring layer formed over the substrate, an MTJ (Magnetic Tunnel Junction) element formed in an insulating layer located lower than an uppermost wiring layer in the multilayer wiring layer, a wiring formed in a wiring layer immediately above the MTJ element and coupled to the MTJ element, and a shield conductor region provided in the wiring or a wiring layer immediately above the wiring, and covering an entirety of the MTJ element in a plan view.

Abstract: An integrated circuit contains lower components in the substrate, a PMD layer, upper components over the PMD layer, lower contacts in the PMD layer connecting some upper components to some lower components, an ILD layer over the upper components, metal interconnect lines over the ILD layer, and upper contacts connecting some upper components to some metal interconnect lines, and also includes annular stacked contacts of lower annular contacts aligned with upper annular contacts. The lower contacts and upper contacts each have a metal liner and a contact metal on the liner. The lower annular contacts have at least one ring of liner metal and contact metal surrounding a pillar of PMD material, and the upper contacts have at least one ring of liner metal and contact metal surrounding a pillar of ILD material. The annular stacked contacts connect the metal interconnects to the lower components.

Abstract: A basic Spin-Orbit-Torque (SOT) structure with lateral structural asymmetry is provided that produces a new spin-orbit torque, resulting in zero-field current-induced switching of perpendicular magnetization. More complex structures can also be produced incorporating the basic structure of a ferromagnetic layer with a heavy non-magnetic metal layer having strong spin-orbit coupling on one side, and an insulator layer on the other side with a structural mirror asymmetry along the in-plane direction. The lateral structural asymmetry and new spin-orbit torque, in effect, replaces the role of the external in-plane magnetic field. The direction of switching is determined by the combination of the direction of applied current and the direction of symmetry breaking in the device.

Abstract: A method for providing a magnetic junction usable in a magnetic device and the magnetic junction are described. A free layer and nonmagnetic spacer layer are provided. The free layer and nonmagnetic spacer layer are annealed at an anneal temperature of at least three hundred fifty degrees Celsius. A pinned layer is provided after the annealing step. The nonmagnetic spacer layer is between the pinned layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

Abstract: According to one embodiment, a memory includes a semiconductor layer including a trench which extends in a first direction, the trench having a first portion with a first depth and a second portion with a second depth deeper than the first depth, a gate insulating layer covering the semiconductor layer in the first portion, an element isolation layer covering the semiconductor layer in the second portion, the element isolation layer extending in a second direction from the second portion, a gate electrode provided on the gate insulating layer in the first portion and the element isolation layer in the second portion, the gate electrode filling the trench, and a third impurity region provided in the semiconductor layer direct below the first portion, the third impurity region being continuously in the first direction.

Abstract: A method for providing a dual magnetic junction usable in a magnetic device and the dual magnetic junction are described. First and second nonmagnetic spacer layers, a free layer and pinned are provided. The first pinned layer, free layer and nonmagnetic spacer layer may be annealed at an anneal temperature of at least three hundred fifty degrees Celsius before a second pinned layer is provided. The second pinned layer may include Co, Fe and Tb. The nonmagnetic spacer layers are between the pinned layers and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

Abstract: A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. The magnetic junction includes a free layer, a pinned layer and nonmagnetic spacer layer between the free and pinned layers. The free layer includes at least one of a hybrid perpendicular magnetic anisotropy (PMA) structure and tetragonal bulk perpendicular magnetic anisotropy (B-PMA) structure. At least one of the free layer and the pinned layer have a perpendicular magnetic anisotropy energy greater than an out-of-plane demagnetization energy. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.

Abstract: A magnetic tunnel junction (MTJ) device is formed by a process that includes forming a trench in a substrate and depositing an MTJ structure within the trench. The MTJ structure includes a bottom electrode, a fixed layer, a tunnel barrier layer, a free layer, and a top electrode. The process includes applying reverse photo etching to remove material that is not directly over the trench. The process also includes plagiarizing the MTJ structure without performing a photo-etch process on the MTJ structure.

Abstract: A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. The shape and/or configuration of the nonmagnetic bridge directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer of the structure is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell.

Abstract: The object of the present invention is to provide a method for preparing a nano-sheet array structure of a Group V-VI semiconductor, comprising: (A) providing an electrolyte containing a hydrogen ion and disposing an auxiliary electrode and a working electrode in the electrolyte, wherein the working electrode comprises a Group V-VI semiconductor bulk; and (B) applying a redox reaction bias to the auxiliary electrode and the working electrode to form a nano-sheet array structure on the bulk.

Abstract: A method of manufacturing a magnetoresistive-based device includes a metal hard mask that is inert to a top electrode etch chemistry and that has low sputter yield during a magnetic stack sputter. The metal hard mask is patterned by the photo resist and the photo mask is then stripped and the top electrode (overlying magnetic materials of the magnetoresistive-based device) is patterned by the metal hard mask.

Abstract: A perpendicular STT-MRAM comprises apparatus and a method of manufacturing a plurality of magnetoresistive memory element having local magnetic shielding. As an external perpendicular magnetic field exists, the permeable dielectric layers, the permeable bit line and the permeable bottom electrode are surrounding and have capability to absorb and channel most magnetic flux surrounding the MTJ element instead of penetrate through the MTJ element. Thus, magnetization of a recording layer can be less affected by the stray field during either writing or reading, standby operation.

Abstract: A spintronic device and a method for making said spintronic device. The spintronic device includes an epitaxial crystalline ferromagnetic oxide formed directly on the semiconductor material thereby allowing spin-polarized current to be efficiently injected from the ferromagnetic oxide into the semiconductor material. A host crystal lattice includes multiple sets of stacked oxide layers of material A and B of a perovskite structure with a formula of ABO3. After an oxide layer of B is grown, magnetic ions are introduced to intermix with the B material, which may replace some of the ions of the B material. The process of growing additional stacked oxide layers of material A and B and introducing further magnetic ions after the deposition of the oxide layer of B continues until enough magnetic ions are sufficiently close to one another that they align in the same direction thereby forming a ferromagnetic oxide on the semiconductor material.

Abstract: Multi-bit ferroelectric memory devices and methods of forming the same are provided. One example method of forming a multi-bit ferroelectric memory device can include forming a first ferroelectric material on a first side of a via, removing a material to expose a second side of the via, and forming second ferroelectric material on the second side of the via at a different thickness compared to the first side of the via.

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first cavity through the substrate, and a toroid inductor configured around the first cavity of the substrate. The toroid inductor includes a set of windings configured around the first cavity. The set of windings includes a first set of interconnects on a first surface of the substrate, a set of though substrate vias (TSVs), and a second set of interconnects on a second surface of the substrate. The first set of interconnects is coupled to the second set of interconnects through the set TSVs. In some implementations, the integrated device further includes an interconnect material (e.g., solder ball) located within the first cavity. The interconnect material is configured to couple a die to a printed circuit board. In some implementations, the interconnect material is part of the toroid inductor.

Abstract: The present invention relates to a cobalt (Co) and platinum (Pt)-based multilayer thin film having a novel structure and perpendicular magnetic anisotropy, and to a fabrication method thereof. More specifically, the invention relates to a cobalt and platinum-based multilayer thin film having perpendicular magnetic anisotropy (PMA), which includes thin cobalt layers and thin platinum layers alternately deposited over a substrate, and has an inverted structure in which a thickness of the thin cobalt layers is greater than that of the thin platinum layers, and to a fabrication method thereof. The cobalt and platinum-based multilayer thin film has a new structure in which the thickness of a magnetic thin layer is greater than that of a non-magnetic thin layer. The multilayer thin film may be easily applied as a free layer and a pinned layer in a magnetic tunnel junction by controlling the perpendicular magnetic anisotropy energy depending on the thickness ratio of the layers.

Abstract: Embodiments of mechanisms for forming a semiconductor device structure are provided. The semiconductor device structure includes a metal-insulator-metal (MIM) capacitor formed on a substrate. The semiconductor device structure also includes an inductor formed on the MIM capacitor. The semiconductor device structure further includes a via formed between the MIM capacitor and the inductor, and the via is formed in a plurality of dielectric layers, and the dielectric layers comprise an etch stop layer.

Abstract: A method for fabricating a semiconductor device includes forming a magnetic tunnel junction (MTJ) element on a substrate, forming a first capping layer along the shape of the MTJ element, forming an insulating layer on the first capping layer, forming a trench exposing a portion of the first capping layer above the MTJ element by selectively etching the insulating layer, forming a second capping layer on sidewalls of the trench, removing the exposed portion of the first capping layer using the second capping layer as an etching mask to expose an upper surface of the MTJ element, and forming a conductive layer in the trench, wherein the conductive layer contacts the upper surface of the MTJ element.

Abstract: A topological insulator structure includes an insulating substrate and a magnetically doped TI quantum well film located on the insulating substrate. A material of the magnetically doped TI quantum well film is represented by a chemical formula of Cry(BixSb1-x)2-yTe3. 0<x<1, 0<y<2. Values of x and y satisfies that an amount of a hole type charge carriers introduced by a doping with Cr is substantially equal to an amount of an electron type charge carriers introduced by a doping with Bi. The magnetically doped TI quantum well film is in 3 QL to 5 QL.

Abstract: A lower electrode film, a ferroelectric film, and an upper electrode film are formed on an insulation film covering a transistor formed on a semiconductor substrate. Furthermore, a Pt film is formed as a cap layer on the upper electrode film. Then, a hard mask (a TiN film and an SiO2 film) of a predetermined pattern is formed on the Pt film, and the Pt film and the upper electrode film are etched. Then, an insulating protective film is formed on an entire surface, and a side surface of the upper electrode film is covered with the insulating protective film. Next, the ferroelectric film and the lower electrode film are etched, thus forming a ferroelectric capacitor.

Abstract: In a method for fabricating a semiconductor device, a conductive layer is formed on a substrate, where the substrate has a bottom layer formed thereon. A magnetic tunnel junction layer is formed on the conductive layer. The magnetic tunnel junction layer is patterned using an etching gas containing oxygen. An insulating layer is formed by oxidizing the conductive layer exposed outside the patterned magnetic tunnel junction layer using the etching gas.

Abstract: Embodiments relate to a sensor device including a layer stack 600, the layer stack 600 including at least ferromagnetic and non-magnetic layers formed on a common substrate 620. The sensor device 600 further includes at least a first magneto-resistive sensor element 711 provided by a first section 611 of the layer stack 600. The first magneto-resistive sensor element 711 herein is configured to generate a first signal. The sensor device 600 also includes a second magneto-resistive sensor element 712 provided by a second section 612 of the layer stack 610. The second magneto-resistive sensor element 712 herein is configured to generate a second signal for verifying the first signal.

Abstract: A method of fabricating a semiconductor device includes providing a wafer in a chamber of a point-cusp magnetron physical vapor deposition (PCM-PVD) apparatus, the chamber including a metal target. The method further includes providing an inert gas and a reactive gas in the chamber and forming an amorphous conductive layer on the wafer by reacting the reactive gas with a metal atom separated from the metal target by the inert gas.

Abstract: A Hall Effect sensor with a graphene detection layer implemented in a variety of geometries, including the possibility of a so-called “full 3-d” Hall sensor, with the option for integration in a BiCMOS process and a method for producing said Hall Effect sensor is disclosed.

Abstract: Embodiments of the invention are described that use a thin metallic hard mask, which can be a bi-layer film, to increase the incident IBE angle for MTJ sidewall cleaning without losing the process margin for the subsequent interconnection process. The patterned metallic hard mask pads also serve as the top electrode for the MTJ cells. Using a thin metallic hard mask is possible when the hard mask material acts as a CMP stopper without substantial loss of thickness. In the first embodiment, the single layer hard mask is preferably ruthenium. In the second embodiment, the lower layer of the bi-layer hard mask is preferably ruthenium. The wafer is preferably rotated during the IBE process for uniform etching. A capping layer under the hard mask is preferably used as the etch stopper during hard mask etch process in order not to damage or etch through the upper magnetic layer.

Abstract: A method for manufacturing a semiconductor memory device includes forming a magnetic tunnel junction layer on a lower electrode, forming a spacer having an annular shape on the magnetic tunnel junction layer, forming upper electrodes on both sidewall surfaces of the annular shaped spacer, removing the spacer, and etching the magnetic tunnel junction layer by using the upper electrodes as an etch mask.

Abstract: Provided are a magneto resistive element and a method of manufacturing the same, and in particular, a magneto resistive element and a method of manufacturing the same that may be applied to a digitizer sensing panel. The magneto resistive element includes a substrate, a first electrode disposed on the substrate, a first hole transport layer disposed on the first electrode, a first magneto resistive layer disposed on the first hole transport layer, wherein the first magneto resistive layer comprises an organic material, a first transport layer disposed on the first magneto resistive layer, a second magneto resistive layer disposed on the first transport layer, wherein the second magneto resistive layer comprises an organic material, a first electron transport layer disposed on the second magneto resistive layer, and a second electrode disposed on the first electron transport layer.

Abstract: This invention comprises a method to make small MTJ element using hybrid etching and oxygen plasma immersion ion implantation. The method has no removal of the magnetic free layer (or memory layer) and hence prevents any possible physical damage near the free layer edges. After photolithography patterning, alternative Ta, Ru, Ta etchings are performed before it stops on an MgO intermediate layer above the free layer. Then an oxygen plasma immersion ion implantation is performed to completely oxidize the exposed portion of the free layer, leaving the hard mask covered portion unchanged which define the lateral width of the MTJ element.

Abstract: Embodiments of mechanisms of forming an inductor structure are provided. The inductor structure includes a substrate and a first dielectric layer formed over the substrate. The inductor structure includes a first metal layer formed in the first dielectric layer and a second dielectric layer over the first metal layer. The inductor structure further includes a magnetic layer formed over the first dielectric layer, and the magnetic layer has a top surface, a bottom surface and sidewall surfaces between the top surface and the bottom surface, and the sidewall surfaces have at least two intersection points.

Abstract: A light emitting diode including a magnetic structure and a method of fabricating the same are disclosed. The magnetic structure composed of passivation layers and a magnetic layer is disposed inside a luminous structure composed of an active layer and a semiconductor layer. In the light emitting diode, the magnetic structure including the magnetic layer is disposed on a side surface of the active layer to improve recombination rate of charge carriers for light emission by increasing influence of a magnetic field applied to the active layer. In addition, the light emitting diode according to the present invention allows change in position of the magnetic structure including the magnetic layer depending upon an etched shape of the luminous structure, thereby realizing various magnetic field distributions.

Abstract: A memory element having a layer structure, the layer structure includes: a memory layer whose magnetization direction is changed in accordance with information; a magnetization-fixed layer having magnetization perpendicular to a film surface to be a basis of the information stored in the memory layer; and an intermediate layer made of a non-magnetic material, disposed between the memory layer and the magnetization-fixed layer, wherein at least a periphery of the memory layer is covered with a magnetic material through a non-magnetic material among the layer structure.