Abstract: Disclosed is a method of fabricating a semiconductor device having improved processing stability. A protection layer may be formed on a semiconductor substrate. A sacrificial layer having an etch selectivity with respect to the protection layer may be formed on the protection layer. A part of the sacrificial layer may be selectively etched, thereby forming an alignment key. An aligned well may be formed using the alignment key. An aligned isolation layer may be formed in the semiconductor substrate having the well formed therein, using the alignment key.

Abstract: A wafer has thereon a plurality of integrated circuit die areas, scribe line that surrounds each of the integrated circuit die areas, and a laser marking region having therein a laser marking feature. A pad layer is formed on the wafer. AA photoresist pattern is formed on the pad layer. The AA photoresist pattern includes trench openings that expose STI trench areas within the integrated circuit die areas and dummy openings that merely expose a transitioning region of the laser-marking region. The pad layer and the substrate are etched through the trench openings and dummy openings, to form STI trenches within the integrated circuit die areas and dummy trenches in the transitioning region. A trench fill dielectric is deposited over the wafer and fills the STI trenches and the dummy trenches. Using the pad nitride layer as a polish stop layer, chemical mechanical polishing the trench fill dielectric.

Abstract: Disclosed herein is a method for manufacturing a semiconductor device. According to the present invention, a device isolation film having a step difference occurring during a process of forming a device isolation film in a scribe lane region serves as a first alignment key, and a second alignment key formed during a process of forming a recess gate region is used in the subsequent process, thereby improving the process steps and product cost.

Abstract: A surface position measuring method wherein measurement light is obliquely projected onto a substrate surface and on the basis of a position of the detected measurement light and a predetected offset, the position of the substrate surface with respect to a direction of an optical axis of the projection optical system is measured, memorizing a first position of a point on the substrate while using a reference mark provided on a substrate stage, measuring the position of the measurement light as a first measurement position; rotating the substrate by 180 deg. in a plane perpendicular to the optical axis; memorizing a second position of the measurement point on the rotated substrate with reference to the reference mark; measuring the position of the measurement light as a second measurement position; and detecting of the offset at the measurement point on the basis of the first and second measurement position.

Abstract: A method of wafer repairing comprises identifying locations and patterns of defective regions in a semiconductor wafer; communicating the locations and patterns of defective regions to a direct-writing tool; forming a photoresist layer on the semiconductor wafer; locally exposing the photoresist layer within the defective regions using an energy beam; developing the photoresist layer on the semiconductor wafer; and wafer-processing the semiconductor wafer under the photoresist layer after exposing and developing.

Abstract: A liquid crystal display (LCD) panel with marks for checking cutting precision by visual inspection is provided. A checkerboard mark is formed on an intersection of two adjacent cutting lines of the LCD panel. The checkerboard mark includes a pair of first-square marks in a diagonal relationship and a pair of second-square marks in a diagonal relationship. When completing cutting of the LCD panel, the cutting precision of the LCD panel can be checked by visually inspecting the distance between the square mark and the cutting line or the residue of the checkerboard mark. The checkerboard mark is suitable for various LCD panels' arrangement.

Abstract: An object of the present inventions is to overcome a problem that the presence of a metal film, which is opaque to a visible light, between a lower layer alignment mark and a photoresist prevents the detection of the lower layer alignment mark, to make the pattern formation difficult. In the present inventions, an insulating film is placed beneath the alignment mark in structure; an alignment mark consisting of said multi-layered film comprising an alignment mark layer and the insulating film, which constitutes a stepped part with an increased difference in level, is first formed, inside a mark hole, in a manner of self-alignment; and then the metal film which is the very cause of the above problem is formed thereon. Since the metal film itself has a stepped shape corresponding to the alignment mark, alignment can be made with great accuracy.

Abstract: A multi-layered semiconductor structure with free areas limiting the placement of test keys. First and second scribe lines intersect to define one corner point of a die. The first and second scribe lines are part of the multilayered structure and at least one layer of the multi-layer structure is a low-k dielectric layer. Free area A1 is defined on the first scribe line and is defined by the equation A1=D1×S1, where D1 is the distance from the corner point of the die toward the main area of the die, and S1 is the width of the first scribe line. Free area AS is defined at the intersection of the first scribe line and the second scribe line adjacent the die and is defined by the equation AS=S1×S2, where S2 is the width of the second scribe line.

Abstract: A semiconductor device includes a first insulation layer including a first conductor pattern, a second insulation layer formed on the first insulation layer and including a second conductor pattern, and a third conductor pattern formed on the second insulation layer, wherein there is formed a first alignment mark part in the first insulation layer by a part of the first conductor pattern, the third conductor pattern is formed with a second alignment mark part corresponding to the first alignment mark part, the first and second alignment marks forming a mark pair for detecting alignment of the first conductor pattern and the third conductor pattern, the second conductor pattern being formed in the second insulation layer so as to avoid the first alignment mark part.

Abstract: A first film layer is formed over a substrate. A portion of the first film layer is removed to form a first alignment mark pattern and a first conductive layer is formed to fill the first alignment mark pattern to form a first alignment mark. A second film layer is formed and a portion of the second film layer is removed to form openings and to form a second alignment mark pattern. A second conductive layer is formed to fill the openings to form first conductive wires and to fill the second alignment mark pattern to form a second alignment mark. A third film layer and a hard mask layer are formed over the second film layer and a portion of the hard mask layer and the third film layer is removed to form via openings. A third conductive layer is formed in the via openings.

Abstract: A method comprising adjusting a first relative position between a substrate and a fabrication unit by a first shift value, forming a first pattern relative to a first pattern instance on the substrate subsequent to adjusting the first relative position by the first shift value, and calculating a second shift value using a first displacement between the first pattern and the first pattern instance and a second displacement between a second relative position of the first pattern instance with respect to a second pattern instance is provided.

Abstract: Disclose is a combined scatterometry mark comprising a scatterometry critical dimension (CD) or profile target capable of being measured to determine CD or profile information and a scatterometry overlay target disposed over the scatterometry CD or profile target, the scatterometry overlay target cooperating with the scatterometry CD or profile target to form a scatterometry mark capable of being measured to determine overlay.

Abstract: A method for reducing a thickness variation of a nitride layer in a shallow trench isolation (STI) CMP process is provided, the method including forming an active region pattern in an alignment key region of a scribe lane where a device isolation film is formed at an ISO level, and forming a dummy active region pattern substantially adjacent to a vernier key pattern in the scribe lane during formation of the vernier key pattern, wherein the dummy active region pattern is spaced apart from the vernier key pattern by a known distance. Preferably, the active region pattern and the dummy active region pattern are formed prior to the STI CMP process.

Abstract: A marker structure on a substrate includes line elements and trench elements, the line elements and trench elements each having a length in a first direction and being arranged in an alternating repetitive sequence in a second direction perpendicular to the first direction, the alternating repetitive sequence having a sequence length, the marker structure having at least one pitch value, the at least one pitch value being the sum of a line width of one line element and a trench width of one trench element. A width of the line elements varies over the sequence length of the marker structure between a minimum line width value and a maximum line width value, while a width of the trench elements likewise varies over the sequence length of the marker structure between a minimum trench width value and a maximum trench width value. A duty cycle of a pair of a line element and an adjacent trench element is substantially constant over the sequence length of the marker structure.

Abstract: An overlay key includes a first overlay key having a first main overlay pattern and a first auxiliary pattern, and a second overlay key having a second main overlay pattern and a second auxiliary overlay pattern, the second auxiliary overlay pattern formed at a location corresponding to the first auxiliary overlay pattern.

Abstract: A device for locally treating a substrate is disclosed. The device includes an enclosure for forming an enclosed environment at a location on the substrate, a seal for sealing the enclosed environment between the enclosure and the substrate, a supply channel for supplying a chemical reactant to the location, and a removal channel for removing a chemical from the enclosed environment.

Abstract: A semiconductor device composed of III-nitride materials is produced with epitaxial growth that permits vertical and lateral growth geometries to improve device characteristics. The resulting device has a greater breakdown voltage due to the greater integrity of the semiconductor material structure since no ion implantation processes are used. The epitaxially grown layers also exhibit greater thermal conductivity for improved operation with power semiconductor devices. The device may include a laterally grown charge compensated area to form a superjunction device. The resulting device may be bidirectional and have improved breakdown voltage in addition to higher current capacity for a given voltage rating.

Abstract: A method for manufacturing a marker structure including line elements and trench elements arranged in a repetitive order includes filling the trench elements with silicon dioxide and leveling the marker structure. A sacrificial oxide layer is grown on the semiconductor surface, and a first subset of the line elements is exposed to an ion implantation beam including a dopant species to dope and change an etching rate of the first subset. The substrate is annealed to activate the dopant species, and the semiconductor surface is etched to remove the sacrificial oxide layer and to level the first subset to a first level and to create a topology such that the first subset has a first level differing from a second level of a surface portion of the marker structure different from the first subset.

Abstract: A semiconductor wafer includes a plurality of active circuit die areas, each of which being bordered by a dicing line region through which the plurality of active circuit die areas are separated from each other by mechanical wafer dicing. Each of the plurality of active circuit die areas has four sides. An overcoat covers both the active circuit die areas and the dicing line region. An inter-layer dielectric layer is disposed underneath the overcoat. A reinforcement structure includes a plurality of holes formed within the dicing line region. The plurality of holes are formed by etching through the overcoat into the inter-layer dielectric layer and are disposed along the four sides of each active circuit die area. A die seal ring is disposed in between the active circuit chip area and the reinforcement structure.

Abstract: Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.

Abstract: A semiconductor wafer includes (a) a first principal side and a second principal side opposite to each other, (b) a first bevel contour and a second bevel contour provided at an outer periphery of the first principal side and the second principal side, (c) a first recess formed in the first bevel contour, and (d) a first type of ID mark configured by a protruding dot provided on a bottom face of the first recess.

Abstract: Aspects of the invention can provide an alignment method that is preferably applicable when manufacturing equipments by liquid-phase processing. The alignment method in a device manufacturing process can include forming of a functional film on a substrate by liquid-phase processing, forming an alignment mark on the substrate on which the functional film is formed so as to make a pattern of the alignment mark appear on a film that is formed after forming the functional film, and aligning the film that is formed after forming the functional film by using the alignment mark.

Abstract: In a method according to one embodiment of the invention, a plurality of markers are printed in resist on a substrate at a range of angles relative to a crystal axis of the substrate. The markers are etched in to the substrate using an anisotropic etch process, such that after the etch the apparent positions of the markers are dependent on their orientation relative to the crystal axis. The apparent positions of the markers are measured, and from this information the orientation of the crystal axis is derived.

Abstract: An optical target is provided. In one embodiment, the target is formed on a substrate. The target includes a first layer deposited below a second layer on the substrate. The second layer is deposited below a third layer on the substrate. The first layer has a topographic contour formed thereon, the first layer at least partially projecting a patterned topographical contour through the second layer to the third layer.

Abstract: Aperture masks and deposition techniques for using aperture masks are described. In addition, techniques for creating aperture masks and other techniques for using the aperture masks are described. The various techniques can be particularly useful in creating circuit elements for electronic displays and low-cost integrated circuits such as radio frequency identification (RFID) circuits. In addition, the techniques can be advantageous in the fabrication of integrated circuits incorporating organic semiconductors, which typically are not compatible with wet processes.

Abstract: A method of manufacturing functional elements by forming a plurality of functional elements each having a through-hole piercing a surface on a substrate. The method includes the steps of forming an alignment mark on a surface of the substrate in an area in which the functional elements are constituted and the through-hole is formed in an additional process, forming an anti-etching layer on a reverse surface of the substrate, and providing on the reverse surface of the substrate a photomask having a pattern shape for forming the through-hole and a mark shape for registering the alignment mark and forming the through-hole by removing the etching layer corresponding to the through-hole. The mark shape is located at a position corresponding to a region where the through-hole is formed on the reverse surface of the substrate and is capable of being registered to the alignment mark.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate and forming a projecting alignment mark. The substrate includes an insulating layer and a semiconductor layer on the insulating layer, and the substrate includes device areas and a scribe line area which surrounds the device area in the semiconductor layer. The projecting alignment mark is formed on the scribe line area.

Abstract: Disclosed are a semiconductor wafer, a semiconductor device, and a method of manufacturing the semiconductor device, which are capable of easily carrying out an alignment between a semiconductor substrate and an electron beam exposure apparatus.

Abstract: The invention relates to a method for creating a pattern on a substrate comprising a first alignment structure, using an elastomeric stamp comprising a patterning structure and a second alignment structure. The method comprises a moving step for moving the elastomeric stamp towards the substrate, and a deformation step for deforming the patterning structure with a tensile or compressive force generated by cooperation of the first alignment structure and the second alignment structure.

Abstract: An alignment target includes periodic patterns on two elements. The periodic patterns are aligned when the two elements are properly aligned. By measuring the two periodic patterns at multiple polarization states and comparing the resulting intensities of the polarization states, it can be determined if the two elements are aligned. A reference measurement location may be used that includes third periodic pattern on the first element and a fourth periodic pattern on the second element, which have a designed in offset, i.e., an offset when there is an offset of a known magnitude when the first and second element are properly aligned. The reference measurement location is measured at two polarization states. The difference in the intensities of the polarization states at reference measurement location and is used to determine the amount of the alignment error.

Abstract: An alignment target includes periodic patterns on two elements. The alignment target includes two locations, at least one of which has a designed in offset. In one embodiment, both measurement locations have a designed in offset of the same magnitude but opposite directions. For example, two separate overlay patterns that are mirror images of each other may be used. Alternatively, the magnitudes and/or directions may vary between the measurement locations. The radiation that interacts with the measurement locations is compared. The calculated difference is extremely sensitive to any alignment error. If the difference between the patterns is approximately zero, the elements are properly aligned. When an alignment error is introduced, however, calculated difference can be used to determine the error. In one embodiment, the alignment target is modeled to determine the alignment error. In another embodiment, additional overlay patterns with additional reference offsets are used to determine the alignment error.

Abstract: Using an imaging system in relation to a plurality of material layers in an initial alignment state is provided, a first of the plurality of material layers at least partially obscuring a second of the plurality of material layers in the initial alignment state. The first material layer is moved from a first position corresponding to the initial alignment state to a second position out of a field of view of the imaging system, and a first image of the second material layer is stored. The first material layer is moved back the first position to restore the initial alignment state. A second image of the first material layer is acquired. The second image and the stored first image are processed to determine the initial alignment state.

Abstract: A scheme for aligning opaque material layers of a semiconductor device. Alignment marks are formed in a via level of the semiconductor device. The alignment marks are formed using a separate lithography mask, and may have about the same length as vias formed in the via layer. The alignment marks comprise trenches that are not filled with material and are not exposed to a CMP process. An opaque material layer is deposited, and depressions are formed in the opaque material layer over the alignment mark trenches. The depressions in the opaque material layer are used to align a lithography process to open the opaque material layer over alignment marks in an underlying metallization layer. The alignment marks in the metallization layer are then used to align the lithography process used to pattern the opaque material layer.

Abstract: A manufacturing method of a plasma display panel and the plasma display panel made using the manufacturing method include the align marks being maintained in a discernible state. The method for manufacturing a plasma display panel includes forming electrodes on a substrate along one direction, and forming align marks on edges of the substrate, depositing a dielectric paste on the substrate covering the align marks, drying the dielectric paste, and baking the dielectric paste to thereby form a dielectric layer. The align marks are left fully remaining such that they are easily discernible, thereby making sealing and other processes easy.

Abstract: A mask blank has a plurality of pattern formation regions in which mask circuit patterns are to be formed, and a supporting region in which any mask circuit pattern is not to be formed. The supporting region is provided for holding the plurality of pattern formation regions while separating the plurality of pattern formation regions from each other. The supporting region has first and second alignment marks. Exposure of a mask made from the mask blank for forming mask circuit patterns thereon is performed on the basis of the first alignment marks, and exposure of a substrate for forming circuit patterns thereon is performed on the basis of the second alignment marks. With this configuration, a mask used for charged particle beam reduction-and-division transfer exposure can be highly accurately produced at a low cost, and exposure of a substrate can be highly accurately performed by using the mask.

Abstract: A method of forming a crystalline silicon layer that includes forming a semiconductor layer of amorphous silicon on a substrate having a first region and a second region at a periphery of the first region; forming at least one concave-shaped alignment key by irradiating a laser beam onto the semiconductor layer in the second region; and crystallizing the semiconductor layer in the first region using the at least one alignment key.

Abstract: In a semiconductor device including a monocrystalline thin film transistor 16a that has been formed on a monocrystalline Si wafer 100 and then is transferred to a insulating substrate 2, LOCOS oxidization is performed with respect to the element-isolation region of the monocrystalline Si wafer 100 so as to create a field oxide film (SiO2 film) 104, and a marker 107 is formed on the field oxide film 104. With this structure, alignment of components may be performed based on a gate electrode 106 upon or after the transfer step.

Abstract: An integrated circuit capable of operating despite a profile shift is disclosed. Overlay marks on the integrated circuit are surrounded by a trench that tends to relieve the effect of a profile shift caused by stress applied to the integrated circuit. The position of the overlay marks tends, therefore, not to be affected by the stress.

Abstract: A method for measuring overlay in semiconductor wafers includes obtaining diffraction based and imaging based measurements of the same target. The two separate measurements are then combined in a way that is consistent to both measurements to obtain an overlay measurement that has high precision and large range.

Abstract: A semiconductor wafer comprises a wafer formed of a semiconductor material having a peripheral edge portion and a repeating mark on the edge portion of the wafer to allow identification of the wafer. Also described is a method of identifying and tracking these semiconductor wafers.

Abstract: An integrated circuit in which measurement of the alignment between subsequent layers has less susceptibility to stress induced shift. A first layer of the structure has a first overlay mark. A second and/or a third layer are formed in the alignment structure and on the first layer. Portions of the second and/or third layer are selectively removed from regions in and around the first overlay mark. A second overlay mark is formed and aligned to the first overlay mark. The alignment between the second overlay mark and first overlay mark may be measured with an attenuated error due to reflection and refraction or due to an edge profile shift of the first overlay mark.

Abstract: A semiconductor structure including a semiconductor substrate, an isolation trench in the semiconductor substrate, and an alignment trench in the semiconductor substrate is disclosed. The structure also includes a dielectric layer and a metallic layer. The dielectric layer is on the semiconductor substrate and in both the isolation trench and the alignment trench. The dielectric layer fills the isolation trench and does not fill the alignment trench. The metallic layer is on the dielectric layer.

Abstract: An overlay vernier pattern for measuring multi-layer overlay alignment accuracy and a method for measuring the same is provided. A distance between a first alignment mark in a first material layer and a second alignment mark in an underlying second material layer is measured, so as to provide an alignment offset between the first material layer and the second material layer in addition, a distance between the second alignment mark in the second material layer and a third alignment mark in a third material layer underlying the second material layer is measured, so as to provide an alignment offset between the second material layer and the third material layer. The second alignment marks can be repeatedly used when measuring the alignment accuracy between the first and the second material layers measuring the alignment accuracy between the second and the third material layers.

Abstract: An overlay vernier pattern for measuring multi-layer overlay alignment accuracy and a method for measuring the same is provided. A distance between a first alignment mark in a first material layer and a second alignment mark in an underlying second material layer is measured, so as to provide an alignment offset between the first material layer and the second material layer. In addition, a distance between the second alignment mark in the second material layer and a third alignment mark in a third material layer underlying the second material layer is measured, so as to provide an alignment offset between the second material layer and the third material layer. Because the second alignment marks can be repeatedly used, scribe line areas for forming these alignment marks and measuring time are saved to increase the production throughput.

Abstract: An electronic device is provided that includes an organic panel, including a platform made of an electrically nonconductive material; a first electrode on the platform; an organic active layer on the first electrode; a second electrode on the organic active layer; and a first alignment structure, in addition, a driver panel is provided and includes a substrate; a driver circuit formed on the substrate; and a second alignment structure for coupling with the first alignment structure to position the organic panel and driver panel in substantial alignment, and to electrically couple the driver circuit to the organic active layer.

Abstract: A semiconductor process wafer having substantially co-planar active areas and a laser marked area in an adjacent inactive area and method for forming the same to eliminate a step height and improve a subsequent patterning process over the active areas wherein an inactive area trench is formed overlying the laser marked area in parallel with formation of STI trenches in the active area whereby the active areas and the inactive area are formed substantially co-planar without a step height.

Abstract: An overlay target includes two pairs of test patterns used to measure overlay in x and y directions, respectively. Each test pattern includes upper and lower grating layers. A single pitch (periodic spacing) is used for all gratings. Within each test pattern, the upper and lower grating layers are laterally offset from each other to define an offset bias. Each pair of test patterns has offset biases that differ by the grating pitch/4. This has the important result that the combined optical response of the test patterns is sensitive to overlay for all values of overlay. An algorithm obtains overlay and other physical properties of the two or more test patterns from their optical responses in one combined regression operation.

Abstract: A method of testing a test wafer includes shielding test centers on a test wafer using shielding tabs during the deposition of a layer. The test wafer has the same size and shape of product wafers. The shielding tabs are then removed from the test wafer. A plurality of predetermined points which are separated from each test center by a critical interval are checked, and whether each point is covered by the layer is determined through an interferometer or a microprobe. The test wafer is processed after adjustments to or maintenance on equipment, or after a fixed number of product wafers have been processed.

Abstract: A common carrier for forming multiple printheads thereon and method of forming thereof is described. The common carrier includes a carrier substrate for adhering a plurality of unprocessed, integrateable semiconductor chips. Once adhered, the carrier substrate is lithographically processed to form a plurality of integrated circuit (IC) printhead chips such that alignment of the IC chips on the carrier substrate has the precision of lithographic alignment tolerances which is well within printhead alignment requirements.

Abstract: In a semiconductor device including a semiconductor wafer having a first main surface where a circuit element is formed, electrode pads are formed at an upper portion of the first main surface of the semiconductor wafer electrically connected with the circuit element. Index marks are formed on a second main surface of the semiconductor wafer that is opposite the first main surface. The index marks consist of line segments and indicate a direction along which the semiconductor device is to be mounted.