Abstract: An overlay mark for checking the alignment accuracy between a lower layer and a lithography process for defining an upper layer is described, including a part of the lower layer having two first x-directional trenches, two first y-directional trenches, two second x-directional trenches and two second y-directional trenches therein, and two x-directional and two y-directional photoresist bars thereover that are surrounded by the trenches and formed in the lithography process. When the lower layer is fully aligned with the lithography process, the intersection of the central line of the two first x-directional trenches and that of the two first y-directional trenches, the intersection of the central line of the two second x-directional trenches and that of the two second y-directional trenches and the intersection of the central line of the two x-directional photoresist lines and that of the two y-directional photoresist lines coincide with each other.

Abstract: An alignment apparatus for a substrate bonding system is provided with a first optical arm arranged to direct onto a detector radiation from a first alignment mark on a first substrate, and a second optical arm arranged to direct onto the detector radiation from a second alignment mark on a second substrate. The first alignment mark has a known location relative to a functional pattern provided on an opposite side of the first substrate, and the second alignment mark has a known location relative to a functional pattern provided on an opposite side of the second substrate. The substrate bonding system can be further provided with first and second substrate tables arranged to hold the first and second substrates such that they face one another, at least one of the substrate tables being movable in response to a signal output from the detector, thereby allowing the first and second substrates to be aligned with respect to each other for bonding.

Abstract: A method for checking the alignment accuracy using an overlay mark is provided. The overlay mark includes an inner mark and an outer mark formed on a wafer. The outer mark is formed in a lower layer on the wafer when the lower layer is patterned. The inner mark is formed within the outer mark over the lower layer when a lithography process for defining an upper layer is performed. A measurement process is conducted to obtain a first relation between each of the interior profiles of the outer marks and a second relation between each of the inner marks. Alternatively, a third relation between each of the interior profiles of the outer marks and each of the inner marks is obtained. The X-directional alignment accuracy and y-directional alignment accuracy are computed according to the first and the second relations, or the third relation.

Abstract: A dicing die-bonding film has a supporting substrate, an adhesive layer formed on the supporting substrate, and a die-bonding adhesive layer formed on the adhesive layer, and further has a mark for recognizing the position of the die-bonding adhesive layer. It is possible to provide a dicing die-bonding film in which in the case a semiconductor wafer and the dicing die-bonding film are stuck onto each other, the position of the die-bonding adhesive layer in the film can be recognized.

Abstract: A method for manufacturing a semiconductor device, includes: forming a recognition mark that defines a well-forming region for forming a well on a semiconductor substrate; forming a mask, using the recognition mark, that is patterned so that the well-forming region is opened; introducing an impurity into the well-forming region; performing heat treatment for forming a well by diffusing the impurity; and forming an element isolation region on the semiconductor substrate.

Abstract: A semiconductor wafer includes a semiconductor substrate, a semiconductor layer, and an oxide layer. The semiconductor layer is disposed on a surface of the semiconductor substrate and has a crystal structure similar to a crystal structure of the semiconductor substrate. The semiconductor layer includes an element section and a scribe section. The scribe section is disposed to divide the element section into a plurality of portions and is configurated to be used as a cutting allowance for dicing. Each of the portions includes a column structure in which columns having different conductivity types are arranged alternately. The oxide layer is disposed on a surface of the scribe section to be exposed to an outside of the semiconductor device.

Abstract: A method for manufacturing a semiconductor device comprises forming a laser marking, forming a trench pattern, forming a metal interconnection layer, removing a predetermined portion of the metal interconnection layer, and planarizing the metal interconnection layer. The laser marking is formed in a first region of a wafer, and the first region has a first width from an edge of the wafer. The trench pattern is formed above the wafer except for above the first region. The metal interconnection layer is formed above the wafer where the laser marking and the trench pattern are formed. The predetermined portion of the metal interconnection layer is removed, and the predetermined portion has a second width from the edge of the wafer equal to or greater than the first width. And the metal interconnection layer above the wafer where the trench pattern is formed is planarized to a predetermined thickness.

Abstract: A small-size (w<0.5 micrometers) alignment mark in combination with a “k1 process” is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT alignment. The “k1 process” is utilized to etch away polysilicon studded in the alignment mark trenches and refresh the trench profile prior to AA pattern transferring, thereby improving wafer alignment accuracy and precision.

Abstract: A method of forming a monitor mark includes forming an insulating film on a semiconductor substrate, and forming a first repetitive line pattern group and a second repetitive line pattern group by patterning the insulating film on the semiconductor substrate, such that the first repetitive line pattern group and the second repetitive line pattern group face each other with a predetermined space therebetween.

Abstract: In a method of fabricating a semiconductor optical device, insulating structures for an alignment mark for use in electron beam exposure is formed on a primary surface of a first III-V semiconductor region. After forming the insulating structures, a second III-V semiconductor region is grown on the first III-V semiconductor region to form an epitaxial wafer. The height of the insulating structures is larger than thickness of the second III-V semiconductor region. After forming the second III-V semiconductor region, alignment for the electron beam exposure is performed. After the alignment, a resist is exposed to electron beam to form a resist mask. The resist mask has a pattern for a diffraction grating, and the resist is on the epitaxial wafer.

Abstract: An electronic device is formed by epitaxially growing a Si substrate on a Si layer of an SOI substrate in which the Si layer is deposited on a front surface of a substrate with an insulating layer interposed therebetween; forming an element on a front-surface side of the Si substrate; and forming a back-surface element aligned with respect to the element, on a back-surface side of the Si substrate after the substrate is etched. A mark is formed by etching and removing the Si layer and the insulating layer in a predetermined position of the SOI substrate. The element is formed using a concave part as a reference position. The concave part appears on the front surface of the Si substrate epitaxially grown on the mark. The back-surface element is formed using the mark as a reference position. The mark appears after the substrate is etched.

Abstract: Correcting for misalignment of a substrate before it is exposed is performed using offset corrections and process corrections that are calculated based on alignment offset measurements of alignment marks and overlay measurements of overlay targets on substrates in previous batches.

Abstract: In a method for measuring the bonding quality of bonded substrates, such as bonded SOI wafers, a plurality of marks are created at a first side of a top substrate after, or before, the bonding of the top substrate onto a bottom substrate. Then, the positions of the plurality of marks are measured using a metrology tool. Next, for each of the marks, a difference between a measured position and an expected position is calculated. These differences can be used to determine delamination between the top substrate and the bottom substrate. By displaying a vector field representing the differences, and by not showing vectors that exceed a certain threshold, the delamination areas can be made visible.

Abstract: An alignment mark mask element protects an underlying alignment mark during subsequent processing of a fabrication substrate. The alignment mark mask element is formed concurrent with formation of a photomask from a dual-tone photoresist that exhibits a pattern reversal upon exposure to an energy level. A portion of the dual-tone photoresist above the alignment mark is exposed to an energy sufficient to reverse a positive tone resist to a negative tone, which remains above the alignment mark after developing. The remainder of the dual-tone photoresist is exposed through a reticle at a lesser energy level and patterned to define aperture locations of a photomask for formation of semiconductor device features. In addition, a photomask for use on a fabrication substrate and an intermediate semiconductor device are disclosed. Methods of forming a photomask and an intermediate semiconductor device structure are also disclosed.

Abstract: A method of manufacturing a semiconductor wafer for dicing includes providing a semiconductor wafer including a substrate and a plurality of upper layers on the substrate that form a formation of die areas. The formation is arranged so that adjacent die areas are separated by a path for a dicing tool within each path, a pair of spaced apart lines is fabricated. Each line defines a dicing edge of a respective path and has at least one trench extending between a top surface of the wafer and the substrate. Each trench is filled with a stress absorbing material for reducing die tool induced stress on the die areas during dicing.

Abstract: Exemplary embodiments of the present invention provide a method of manufacturing a semiconductor device that can take a connection between layers without giving damage to a layer, which is underlying. The semiconductor device includes forming conductive members Ms and Md at a predetermined position of a semiconductor film, forming an insulating film on a whole surface of a substrate excluding the conductive members Ms and Md, and forming a conductive film that is connected to the semiconductor film with the conductive member Ms and Md.

Abstract: A product information marking method including a back side grinding step for grinding the back side of a wafer having a plurality of devices formed on the front side so as to be partitioned by a plurality of separation lines, thereby obtaining a desired thickness of the wafer. After performing the back side grinding step, a marking step for marking product information on the back side of each device by applying a laser beam to the back side of the wafer is performed before separating the devices from each other. Thus, the product information is marked on each device in the stage of the wafer.

Abstract: A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.

Abstract: A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target including a high atomic weight layer formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.

Abstract: A method for forming a semiconductor device comprising forming an inter-layer dielectric (ILD) layer on a semiconductor substrate; forming a first trench and second trench in a cell area on the ILD layer, wherein the second trench has a width which is wider than the first trench; forming a first metal layer on the substrate, such that the first metal layer fills the first trench and does not entirely fill the second trench; performing a planarization process on the first metal layer such that the surface of the first metal layer in the first trench and the surface of the substrate has a height which is different than the height of the surface of the first metal layer in the second trench; and forming a plurality of align key and overlay key areas by forming a second metal layer on the surface of the substrate and first metal layer.

Abstract: A method for fabricating a device adapted for precision aligning integrated circuits having small-scale architecture in a stack, the method includes obtaining dimensions of the integrated circuits; fabricating a precision guide using the dimensions; and fabricating alignment fiducials into at least one of the precision guide and a carrier wafer. A method for placing integrated circuits having small-scale architecture into a stack, the method includes selecting a device adapted for precision aligning the integrated circuits into the stack and precision aligning the integrated circuits into the stack.

Abstract: A tape carrier type semiconductor device comprising: a long flexible insulating tape; and a plurality of semiconductor devices sequentially arranged on one surface of the tape, wherein each semiconductor device has a wiring pattern and a semiconductor element, and wherein each semiconductor device has either a hole or a target mark inside a predetermined region enclosed by an outline of the semiconductor device, the outline being for die-cutting into pieces, the hole being bored through the tape for indicating that the semiconductor device is a non-defective, the target mark not being bored through the tape for indicating that the semiconductor device is a defective.

Abstract: A method of indexing a plurality of dice obtained from a material wafer comprising a plurality of stacked material layers, each die being obtained in a respective die position in the wafer, the method including providing a visible index on each die indicative of the respective die position, wherein providing the visible index on each die includes: forming in a first material layer of the die a reference structure adapted to defining a mapping of the wafer; and forming in a second material layer of the die a marker associated with the reference structure, a position of the marker with respect to the reference structure being adapted to provide an indication of the die position in the wafer.

Abstract: A manufacturing method of a semiconductor wafer includes forming a plurality of alignment trenches in the wafer substrate. A dielectric layer is formed over the substrate filling the trenches. A planarization process is performed to remove the dielectric layer above the substrate. A photolithograph process is subsequently performed to selectively remove the dielectric layer formed in the trenches in the alignment area.

Abstract: A method for stacking and bonding wafers in precision alignment by detecting alignment marks provided on wafer edges, comprising the steps of: (a) providing at least a first wafer having at least a first pattern and at least a second pattern disposed on the cross-section thereof, at least a second wafer having at least a third pattern and at least a fourth pattern disposed on the cross-section thereof, and at least a sensing device, while pairing the first pattern with the third pattern and pairing the second pattern with the fourth pattern; (b) actuating the first wafer and the second wafer for enabling the first to parallel the second wafer and to be a distance apart from the second wafer; (c) actuating the first wafer and the second wafer for bringing the two wafers to move toward each other while enabling the sensing device for detecting and determining whether or not the first pattern is in a position capable of matching with the third pattern and the second pattern in another position capable of matchin

Abstract: An oxidation process is used to produce a positional reference structure on a semiconductor wafer. A photolithographic mask layer used to define the positional reference structure can be combined with a photolithographic mask layer used to define an active device layer on the wafer, whereby both patterns can be printed in a single photolithographic operation. The same oxidation process used to produce an isolating oxide between active device regions of the active device layer can also be used to produce the positional reference structure.

Abstract: A zero-order overlay target comprises a first zero-order line array fabricated on a first layer of a semiconductor structure, the first zero-order line array having a first pitch, and a second zero-order line array fabricated on a second layer of the semiconductor structure, the second zero-order line array having a second pitch. The second pitch may be different from the first pitch, and a portion of the second zero-order line array may be positioned to become optically coupled to a portion of the first zero-order line array when subject to an overlay measurement. Further, the second pitch may be variable. For example, the variable pitch may comprise a first set of features having a pitch approximately equal to the first pitch, a second set of features having a pitch different from the first pitch, and a third set of features having a pitch approximately equal to the first pitch.

Abstract: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

Abstract: A method of a semiconductor device comprises: a) depositing a first semiconductor layer and a second semiconductor layer in a semiconductor substrate in series; b) forming a first groove penetrating the first and second semiconductor layers and placed adjacent to an element region by partly etching the first and second semiconductor layers; c) forming a supporting member that supports the second semiconductor layer and covers over the second semiconductor layer and is embedded into the first groove; d) forming a second groove that exposes the first semiconductor layer from the bottom of the second semiconductor layer supported by the supporting member and is placed near the element region; and e) forming a cavity between the semiconductor substrate and the second semiconductor layer in the element region by etching the first semiconductor layer via the second groove under a specific condition in which the first semiconductor layer is easily etched, compared to the second semiconductor layer.

Abstract: A method of forming a pre-metal dielectric (PMD) layer of a semiconductor device using a chemical mechanical polishing (CMP) process which can be suitable for easily recognizing an alignment key. Such a method can reduce or otherwise eliminate alignment key erosion due to CMP by previously forming an alignment key pattern of polysilicon in an active region of a semiconductor scribe lane.

Abstract: A method for aligning multiple substrates. The method includes providing a handle substrate, providing a spacer substrate, and forming a plurality of first alignment marks on a first surface of the handle substrate. The method also includes forming a plurality of self-limiting alignment marks on a first surface of the spacer substrate and forming a plurality of openings in the spacer substrate, each of the plurality of openings surrounded by standoff regions. The method further includes aligning the first surface of the handle substrate and the first surface of the spacer substrate using the first alignment marks and the self-limiting alignment marks and bonding the handle substrate to the spacer substrate to form a composite substrate structure. In a specific embodiment, the plurality of self-limiting alignment marks and the plurality of openings are formed using an anisotropic wet etching process that preferentially etches the spacer substrate.

Abstract: A method for registering a pattern on a semiconductor wafer with an oxide surface includes etching into the surface four sets of two trenches each. Each trench in a set is parallel to the other. The trenches are configured such that each set forms one side of a box shape. The trenches are overfilled with a first metal layer, the excess of which is removed so that the height of the metal is level with the height of the oxide. An overlay setting is then obtained between a photoresist mask and the filled trenches before depositing a second metal layer over the oxide and trenches. The second metal layer is coated with the photoresist according to the overlay setting.

Abstract: A semiconductor device and a method for making the semiconductor device having a guard ring formed by a trench filled with a metallic material is described. Using the trench, crack and moisture propagation may be eliminated or prevented from propagating from a dicing area to an active circuit area of a chip.

Abstract: In an overlay metrology method used during semiconductor device fabrication, an overlay alignment mark facilitates alignment and/or measurement of alignment error of two layers on a semiconductor wafer structure, or different exposures on the same layer. A target is small enough to be positioned within the active area of a semiconductor device combined with appropriate measurement methods, which result in improved measurement accuracy.

Abstract: The present invention relates to positioning components of an assembly using fiducial features. A first fiducial feature on a first piece of the assembly can be located. A first component can be positioned on the first piece of the assembly based on the location of the first fiducial feature. A second fiducial feature on a second piece of the assembly can be located. The second component can be positioned relative to the second piece of the assembly based on the location of the second fiducial feature. The first piece can be positioned relative to the second piece based on the locations of the first and second fiducial features. The assembly can be an optical device. The first component can be an active optical device, the second component can be a lens, the first piece can be a package, and the second piece can be a lid.

Abstract: A low-power CMOS device can be fabricated by forming a shallow trench on a silicon substrate using a gate mask and negative photoresist. This enables an extremely low profile for a junction after completion of lightly doped drain and source/drain implantations. The method includes forming a shallow trench in a silicon substrate.

Abstract: Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.

Abstract: Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.

Abstract: A method of determining alignment error in electronic substrates comprises providing on a layer of a substrate a first contrasting set of elements forming a first grid pattern having a plurality of grid segments in the x and y directions. The method also includes providing nested within at least one of the first grid pattern segments, on the same or different layer of a substrate, a second contrasting set of elements forming a second grid pattern having a plurality of grid segments in the x and y directions. The method then includes determining the center of the first set of elements in the first grid pattern and determining the center of the second set of elements in the second grid pattern. The method then comprises comparing the centers of the first and second sets of elements and determining alignment error of the first and second grid patterns.

Abstract: The invention is directed to increasing the number of semiconductor dice obtained from one semiconductor wafer and enhancing the reliability and yield of the semiconductor dice when the semiconductor dice as products and TEG dice are formed on the semiconductor wafer. TEG die pattern regions are respectively placed on the top and bottom placing a plurality of semiconductor die pattern regions regularly arrayed in a longitudinal direction therebetween. The vertical length of each of the TEG die pattern regions is substantially half of the vertical length of the semiconductor die pattern region. With this reticle, two adjacent TEG die patterns respectively formed by two continuous exposure processes form the area of one semiconductor die pattern. In this manner, the area of the TEG die patterns on the semiconductor wafer is reduced and the yield of the semiconductor dice is increased correspondingly.

Abstract: A method for aligning multiple substrates. The method includes providing a handle substrate, providing a spacer substrate, and forming a plurality of first alignment marks on a first surface of the handle substrate. The method also includes forming a plurality of self-limiting alignment marks on a first surface of the spacer substrate and forming a plurality of openings in the spacer substrate, each of the plurality of openings surrounded by standoff regions. The method further includes aligning the first surface of the handle substrate and the first surface of the spacer substrate using the first alignment marks and the self-limiting alignment marks and bonding the handle substrate to the spacer substrate to form a composite substrate structure. In a specific embodiment, the plurality of self-limiting alignment marks and the plurality of openings are formed using an anisotropic wet etching process that preferentially etches the spacer substrate.

Abstract: A semiconductor memory device includes a substrate having first and second source/drain regions therein and a channel region therebetween. The device also includes first and second charge storage layers on the channel region, a first insulating layer on the channel region between the first and second charge storage layers, and a gate electrode on the insulating layer opposite the channel region and between inner sidewalls of the first and second charge storage layers. The gate electrode extends away from the substrate beyond the first and second charge storage layers. The device further includes second and third insulating layers extending from adjacent the inner sidewalls of the first and second charge storage layers along portions of the gate electrode beyond the first and second charge storage layers. Related methods of fabrication are also discussed.

Abstract: A method (and apparatus) of replicating a pattern on a structure, includes using imprint lithography to replicate a pattern formed on a first structure onto a portion of a second structure.

Abstract: The intensity of light of a predetermined wavelength corresponding to the type of a protective tape joined to the surface of a semiconductor wafer is adjusted by a controller, and a holding stage for holding the semiconductor wafer is scanned rotationally. At this time, at a V notch portion for positioning formed in the semiconductor wafer, light is transmitted through the protective sheet covering the surface, which is received by a photoreception sensor. Based on the change in the reception amount of light in the photoreception sensor, the position of a detection site is specified.

Abstract: In a method for manufacturing a semiconductor device having an alignment mark, a buffer layer is formed on a substrate. A trench is formed at an isolation region of the substrate. The trench is filled with an insulating layer. An alignment groove is formed on the insulating layer in a scribe lane region of the substrate. The buffer layer is removed to form an alignment pattern. An alignment mark includes the alignment pattern and the alignment groove. Therefore, the alignment pattern may be not attacked by solutions in a successive cleaning process such that the alignment mark may be not damaged and maintains its original shape.

Abstract: A method for a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior art fiducials and pin one indicators. Methods of fabricating a carrier substrate and fabricating a semiconductor device package using the combination pin one indicator and alignment fiducial are also described.

Abstract: A semiconductor integrated circuit is fabricated in a substrate having a semiconductor layer and an underlying insulator layer. The fabrication process includes a step of locally oxidizing the semiconductor layer to form a field oxide, during which step the semiconductor layer is protected by a nitride film. The nitride film has both openings to permit local oxidization in the integrated circuit area, and an opening defining an alignment mark adjacent to the circuit area. The alignment mark may be formed either in the semiconductor and insulator layers, or in a part of the nitride film left after the nitride film is removed from the circuit area. In either case, the edge height of the alignment mark is not limited by the thickness of the semiconductor layer. Using the nitride layer to define both the alignment mark and the field oxide reduces the necessary number of fabrication steps.

Abstract: A semiconductor-device manufacturing method includes forming an element separating insulating film on a semiconductor substrate; forming a gate multilayer film for forming a gate electrode thereon; removing the gate multilayer film in an alignment mark forming area positioned on the element separating insulating film; forming a pattern of a first conductive film in the element forming area; forming an alignment mark of the first conductive film, used in photolithography, in the alignment mark forming area surrounded by the gate multilayer film; forming an inter-layer insulating film thereon; removing the inter-layer insulating film in the alignment mark forming area, so that it remains on the gate multilayer film around the alignment mark forming area; removing or thinning the element separating insulating film around the alignment mark; and forming a pattern of a second conductive film on the inter-layer insulating film by performing alignment of the photolithography by using the alignment mark.

Abstract: A marker structure on a substrate for optical alignment of the substrate includes a plurality of first structural elements and a plurality of second structural elements. In use, the marker structure allows the optical alignment based upon providing at least one light beam directed on the marker structure, detecting light received from the marker structure at a sensor, and determining alignment information from the detected light, the alignment information comprising information relating a position of the substrate to the sensor.

Abstract: An integrated circuit capable of operating despite a profile shift is disclosed. Overlay marks on the integrated circuit are surrounded by a trench that tends to relieve the effect of a profile shift caused by stress applied to the integrated circuit. The position of the overlay marks tends, therefore, not to be affected by the stress.