Abstract: An alignment target with geometry designs provides a desired alignment offset for processes (both symmetric and asymmetric) on a wafer substrate. The alignment target includes one or more sub-targets, where each sub-target is defined as having a left portion and a right portion having a different geometric pattern, and where the left portion has a geometry density and the right portion has a geometry density.

Abstract: A semiconductor-device manufacturing method includes forming an element separating insulating film on a semiconductor substrate; forming a gate multilayer film for forming a gate electrode thereon; removing the gate multilayer film in an alignment mark forming area positioned on the element separating insulating film; forming a pattern of a first conductive film in the element forming area; forming an alignment mark of the first conductive film, used in photolithography, in the alignment mark forming area surrounded by the gate multilayer film; forming an inter-layer insulating film thereon; removing the inter-layer insulating film in the alignment mark forming area, so that it remains on the gate multilayer film around the alignment mark forming area; removing or thinning the element separating insulating film around the alignment mark; and forming a pattern of a second conductive film on the inter-layer insulating film by performing alignment of the photolithography by using the alignment mark.

Abstract: A method of manufacturing a thin film transistor array panel is provided, which includes: forming a semiconductor layer of polysilicon on an insulating substrate; forming a gate insulating layer on the semiconductor layer; forming a gate electrode on the gate insulating layer; forming a source region and a drain region by doping conductive impurities in the semiconductor layer; forming an interlayer insulating layer covering the gate electrode; forming a source electrode and a drain electrode respectively connected to the source and the drain regions; forming a passivation layer covering the source and the drain electrodes; forming a pixel electrode connected to the drain electrode; and forming a first alignment key when forming one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode, wherein one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode is at least formed by photol

Abstract: A semiconductor chip comprises a silicon substrate on which semiconductor elements are formed, pads, each of which is formed on the silicon substrate and electrically connected to at least one of the semiconductor elements, a first insulating layer having an opening over each one of the pads, a first wiring layer formed on the first insulating layer, electrically connected to the pads and having connecting parts, a second insulating layer formed on the first wiring layer and having openings over the connecting parts of the first wiring layer, electrically functioning solder bumps, each of which is formed on one of the openings of the second insulating layer with electrically connecting to one of the pads via the first wiring layer, and dummy bumps for self adjustment, each of which is formed on one of the openings of the second insulating layer without electrically connecting to the pad.

Abstract: An integrated circuit system comprising: providing a substrate; forming a main feature using a first non-cross-junction assist feature over the substrate; forming the main feature using a second non-cross-junction assist feature, adjacent a location of the first non-cross-junction feature, over the substrate; and forming an integrated circuit having the substrate with the main feature thereover.

Abstract: A flexible insulating base, a plurality of conductor wirings aligned on the flexible insulating base, and bump electrodes provided respectively in end portions of the plurality of conductor wirings in a region where a semiconductor chip is to be placed are provided. The semiconductor chip is mounted on the conductor wirings by bonding electrode pads formed on the semiconductor chip to the bump electrodes. An auxiliary conductor wiring formed similarly to the conductor wirings is provided on the insulating base, and an auxiliary bump electrode formed similarly to the bump electrodes is provided on the auxiliary conductor wiring, so that the electrode pads formed on the semiconductor chip can be registered with respect to the bump electrodes on the conductor wirings by positioning the semiconductor chip with reference to the auxiliary bump electrode.

Abstract: Methods and apparatuses are provided for improving the intensity profile of a beam image used to process a semiconductor substrate. At least one photonic beam may be generated and manipulated to form an image having an intensity profile with an extended uniform region useful for thermally processing the surface of the substrate. The image may be scanned across the surface to heat at least a portion of the substrate surface to achieve a desired temperature within a predetermined dwell time. Such processing may achieve a high efficiency due to the large proportion of energy contained in the uniform portion of the beam.

Abstract: A test key for checking an interconnect structure is described, including a contiguous metal line and multiple conductive plugs on the contiguous metal line, wherein one end of each plug contacts with the contiguous metal line. The other end of at least one plug is not connected to any conductor. In addition, the two ends of the contiguous metal line are connected to different voltages.

Abstract: In a method for forming a fine pattern of a semiconductor device, forming a spacer for double patterning of a cell region is performed separate from forming a mask pattern that defines a dummy pattern for a pad of a peripheral circuit region.

Abstract: A semiconductor device includes a semiconductor chip, a moisture resistant ring provided in the semiconductor chip and having a chamfered flat part in a position corresponding to a corner of the semiconductor chip, and a first monitor pattern formed inside the moisture resistant ring. At least a part of the first monitor pattern is disposed inside an n-sided polygonal area (n is a natural number which is 4 or higher than 4) situated within the moisture resistant ring, and outside a quadrangular area situated inside the n-sided polygonal area. The n-sided polygonal area has a vertex at least at each of a first end and a second end of the chamfered flat part, and the quadrangular area has a vertex at least at a middle point of the chamfered flat part.

Abstract: A method for forming an image sensor device. An alignment mark is formed on or in a substrate with distance from the alignment mark to the substrate edge less than about 3 mm. An array of active photosensing pixels is formed on the substrate. At least one dielectric layer is formed covering the substrate and the array. A color filter photoresist is formed on the least one dielectric layer. Subsequent to removal of the color filter photoresist from the alignment mark, the color filter photoresist is exposed with alignment to the alignment mark.

Abstract: A method for implementing alignment of a semiconductor device structure includes forming first and second sets of alignment marks within a lower level of the structure, the second set of alignment marks adjacent the first set of alignment marks. An opaque layer is formed over the lower level, including the first and second sets of alignment marks. A portion of the opaque layer corresponding to the location of said first set of alignment marks is opened so as to render the first set optically visible while the second set of alignment marks initially remains covered by the opaque layer. The opaque layer is patterned using the optically visible first set of alignment marks, wherein the second set of alignment marks remain available for subsequent alignment operations in the event the first set becomes damaged during patterning of the opaque layer.

Abstract: The present invention provides a method for manufacturing a semiconductor substrate in which a semiconductor wafer, formed of a material less likely to increase the hole diameter, is processed to a semiconductor substrate actually applicable to an existing manufacture line. An SiC wafer 12 is temporarily fixed to a Si wafer 18 through a wax 20. The SiC wafer 12 temporarily fixed to the Si wafer 18 is overlapped with a Si wafer 14 having the same hole diameter as the Si wafer 18 through an SOG film 16P. Orientation flats 14A and 18A are aligned, and while the Si wafers 14 and 18 are overlapped with each other, heating is performed under pressure to solidify the SOG film 16P, whereby an SOG solidified film 16S is formed. With the aid of the SOG solidified film 16S, the SiC wafer 12 is adhered to the Si wafer 14. The SiC wafer 12 is adhered at a predetermined position of the Si wafer 14 facing the SiC wafer 12 so as to be transferred from the Si wafer 18 to the Si wafer 14.

Abstract: A substrate provided with an alignment mark in a substantially transmissive process layer overlying the substrate, said mark comprising high reflectance areas for reflecting radiation of an alignment beam of radiation, and low reflectance areas for reflecting less radiation of the alignment beam, wherein the high reflectance areas comprise at least one substantially linear sub-grating. In one example, a substantially linear sub-grating comprises a plurality of spaced square regions.

Abstract: A method is provided for forming plural kinds of wells on a single semiconductor substrate with an improved alignment accuracy and obviating the generation of step height between the wells. The method includes forming a selective etching film on the semiconductor substrate, forming openings on the selective etching film overlying a first well forming region and an alignment mark forming region using a first resist film as a mask for defining the first well forming region and the alignment mark forming region, implanting the first well forming region with a dopant of a first conductivity type and removing the first resist film, forming a second resist film to mask at least the first well forming region, having an opening overlying the alignment mark forming region larger than the opening of the selective etching film overlying the same region, and forming the alignment mark by performing an etching process using the second resist film and selective etching film as a mask.

Abstract: A method for manufacturing a semiconductor device capable of eliminating additional processes for forming an alignment key, thereby shortening the manufacturing process and lowering the manufacturing costs.

Abstract: A method for wafer backside alignment overlay accuracy includes forming a buried layer on a front-side of a wafer; forming a conductive layer on the buried layer and patterning a first test structure and a second test structure therein; forming an etch stop layer on the conductive layer; etching through the wafer from the backside to perform an alignment process with the first test structure; and determining an overlay accuracy of the alignment process with the second test structure. The first test structure includes an optical vernier and the second test structure includes an electrical testing structure.

Abstract: A method that includes providing a semiconductor substrate having a mask on a surface thereof. The mask includes a first region having no masking elements and a second region having a plurality of masking elements. Each of the plurality of masking elements has a dimension that is equal to a first length, the first length less than twice a diffusion length of a dopant. The method further includes bombarding the semiconductor substrate and masking element with ions of the dopant. The ions form a first impurity concentration in the first region and a second impurity concentration in the second region.

Abstract: A method of measuring warpage of a rear surface of a substrate includes a substrate detection step, a best fit plane calculation step, and a warpage calculation step. Further, the method of measuring warpage of a rear surface of a substrate can further includes after the substrate detection step and before the best fit plane calculation step: a noise removal step and an outer peripheral portion removal step; the outer peripheral portion removal step and a smoothing step; or the noise removal step, the outer peripheral portion removal step, and the smoothing step. Thereby, a method of measuring warpage of a rear surface with a high surface roughness of a substrate can be provided.

Abstract: A method of indexing a plurality of dice obtained from a material wafer comprising a plurality of stacked material layers, each die being obtained in a respective die position in the wafer, the method including providing a visible index on each die indicative of the respective die position, wherein providing the visible index on each die includes: forming in a first material layer of the die a reference structure adapted to defining a mapping of the wafer; and forming in a second material layer of the die a marker associated with the reference structure, a position of the marker with respect to the reference structure being adapted to provide an indication of the die position in the wafer.

Abstract: A plurality of IC regions are formed on a semiconductor wafer, which is cut into individual chips incorporating ICs, wherein wiring layers and insulating layers are sequentially formed on a silicon substrate. In order to reduce height differences between ICs and scribing lines, a planar insulating layer is formed to cover the overall surface with respect to ICs, seal rings, and scribing lines. In order to avoid occurrence of breaks and failures in ICs, openings are formed to partially etch insulating layers in a step-like manner so that walls thereof are each slanted by prescribed angles ranging from 20° to 80°. For example, a first opening is formed with respect to a thin-film element section, and a second opening is formed with respect to an external-terminal connection pad.

Abstract: A method of making at least one marker (MX) for double gate SOI processing on a SOI wafer is disclosed. The marker has a diffracting structure in a first direction and the diffracting structure is configured to generate an asymmetrical diffraction pattern during use in an alignment and overlay detection system for detection in the first direction.

Abstract: Many holes are formed in an interlayer insulating film and the surface of the interlayer insulating film is covered with a metal film, with its surface undulated by openings or recesses formed to scatter reflection light. The size of the recesses is about the size of contact holes of elements. Hence the recesses are not detectable by an image recognition apparatus. The size of the metal film, however, is set so that it can be detected by the image recognition apparatus.

Abstract: The object of the present invention is providing an alignment error measuring mark for an accurate alignment in a metal photolithography process. A substrate reference mark 110 is produced by forming a concavity by an erosion caused from a chemical mechanical polishing a tungsten on a surface of a interlayer film 132 after holes for substrate reference mark 111 is formed on the interlayer film 132 at a predetermined density and the tungsten is deposited in the holes for substrate reference mark 111 and on the interlayer film 132. A resist reference mark is formed on a resist film 134 on the substrate reference mark 110 and in a shape of a rectangular shape having a different size from the one of the substrate reference mark 110. Since the substrate reference mark 110 is formed by the concavity from the erosion, a position of an edge 133a of the concavity of a alminum film 133 can be aligned to a position of an edge 110a of the concavity of the substrate reference mark 110.

Abstract: A semiconductor device includes a pad electrode layer and an align mark layer, formed on the semiconductor substrate. A passivation layer is formed on the semiconductor substrate and exposes at least a portion of the top of the pad electrode layer and at least a portion of the top of the align mark layer. A light-transmitting protecting layer covers at least a portion of the passivation layer, exposes the top portion of the pad electrode layer exposed from the passivation layer, and covers the portion of the align mark layer exposed from the passivation layer.

Abstract: A method of manufacturing a semiconductor device, includes forming a structure wherein a first alignment mark is provided in a first alignment-mark arrangement area of a first layer, a second alignment mark is provided in a second alignment-mark arrangement area of a second layer, a dummy pattern is provided above the first alignment-mark arrangement area, and substantially no dummy pattern is provided above the second alignment-mark arrangement area, and aligning a third layer provided above the structure by using the second alignment mark.

Abstract: A method for manufacturing a display substrate is disclosed, which includes the following steps: providing a substrate; forming a plurality of bumps on an active area of the substrate and at least one marking pattern on a non-active area of the substrate; and staining the marking pattern or filling a material having low transmittance ratio into the marking pattern. The present invention further discloses a method for making a display substrate, including the steps: providing a substrate; forming a shadow layer on a non-active area of the substrate; forming a plurality of bumps on an active area of the substrate and at least one marking pattern on the shadow layer of the non-active area on the substrate; and removing a part of the shadow layer not covered by the marking pattern.

Abstract: In a method of fabricating a semiconductor device having an alignment key and a semiconductor device fabricated thereby. The method of fabricating a semiconductor device includes providing a semiconductor substrate having a scribe lane region and a cell region. An etch barrier pattern and a gate pattern are formed on the scribe lane region and the cell region respectively. A first interlayer insulating layer is formed to cover the etch barrier pattern and the gate pattern. A preliminary alignment key pattern and a bit line pattern are formed on the first interlayer insulating layer of the scribe lane region and the cell region respectively. A second interlayer insulating layer is formed to cover the preliminary alignment key pattern and the bit line pattern.

Abstract: Provided are an alignment key, a method for fabricating the alignment key, and a method for fabricating a thin film transistor substrate using the alignment key. The method for fabricating the alignment key includes forming a first metal layer on a base substrate, forming a first alignment key and a first mark portion of a second alignment key by selectively patterning the first metal layer, forming a dielectric on the first metal layer, forming a second metal layer on the dielectric, and forming a second mark portion of the second alignment key on the dielectric by selectively patterning the second metal layer.

Abstract: A method of enabling alignment of a wafer in at least one exposure step of an integrated circuit process after a UV-blocking metal layer is formed over the whole wafer covering a patterned upmost metal layer of the integrated circuit is described, wherein the wafer has an edge portion where a composite dielectric layer corresponding to the dielectric layers of the integrated circuit is formed. The method includes forming a cavity in the composite dielectric layer over the edge portion of the wafer in the patterning process of the upmost metal layer, such that an alignment mark is formed after the UV-blocking metal layer is formed.

Abstract: The formation of an alignment key for overlay measurement of a semiconductor device formed by sequentially forming an inter-metal dielectric layer and a capping layer over a semiconductor substrate, and patterning the inter-metal dielectric layer and a capping layer at an alignment key region to thereby form an alignment key hole. A metal layer may then be deposited over the semiconductor substrate including alignment key hole and then an uppermost surface of the deposited metal layer may then be polished to thereby form the alignment key having a step. Accordingly, a dishing phenomenon occurring at the time of polishing using a capping layer can be prevented and an alignment key having a desired step can be formed.

Abstract: An integrated circuit device includes a storage cell including an upper electrode and a lower electrode on a substrate, and a conductive hard mask pattern directly on the upper electrode of the storage cell opposite the lower electrode. The upper electrode is formed of a metal softer than the conductive hard mask pattern. The device further includes an interlayer on the substrate having an alignment key recess therein. The alignment key recess extends towards the substrate beyond a depth of the upper electrode. An alignment key pattern may extend towards the substrate beyond the depth of the upper electrode on opposing sidewalls and on a surface therebetween of the alignment key recess. The alignment key pattern may have a distinct step difference between portions thereof on the opposing sidewalls and portions thereof on the surface therebetween. Related methods are also discussed.

Abstract: Manufacturing a semiconductor device by removing the insulation film in an alignment mark-forming region, depositing a first semiconductor layer, removing the insulation film on the semiconductor substrate after the second semiconductor layer is formed, forming a first exposing region for exposing the semiconductor substrate through the second semiconductor layer and the first semiconductor layer with reference to the second semiconductor layer in the alignment mark-forming region as a first alignment mark for positioning, while forming, on the semiconductor substrate, a second alignment mark, forming a second exposing region for exposing the first semiconductor layer by using the second alignment mark as a reference for positioning, forming a cavity and forming a buried insulation layer in the cavity, and forming a first grate electrode by using the second alignment mark as a reference for positioning.

Abstract: A substrate provided with an alignment mark in a substantially transmissive process layer overlying the substrate, said mark comprising high reflectance areas for reflecting radiation of an alignment beam of radiation, and low reflectance areas for reflecting less radiation of the alignment beam, wherein the high reflectance areas comprise at least one substantially linear sub-grating. In one example, a substantially linear sub-grating comprises a plurality of spaced square regions.

Abstract: A laser mark which will be the positioning mark for a secondary charged particle image in the charged particle beam apparatus is applied by moving the sample processing/observation area in the charged particle beam apparatus so as to come into the view field while performing an observation by an infrared microscope, and by a using a laser optical system disposed coaxially with an optical observation system, the mark made at the periphery of the processing/observation object area. Next, by a superposition of an infrared transmission image and a CAD data, the processing/observation object area and the laser mark are registered onto the CAD data. And, by a correlation of the registered data read from the charged particle beam apparatus and the secondary charged particle image, it is possible to accurately and easily determine the processing position.

Abstract: The invention is directed to an improvement of cutting accuracy in a cutting process when a semiconductor device attached with a supporting member is manufactured. The invention provides a manufacturing method of a semiconductor device where a semiconductor wafer attached with a glass substrate is cut with moving a rotation blade along a dicing region and has following features. A pair of alignment marks is formed facing each other over the dicing region on the semiconductor wafer. Then, when the rotation blade is to be aligned on a center of the dicing region, that is, on a centerline thereof in the cutting process, positions of the alignment marks are detected by a recognition camera, the centerline is calculated based on the detection result, and the rotation blade is aligned on the centerline to perform cutting.

Abstract: A method including forming alignment marks in an upper surface of a semiconductor wafer; selectively depositing a mask over the alignment marks leaving portions of the upper surface exposed; depositing an epitaxial layer over the exposed portions of the upper surface; and thereafter removing the mask.

Abstract: Provided are an alignment mark with a higher rate of recognition, a semiconductor chip including the alignment mark, a semiconductor package including the semiconductor chip, and methods of fabricating the alignment mark, the semiconductor chip, and the semiconductor package. The alignment mark may include an align metal pad on a substrate and may be electrically isolated. A protective film may be on the align metal pad and may include an aperture exposing a part of the align metal pad. A metal alignment bump may be on the align metal pad exposed in the aperture such that the metal alignment bump protrudes above the protective film.

Abstract: Methods and systems of enhancing stepper alignment signals and metrology alignment target signals. In one embodiment, a plurality of alternating rows comprising a first material of a first height and a second material of a second height are constructed. The first material and the second material are selected to enhance the contrast of the mark when imaged for alignment of photolithographic structures.

Abstract: Pattern registration marks which include: a substrate and an upper material layer disposed above the substrate; an outer trench formed in the upper material layer, the outer trench having an outer trench width; an inner trench formed in the upper material layer, the inner trench having an inner trench width; and a conformal layer disposed in the inner trench and the outer trench, the conformal layer having a conformal layer thickness; wherein the outer trench width is greater than twice the conformal layer thickness, and wherein the inner trench width is less than or equal to twice the conformal layer thickness; and methods of using the same.

Abstract: The invention relates to an apparatus for imprinting and/or embossing substrates (7), in particular semiconductor substrates or wafers, having: a receiving unit (5) for receiving the substrate (7) in a working space (13), an adjusting device (2, 3, 4) for adjusting the substrate (7) in relation to an embossing and/or printing punch (10), whereby for a process that is as contamination-free as possible and for a manufacture of the apparatus that is as favourable as possible the receiving unit (5) is designed so as to separate the working space (13) from the environment.

Abstract: A process for fabricating a circuit board with embedded passive component is provided. A conductive layer including a first surface and a second surface opposing to the first surface is provided. The conductive layer has first through holes passing through the conductive layer, respectively. At least one passive component material layer is formed on the first surface. A circuit unit including second through holes is provided. Locations of the second through holes are corresponding to the locations of the first through holes, respectively. The conductive layer and the circuit unit are aligned by the first through holes and the second through holes, while the first surface of the conductive layer faces the circuit unit, and the passive component material layer is between the circuit unit and the conductive layer. The conductive layer is laminated to the circuit unit. The conductive layer is patterning to form a circuit layer.

Abstract: A method of forming alignment marks on edge chips in a kerf region of a semiconductor workpiece. The alignment marks are formed in at least one material layer of the semiconductor device. The alignment marks are formed using a separate lithography mask, and may extend into lower layers, including the workpiece, of the semiconductor device. An opaque material layer is deposited, and depressions are formed in the opaque layer over the deep alignment mark trenches. The depressions in the opaque material layer are used to align a lithography process to open the opaque material layer over alignment marks in an underlying metallization layer. The alignment marks in the metallization layer are then used to align the lithography process used to pattern the opaque material layer.

Abstract: Substrate shrinkage that occurs during manufacture of an electronic assembly is compensated for by the incorporation of a horizontal line, having a plurality of vertical graduations, across a horizontal portion of a substrate and a vertical line, having a plurality of horizontal graduations, across a vertical portion of the substrate. The substrate is then cured and an amount of substrate shrinkage is determined, based upon a location change in the graduations of the horizontal and vertical lines. In this manner, solder can be properly provided on solder pads of the substrate responsive to the amount of substrate shrinkage. As such, electronic components can be properly mounted to the solder pads of the substrate.

Abstract: The present invention relates to overlay marks and methods for determining overlay error. One aspect of the present invention relates to a continuously varying offset mark. The continuously varying offset mark is a single mark that includes over laid periodic structures, which have offsets that vary as a function of position. By way of example, the periodic structures may correspond to gratings with different values of a grating characteristic such as pitch. Another aspect of the present invention relates to methods for determining overlay error from the continuously varying offset mark. The method generally includes determining the center of symmetry of the continuously varying offset mark and comparing it to the geometric center of the mark. If there is zero overlay, the center of symmetry tends to coincide with the geometric center of the mark. If overlay is non zero (e.g., misalignment between two layers), the center of symmetry is displaced from the geometric center of the mark.

Abstract: Methods and systems produce flattening layers associated with nitrogen-containing quantum wells and prevent 3-D growth of nitrogen containing layers using controlled group V fluxes and temperatures. MEE (Migration Enhanced Epitaxy) is used to form a flattening layer upon which a quantum well is formed and thereby enhance smoothness of quantum well interfaces and to achieve narrowing of the spectrum of light emitted from nitrogen containing quantum wells. MEE is performed by alternately depositing single atomic layers of group III and V materials at a given group V flux and then raising the group V flux to saturate the surface of the flattening layer with the group V material. A cap layer is also formed over the quantum well. Where nitrogen is used, the systems incorporate a mechanical means of preventing nitrogen from entering the MBE processing chamber, such as a gate valve.

Abstract: In a semiconductor device including a monocrystalline thin film transistor 16a that has been formed on a monocrystalline Si wafer 100 and then is transferred to a insulating substrate 2, LOCOS oxidization is performed with respect to the element-isolation region of the monocrystalline Si wafer 100 so as to create a field oxide film (SiO2 film) 104, and a marker 107 is formed on the field oxide film 104. With this structure, alignment of components may be performed based on a gate electrode 106 upon or after the transfer step.

Abstract: The present invention provides a method for manufacturing a semiconductor device having an alignment feature. The method for manufacturing the semiconductor device, among other steps, may include implanting an n-type dopant into a substrate thereby forming an implanted region and an unimplanted region in the substrate. The method may further include oxidizing the substrate using a wet oxidation process, the wet oxidation process and n-type dopant causing a ratio of oxidation of the implanted region to the unimplanted region to be 2:1 or greater, and then removing the oxidized portions of the substrate thereby leaving an alignment feature proximate the implanted region.

Abstract: A semiconductor device includes a first surface faced to a mounting board when the semiconductor device is placed over the mounting board and a second surface opposed to the first surface. The semiconductor device also includes a position reference portion which is provided in an area including sides of the second surface and which has an optical reflection factor different from that of the mounting board.

Abstract: An apparatus and method performing a sequence of processing steps on a load supported by a processing plate. The load can include a single sheet on which a plurality of applications are performed or can include a plurality of panels on which respective applications are performed. For each application, at least one coarse target and at least one panel target are used to adjust the programmed coordinates for that application. After the first application of the load is processed using the coarse and panel targets, coarse and panel targets are located for the second application. Using the alignment provided by these targets, the second application is processed. Each subsequent application is similarly aligned and processed.