And Separate Partially Isolated Semiconductor Regions Patents (Class 438/405)
  • Patent number: 9799588
    Abstract: A chip package and a fabrication method thereof are provided according to an embodiment of the invention. The chip package includes a semiconductor substrate containing a chip and having a device area and a peripheral bonding pad area. A plurality of conductive pads is disposed at the peripheral bonding pad area and a passivation layer is formed over the semiconductor substrate to expose the conductive pads. An insulating protective layer is formed on the passivation layer at the device area. A packaging layer is disposed over the insulating protective layer to expose the conductive pads and the passivation layer at the peripheral bonding pad area. The method includes forming an insulating protective layer to cover a plurality of conductive pads during a cutting process and removing the insulating protective layer on the conductive pads through an opening of a packaging layer.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: October 24, 2017
    Assignee: XINTEC INC.
    Inventors: Ching-Yu Ni, Chia-Ming Cheng, Nan-Chun Lin
  • Patent number: 9490250
    Abstract: A half-bridge circuit includes a low-side transistor and a high-side transistor each having a load path and a control terminal. The half-bridge circuit further includes a high-side drive circuit having a level shifter with a level shifter transistor. The low-side transistor and the level shifter transistor are integrated in a common semiconductor body.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: November 8, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Franz Hirler, Joachim Weyers, Uwe Wahl
  • Patent number: 9129815
    Abstract: Provided is a semiconductor device comprising a substrate including a first area and a second area, first through third crystalline layers sequentially stacked on the first area and having first through third lattice constants, respectively, a first gate electrode formed on the third crystalline layer, fourth and fifth crystalline layers sequentially stacked on the second area and having fourth and fifth lattice constants, respectively, and a second gate electrode formed on the fifth crystalline layer, wherein the third lattice constant is greater than the second lattice constant, the second lattice constant is greater than the first lattice constant, and the fifth lattice constant is smaller than the fourth lattice constant.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: September 8, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Gil Yang, Sang-Su Kim, Chang-Jae Yang
  • Patent number: 9087707
    Abstract: A semiconductor arrangement includes a semiconductor body and a power transistor including a source region, a drain region, a body region and a drift region arranged in the semiconductor body, a gate electrode arranged adjacent to the body region and dielectrically insulated from the body region by a gate dielectric. The semiconductor arrangement further includes a high voltage device arranged within a well-like dielectric structure in the semiconductor body and comprising a further drift region.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: July 21, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Franz Hirler, Joachim Weyers, Uwe Wahl
  • Patent number: 9082627
    Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: July 14, 2015
    Assignee: ZIPTRONIX, INC.
    Inventors: Qin-Yi Tong, Gaius Gillman Fountain, Jr., Paul M. Enquist
  • Patent number: 8951850
    Abstract: A method for semiconductor fabrication includes patterning one or more mandrels over a semiconductor substrate, the one or more mandrels having dielectric material formed therebetween. A semiconductor layer is formed over exposed portions of the one or more mandrels. A thermal oxidation is performed to diffuse elements from the semiconductor layer into an upper portion of the one or more mandrels and concurrently oxidize a lower portion of the one or more mandrels to form the one or more mandrels on the dielectric material.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: February 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
  • Patent number: 8927406
    Abstract: A method for fabricating a dual damascene metal gate includes forming a dummy gate onto a substrate, disposing a protective layer on the substrate and the dummy gate, and growing an expanding layer on sides of the dummy gate. The method further includes removing the protective layer, forming a spacer around the dummy gate, and depositing and planarizing a dielectric layer. The method further includes selectively removing the expanding layer, and removing the dummy gate.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: January 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Wang, Wen-Chu Hsiao, Ying-Min Chou, Hsiang-Hsiang Ko
  • Publication number: 20140377935
    Abstract: Provided is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and a method for the structure's fabrication. The structure comprises a gate situated on the top semiconductor layer, the top semiconductor layer situated over a base oxide layer, and the base oxide layer situated over a handle wafer. The top surface of the handle wafer is amorphized by an inert implant of Xenon or Argon to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer.
    Type: Application
    Filed: September 5, 2014
    Publication date: December 25, 2014
    Inventors: Paul D. Hurwitz, Robert L. Zwingman
  • Patent number: 8916428
    Abstract: A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming spacers adjoining sidewalls of the gate stacks, wherein at least one of the spacers extends beyond an edge the isolation feature. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: December 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsan-Chun Wang, Chun Hsiung Tsai
  • Patent number: 8895956
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type first semiconductor layer, a p-type second semiconductor layer and a light emitting layer. The light emitting layer is provided between the first and second semiconductor layers, and includes a plurality of barrier layers including a nitride semiconductor and a well layer provided between the barrier layers and including a nitride semiconductor containing In. The barrier layers and the well layer are stacked in a first direction from the second semiconductor layer toward the first semiconductor layer. The well layer has a p-side interface part and an n-side interface part. Each of the p-side and the n-side interface part include an interface with one of the barrier layers. A variation in a concentration of In in a surface perpendicular to the first direction of the p-side interface part is not more than that of the n-side interface part.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: November 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeya Kimura, Koichi Tachibana, Hajime Nago, Shinya Nunoue
  • Patent number: 8741734
    Abstract: A semiconductor device includes a semiconductor substrate having a trench defining an active region. A wall oxide is formed on side walls of the active region extending in the longitudinal direction, and an element isolation layer is formed in the trenches. A method of manufacturing a semiconductor device includes forming line-shape first trenches on a semiconductor substrate so as to define an active region; forming a wall oxide on surfaces of the first trenches; forming a second trench which separates the active region into a plurality of active regions; and filling the trenches with an element isolation layer.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: June 3, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Bum Kim
  • Patent number: 8679903
    Abstract: A method is provided for fabricating a vertical insulated gate transistor. A horizontal isolation region is formed in a substrate to separate and electrically isolate upper and lower portions of the substrate. A vertical semiconductor pillar with one or more flanks and a cavity is formed so as to rest on the upper portion, and a dielectrically isolated gate is formed so as to include an internal portion within the cavity and an external portion resting on the flanks and on the upper portion. One or more internal walls of the cavity are coated with an isolating layer and the cavity is filled with a gate material so as to form the internal portion of the gate within the cavity and the external portion of the gate that rests on the flanks, and to form two connecting semiconductor regions extending between source and drain regions of the transistor.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: March 25, 2014
    Assignee: STMicroelectronics, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 8673732
    Abstract: Method is to fabricate a MEMS device with a substrate. The substrate has through holes in the substrate within a diaphragm region and optionally an indent space from the second surface at the diaphragm region. A first dielectric structural layer is then disposed over the substrate from the first surface, wherein the first dielectric structural layer has a plurality of openings corresponding to the through holes, wherein each of the through holes remains exposed by the first dielectric structural layer. A second dielectric structural layer with a chamber is disposed over the first dielectric structural layer, wherein the chamber exposes the openings of the first dielectric structural layer and the through holes of the substrate to connect to the indent space. A MEMS diaphragm is embedded in the second dielectric structural layer above the chamber, wherein an air gap is formed between the substrate and the MEMS diaphragm.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: March 18, 2014
    Assignee: Solid State System Co., Ltd.
    Inventors: Tsung-Min Hsieh, Chien-Hsing Lee, Jhyy-Cheng Liou
  • Patent number: 8652887
    Abstract: The present invention relates to a method for providing a Silicon-On-Insulator (SOI) stack that includes a substrate layer, a first oxide layer on the substrate layer and a silicon layer on the first oxide layer (BOX layer). The method includes providing at least one first region of the SOI stack wherein the silicon layer is thinned by thermally oxidizing a part of the silicon layer and providing at least one second region of the SOI stack wherein the first oxide layer (BOX layer) is thinned by annealing.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: February 18, 2014
    Assignee: Soitec
    Inventors: Bich-Yen Nguyen, Carlos Mazure, Richard Ferrant
  • Patent number: 8647935
    Abstract: A method patterns at least one pair of openings through a protective layer and into a substrate. The openings are positioned on opposite sides of a channel region of the substrate. The method forms sidewall spacers along the sidewalls of the openings and removes additional substrate material from the bottom of the openings. The material removal process creates an extended bottom within the openings. The method forms a first strain producing material within the extended bottom of the openings. The method removes the sidewall spacers and forms a second material within the remainder of the openings between the first strain producing material and the top of the openings. The method removes the protective layer and forms a gate dielectric and a gate conductor on the horizontal surface on the substrate adjacent the channel region. The second material comprises source and drain regions.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak, Andreas Scholze
  • Patent number: 8587025
    Abstract: A method for forming a laterally varying n-type doping concentration is provided. The method includes providing a semiconductor wafer with a first surface, a second surface arranged opposite to the first surface and a first n-type semiconductor layer having a first maximum doping concentration, implanting protons of a first maximum energy into the first n-type semiconductor layer, and locally treating the second surface with a masked hydrogen plasma. Further, a semiconductor device is provided.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: November 19, 2013
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina
  • Patent number: 8575040
    Abstract: Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane material to a silicon oxide layer.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: November 5, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Janos Fucsko, John A. Smythe, III, Li Li, Grady S. Waldo
  • Patent number: 8324071
    Abstract: A method for forming a silicon film may be performed using a microheater including a substrate and a metal pattern spaced apart from the substrate. The silicon film may be formed on the metal pattern by applying a voltage to the metal pattern of the microheater to heat the metal pattern and by exposing the microheater to a source gas containing silicon. The silicon film may be made of polycrystalline silicon. A method for forming a pn junction may be performed using a microheater including a substrate, a conductive layer on the substrate, and a metal pattern spaced apart from the substrate. The pn junction may be formed between the metal pattern and the conductive layer by applying a voltage to the metal pattern of the microheater to heat the metal pattern. The pn junction may be made of polycrystalline silicon.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: December 4, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junhee Choi, Andrei Zoulkarneev
  • Patent number: 8324070
    Abstract: A semiconductor device includes a NMOS transistor of a peripheral circuit region. The NMOS transistor is formed over a relaxed silicon germanium layer and a silicon layer to have a tensile strain structure, thereby increasing electron mobility of a channel region in operation of the device. The semiconductor device may include a second active region including a first silicon layer connected to a first active region of a semiconductor substrate, a second silicon layer and a relaxed silicon germanium layer formed over the first silicon layer expected to be a NMOS region, and a NMOS gate formed over the second silicon layer.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: December 4, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yun Taek Hwang
  • Patent number: 8324072
    Abstract: A process for treating a semiconductor-on-insulator type structure that includes, successively, a support substrate, an oxide layer and a thin semiconductor layer. The process includes formation of a silicon nitride or silicon oxynitride mask on the thin semiconductor layer to define exposed areas at the surface of the layer which are not covered by the mask, and which are arranged in a desired pattern; and application of a heat treatment in a neutral or controlled reducing atmosphere and under controlled conditions of temperature and time to induce at least a portion of the oxygen of the oxide layer to diffuse through the thin semiconductor layer, thereby resulting in the controlled reduction in the oxide thickness in the areas of the oxide layer corresponding to the desired pattern. The mask is formed so as to be at least partially buried in the thickness of the thin semiconductor layer.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: December 4, 2012
    Assignee: Soitec
    Inventors: Christelle Veytizou, Fabrice Gritti, Eric Guiot, Oleg Kononchuk, Didier Landru
  • Patent number: 8318583
    Abstract: Provided is a method of forming an isolation structure of a semiconductor device capable of minimizing the number of performing a patterning process and having trenches of various depths. The method includes partially etching the semiconductor substrate using a first patterning process to form first trenches and second trenches having a first depth. The semiconductor substrate has first to third regions. The first trenches are formed in the first region, and the second trenched are formed in the second region. The semiconductor substrate is partially etched using a second patterning process, so that third trenches are formed in the third region, and fourth trenches are formed in the second region. The fourth trenches extend from bottoms of the second trenches. The third trenches have a second depth, and the fourth trenches have a third depth. An isolation layer filling the first to fourth trenches is formed.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: November 27, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Sik Jeong, Jeong-Uk Han, Weon-Ho Park, Byung-Sup Shim
  • Patent number: 8293616
    Abstract: Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active areas are enclosed by the isolation regions. The isolation regions are recessed to expose first parts of the sidewalls of the active areas. The first parts of the sidewalls of the active areas are covered with spacers. The isolation regions are etched to expose second parts of the sidewalls of the active area, the second parts being disposed below the first parts. The active areas are etched through the exposed second parts of the sidewalls to form lateral openings. The lateral openings are filled with a spin on dielectric.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: October 23, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hung Chang, Yu-Rung Hsu, Chen-Hua Yu
  • Patent number: 8288185
    Abstract: Provided are a semiconductor device and a method of forming the same. According to the method, a first buried oxide layer is locally formed in a semiconductor substrate and a core semiconductor pattern of a line form, a pair of anchor-semiconductor patterns and a support-semiconductor pattern are formed by patterning a semiconductor layer on the first buried oxide layer to expose the first buried oxide layer. The pair of anchor-semiconductor patterns contact both ends of the core semiconductor pattern, respectively, and the support-semiconductor pattern contacts one sidewall of the core semiconductor pattern, the first buried oxide layer below the core semiconductor pattern is removed. At this time, a portion of the first buried oxide layer below each of the anchor-semiconductor patterns and a portion of the first buried oxide layer below the support-semiconductor pattern remain. A second buried oxide layer is formed to fill a region where the first buried oxide layer below the core semiconductor pattern.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: October 16, 2012
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: In Gyoo Kim, Dae Seo Park, Jun Taek Hong, Gyungock Kim
  • Patent number: 8259767
    Abstract: Semiconductor laser array devices capable of emitting mid- to long-wavelength infrared (i.e., 4-12 ?m) radiation are provided. The devices include a quantum cascade laser (QCL) structure comprising one or more active cores; an optical confinement structure; a cladding structure; and a plurality of laterally-spaced trench regions extending transversely through the optical confinement and cladding structures, and partially into the QCL structure. The trench regions, each of which comprises a lower trench layer comprising a semi-insulating material and an upper trench layer comprising a material having a refractive index that is higher than that of the semi-insulating material, define a plurality of laterally-spaced interelement regions separated by element regions in the laser array device.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: September 4, 2012
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Dan Botez, Luke J. Mawst
  • Patent number: 8252660
    Abstract: Disclosed herein are flash memory devices and methods of making the same. According to one embodiment, a flash memory device includes first trenches formed in a semiconductor substrate and arranged in parallel, second trenches discontinuously formed in the semiconductor substrate and arranged between the first trenches, first isolation structures respectively formed within the first trenches, second isolation structures respectively formed within the second trenches, and active regions defined by the first isolation structures and the second isolation structures.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: August 28, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung Kee Park
  • Patent number: 8183574
    Abstract: The present invention relates to an electronic device for providing improved heat transporting capability for protecting heat sensitive electronics and a method for producing the same. The present invention also relates to uses of the electronic device for various applications such as in LED lamps for signalizing, signage, automative and illumination applications or a display apparatus or any combinations thereof.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: May 22, 2012
    Assignee: NXP B.V.
    Inventor: Gilles Ferru
  • Patent number: 8158495
    Abstract: Silicon-based single-crystal portions are produced on a surface of a substrate, selectively in zones where a single-crystal material is initially exposed. To do this, a layer is firstly formed over the entire surface of the substrate, using a silicon precursor of the non-chlorinated hydride type, and under suitable conditions so that the layer is a single-crystal layer in the zones of the substrate where a single-crystal material is initially exposed and amorphous outside these zones. The amorphous portions of the layer are then selectively etched so that only the single-crystal portions of the layer remain on the substrate.
    Type: Grant
    Filed: April 18, 2007
    Date of Patent: April 17, 2012
    Assignee: STMicroelectronics S.A.
    Inventors: Didier Dutartre, Laurent Rubaldo, Alexandre Talbot
  • Patent number: 8071440
    Abstract: A method of fabricating a dynamic random access memory is provided. First, a substrate at least having a memory device area and a peripheral device area is provided, wherein an isolation structure and a capacitor are formed in the substrate of the memory device area, and an isolation structure and a well are formed in the substrate of the peripheral device area. A first oxide layer is formed on the substrate of the peripheral device area, and a passing gate isolation structure is formed on the substrate of the memory device area at the same time. A second oxide layer is formed on the substrate of the memory device area. And a first transistor is formed on the substrate of the memory device area, a passing gate is formed on the passing gate isolation structure, and a second transistor is formed on the substrate of the peripheral device area.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: December 6, 2011
    Assignee: United Microelectronics Corporation
    Inventors: Po-Sheng Lee, Yu-Hsien Lin, Wen-Fang Lee
  • Patent number: 8071454
    Abstract: A method for manufacturing a dielectric isolation type semiconductor device comprises: forming a plurality of trenches in a first region on a major surface of a semiconductor substrate; forming a first dielectric layer on the major surface of the semiconductor substrate and a first thick dielectric layer in the first region by oxidizing a surface of the semiconductor substrate; bonding a semiconductor layer of a first conductive type to the semiconductor substrate via the first dielectric layer; forming a first semiconductor region by implanting an impurity into a part of the semiconductor layer above the first thick dielectric layer; forming a second semiconductor region by implanting an impurity of a second conductive type into a part of the semiconductor layer so as to surround the first semiconductor region separating from the first semiconductor region.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: December 6, 2011
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hajime Akiyama
  • Patent number: 8053779
    Abstract: Provided are a thin film transistor (TFT) panel, a method of fabricating the same, and an organic light emitting display device (OLED) including the same. The TFT panel has a TFT region and a capacitor region. A TFT is formed in the TFT region and a capacitor is formed in the capacitor region. The TFT includes an active layer that includes a source and a drain regions. A gate insulation layer is formed on the active layer, and a gate electrode is formed on the gate insulation layer over the active layer. A source and a drain electrodes are formed over the active layer, and connected to the source and drain regions, respectively. In the TFT region, an interlayer insulation layer is formed between the gate electrode and the source/drain electrodes. In the capacitor region, an interlayer insulation layer is formed between a capacitor lower electrode and a capacitor upper electrode to form a capacitor.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: November 8, 2011
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Woo-Sik Jun, Kyung-Jin Yoo, Choong-Youl Im, Jong-Hyun Choi, Do-Hyun Kwon
  • Patent number: 8048759
    Abstract: The present invention aims at offering the semiconductor device which has the structure which are a high speed and a low power, and can be integrated highly. The present invention is a semiconductor device formed in the SOI substrate by which the BOX layer and the SOI layer were laminated on the silicon substrate. And the present invention is provided with the FIN type transistor with which the gate electrode coiled around the body region formed in the SOI layer, and the planar type transistor which was separated using partial isolation and full isolation together to element isolation, and was formed in the SOI layer.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: November 1, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Toshiaki Iwamatsu
  • Patent number: 8030148
    Abstract: In a strained SOI semiconductor layer, the stress relaxation which may typically occur during the patterning of trench isolation structures may be reduced by selecting an appropriate reduced target height of the active regions, thereby enabling the formation of transistor elements on the active region of reduced height, which may still include a significant amount of the initial strain component. The active regions of reduced height may be advantageously used for forming fully depleted field effect transistors.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: October 4, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jan Hoentschel, Andy Wei, Sven Beyer
  • Patent number: 8013372
    Abstract: A method for fabricating an integrated circuit is provided. The method includes providing a substrate having an active region and an opening in the substrate adjacent to the active region. The opening is filled with a dielectric material so as to provide an isolation region in the substrate. A transistor is also formed in the active region and a pre-metal dielectric layer formed over the substrate and transistor. At least one of the dielectric layer in isolation region or the pre-metal dielectric layer includes a stressed O3 TEOS oxide having a stress retaining dopant, wherein the concentration of the stress retaining dopant is sufficient to retard stress degradation of the O3 TEOS oxide.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: September 6, 2011
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Huang Liu, Jeff Shu, Luona Goh, Wei Lu
  • Patent number: 7943479
    Abstract: A method for semiconductor processing provides a DSB semiconductor body having a first crystal orientation layer, and a second crystal orientation layer, and a border region disposed between the first and second crystal orientations. A high-k metal gate stack is deposited over the first crystal orientation layer that comprises an insulation layer, a high-k dielectric layer, a first metal layer, and a second metal layer thereon.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: May 17, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Angelo Pinto, Manuel A. Quevedo-Lopez
  • Patent number: 7927962
    Abstract: A method of manufacturing a semiconductor device and a semiconductor device manufactured by the method, the method comprising: (a) forming a buffer layer on a semiconductor substrate; (b) patterning the buffer layer in a first direction to form buffer layer patterns having lateral surfaces and being spaced from each other at predetermined intervals; (c) forming a semiconductor epitaxial layer on and between the buffer layer patterns; (d) forming a first trench in the semiconductor epitaxial layer in a second direction perpendicular to the first direction to expose lateral surfaces of the buffer layer patterns; (e) selectively removing the buffer layer patterns exposed by the first trench to form spaces; (f) forming buried insulation films in the spaces formed by removal of the buffer layer patterns, a portion of semiconductor epitaxial layer being disposed between the buried insulation films; (g) removing a portion of the semiconductor epitaxial layer disposed between the buried insulation films to form a sec
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: April 19, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Min Soo Yoo
  • Patent number: 7923345
    Abstract: A method of manufacturing a semiconductor device wherein a laminate structure comprising a sacrificial layer is sandwiched between two etch stop layers (8,11) and which separates a semiconductor membrane (9) from a bulk substrate (1) is used to provide an underetched structure. Access trenches (4) and support trenches (5) are formed in the layered structure through the thickness of the semiconductor layer (9) and through the upper etch stop layer (8). The support trenches extend deeper through the sacrificial layer (12) and the lower etch stop layer and are filled. The sacrificial layer is exposed and etched away selectively to the etch stop layers to form a cavity (30) and realise a semiconductor membrane which is attached to the bulk substrate via a vertical support structure comprising the filled support trenches.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: April 12, 2011
    Assignee: NXP B.V.
    Inventors: Jan Sonsky, Wibo D. Van Noort
  • Patent number: 7906406
    Abstract: A process for manufacturing a semiconductor wafer including SOI-insulation wells includes forming, in a die region of a semiconductor body, buried cavities and semiconductor structural elements, which traverse the buried cavities and are distributed in the die region. The process moreover includes the step of oxidizing selectively first adjacent semiconductor structural elements, arranged inside a closed region, and preventing oxidation of second semiconductor structural elements outside the closed region, so as to form a die buried dielectric layer selectively inside the closed region.
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: March 15, 2011
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Gabriele Barlocchi, Pietro Corona, Flavio Francesco Villa
  • Patent number: 7883956
    Abstract: Methods of forming coplanar active regions and isolation regions and structures thereof are disclosed. One embodiment includes shallow-trench-isolation (STI) formation in a semiconductor-on-insulator (SOI) layer on a substrate of a semiconductor structure; and bonding a handle wafer to the STI and SOI layer to form an intermediate structure. The intermediate structure may have a single layer including at least one STI region and at least one SOI region therein disposed between the damaged substrate and the handle wafer. The method may also include cleaving the hydrogen implanted substrate and removing any residual substrate to expose a surface of the at least one STI region and a surface of the at least one SOI region. The exposed surface of the at least one STI region forms an isolation region and the exposed surface of the at least one SOI region forms an active region, which are coplanar to each other.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: February 8, 2011
    Assignee: International Business Machines Corporation
    Inventor: Huilong Zhu
  • Patent number: 7871893
    Abstract: Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.
    Type: Grant
    Filed: January 28, 2008
    Date of Patent: January 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gregory Costrini, David M. Dobuzinsky, Thomas S. Kanarsky, Munir D. Naeem, Christopher D. Sheraw, Richard Wise
  • Patent number: 7829972
    Abstract: A semiconductor component has a drift path (4) in a semiconductor body (5) of a semiconductor chip (6). The semiconductor component has an edge area (7) and a cell area (8), which is surrounded by the edge area (7). A trench structure (9), which surrounds the semiconductor component (6) in the edge area (7), is arranged in the edge area (7) of the semiconductor component (6). At least the trench walls (10) are covered by an insulation material (11). The trench structure (9) which surrounds the semiconductor component (6) has overlapping trench zones (12) with semiconductor material (13) arranged between them.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: November 9, 2010
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Holger Kapels
  • Patent number: 7799583
    Abstract: An integrated component includes a semiconductor substrate; at least one interconnect applied on the semiconductor substrate; an insulating layer applied on the at least one interconnect; and at least one opening through the insulating layer which interrupts the at least one interconnect into a first section and a second section.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: September 21, 2010
    Assignee: Infineon Technologies AG
    Inventors: G√ľnther Ruhl, Markus Hammer, Regina Kainzbauer
  • Patent number: 7795680
    Abstract: An integrated circuit system that includes: providing a substrate; depositing a dielectric on the substrate; depositing an isolation dielectric on the dielectric; forming a trench through the isolation dielectric and the dielectric to expose the substrate; depositing a dielectric liner over the integrated circuit system; processing the dielectric liner to form a trench spacer; and depositing an epitaxial growth within the trench that includes a crystalline orientation that is substantially identical to the substrate.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: September 14, 2010
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Huang Liu, Alex K. H. See, James Lee, Johnny Widodo, Chung Woh Lai, Wenzhi Gao, Zhao Lun, Shailendra Mishra, Liang-Choo Hsia
  • Patent number: 7790568
    Abstract: A method for fabricating a semiconductor device includes: providing a semiconductor substrate; forming a STI region on the semiconductor substrate; forming a channel region on the semiconductor substrate; implanting impurities into the STI region; and performing a thermal treatment to diffuse impurities to a side of the channel region.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: September 7, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Tomohiro Okamura
  • Patent number: 7781300
    Abstract: The invention relates to a method for producing a semiconducting structure including: controlled formation, through a mask (31), in a first substrate (30) in a semiconducting material, of at least one first area in an insulating material (36), up to the level of the lower surface (35) of the mask, before or during the removal of the mask.
    Type: Grant
    Filed: October 6, 2005
    Date of Patent: August 24, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Hubert Moriceau, Franck Fournel, Christophe Morales
  • Patent number: 7776715
    Abstract: A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate.
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: August 17, 2010
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, H. Montgomery Manning
  • Publication number: 20100187662
    Abstract: A method for forming a silicon film may be performed using a microheater including a substrate and a metal pattern spaced apart from the substrate. The silicon film may be formed on the metal pattern by applying a voltage to the metal pattern of the microheater to heat the metal pattern and by exposing the microheater to a source gas containing silicon. The silicon film may be made of polycrystalline silicon. A method for forming a pn junction may be performed using a microheater including a substrate, a conductive layer on the substrate, and a metal pattern spaced apart from the substrate. The pn junction may be formed between the metal pattern and the conductive layer by applying a voltage to the metal pattern of the microheater to heat the metal pattern. The pn junction may be made of polycrystalline silicon.
    Type: Application
    Filed: July 20, 2009
    Publication date: July 29, 2010
    Inventors: Junhee Choi, Andrei Zoulkarneev
  • Patent number: 7719077
    Abstract: Disclosed is a method for the production of a semiconductor component provided with at least one first vertical power component (5,9) and at least one lateral, active component (6) and/or at least one second vertical power component (10) between which is placed at least one trench (2) filled with an insulation (4). Also disclosed is a semiconductor component produced with the method. The semiconductor component is distinguished by an eccentric or concentric arrangement of the respective functional components (5,6,9,10) which are separated from each other by a trench insulation. To produce such a semiconductor component, at least one trench (2), which completely encompasses at least one part area of the front side and then is filled with an insulation (4) is etched into a silicon substrate (1). In the further course of the method, the entire area of the silicon substrate (1) is thinned (1) from said back side to said insulation (4), i.e. to the bottom side of the insulation.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: May 18, 2010
    Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
    Inventors: Klaus Kohlmann Von-Platen, Helmut Bernt, Detlef Friedrich
  • Patent number: 7719033
    Abstract: Semiconductor devices having thin film transistors (TFTs) and methods of fabricating the same are provided. The semiconductor devices include a semiconductor substrate and a lower interlayer insulating layer disposed on the semiconductor substrate. A lower semiconductor body disposed on or in the lower interlayer insulating layer. A lower TFT includes a lower source region and a lower drain region, which are disposed in the lower semiconductor body, and a lower gate electrode, which covers and crosses at least portions of at least two surfaces of the lower semiconductor body disposed between the lower source and drain regions.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: May 18, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hun Jeong, Soon-Moon Jung, Hoon Lim, Won-Seok Cho, Jin-Ho Kim, Chang-Min Hong, Jong-Hyuk Kim, Kun-Ho Kwak
  • Patent number: 7674712
    Abstract: A method of patterning a substrate by mechanically locating a first masking film over the substrate; removing one or more first opening portions in first locations in the first masking film to form one or more first masking portions in the first masking film. First materials are deposited over the substrate in the first locations to form first patterned areas before mechanically locating a second masking film over the substrate and first masking portions. One or more second opening portions are removed from second locations, different from the first locations, in both the second masking film and the first masking portions to form one or more second masking portions. Second materials are deposited over the substrate in the second locations to form second patterned areas.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: March 9, 2010
    Inventor: Ronald S. Cok
  • Patent number: 7659202
    Abstract: A method performed on a wafer having multiple chips each including a doped semiconductor and substrate involves etching an annulus trench, metalizing an inner and an outer perimeter side wall of the annulus trench, etching a via trench into the wafer, making a length of the via trench electrically conductive, thinning a surface of the substrate.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: February 9, 2010
    Inventor: John Trezza