Abstract: Disclosed is a method for the production of a semiconductor component provided with at least one first vertical power component (5,9) and at least one lateral, active component (6) and/or at least one second vertical power component (10) between which is placed at least one trench (2) filled with an insulation (4). Also disclosed is a semiconductor component produced with the method. The semiconductor component is distinguished by an eccentric or concentric arrangement of the respective functional components (5,6,9,10) which are separated from each other by a trench insulation. To produce such a semiconductor component, at least one trench (2), which completely encompasses at least one part area of the front side and then is filled with an insulation (4) is etched into a silicon substrate (1). In the further course of the method, the entire area of the silicon substrate (1) is thinned (1) from said back side to said insulation (4), i.e. to the bottom side of the insulation.

Abstract: A method of patterning a substrate by mechanically locating a first masking film over the substrate; removing one or more first opening portions in first locations in the first masking film to form one or more first masking portions in the first masking film. First materials are deposited over the substrate in the first locations to form first patterned areas before mechanically locating a second masking film over the substrate and first masking portions. One or more second opening portions are removed from second locations, different from the first locations, in both the second masking film and the first masking portions to form one or more second masking portions. Second materials are deposited over the substrate in the second locations to form second patterned areas.

Abstract: A method performed on a wafer having multiple chips each including a doped semiconductor and substrate involves etching an annulus trench, metalizing an inner and an outer perimeter side wall of the annulus trench, etching a via trench into the wafer, making a length of the via trench electrically conductive, thinning a surface of the substrate.

Abstract: A pad oxide layer is formed on a substrate. A pad nitride layer is formed on the pad oxide layer. The pad nitride layer and the pad oxide layer are patterned. Predetermined portions of the substrate are etched using the pad nitride layer as an etch barrier to thereby form trenches used as device isolation regions. The trenches are filled with an insulation layer to thereby form device isolation regions. The pad nitride layer is removed. Recesses are formed by etching predetermined portions of the pad oxide layer and the substrate. The pad oxide layer is removed. A gate oxide layer is formed on the recesses and on the substrate. Gate structures of which bottom portions are buried in the recesses on the gate oxide layer are formed.

Abstract: An integrated circuit (IC) fabrication technique is provided for isolating very high voltage (1000 s of volts) circuitry and low voltage circuitry formed on the same semiconductor die. Silicon-on-Insulator (SOI) technology is combined with a pair of adjacent backside high voltage isolation trenches that are fabricated to be wide enough to stand off voltages in excess of 1000V. The lateral trench is fabricated at two levels: the active silicon level and at the wafer backside in the SOI bulk.

Abstract: A method for fabricating a semiconductor device comprises providing a silicon-containing substrate with first, second, and third regions. First, second, and third gate stacks respectively overlie a portion of the silicon-containing substrate in the first, second, and third regions. A spacer is formed on opposing sidewalls of each of the first, second, and third gate stacks, the spacer overlying a portion of the silicon-containing substrate in the first, second, and third regions, respectively. A source/drain region is formed in a portion of the silicon-containing substrate in the first, second, and third regions, with the source/drain region adjacent to the first, second, and third gate stacks, respectively. The first, second, and third gate stacks have first, second, and third gate dielectric layers of various thicknesses and at least one thereof with a relatively thin thickness is treated by NH3-plasma, having a nitrogen-concentration of about 1013˜1021 atoms/cm2 therein.

Abstract: A method for manufacturing a semiconductor device, includes: (a) forming a SiGe layer on a Si substrate; (b) forming a Si layer on the SiGe layer; (c) forming a dummy pattern made of SiGe in a dummy region of the Si substrate; and (d) wet-etching and removing the SiGe layer formed under the Si layer. In the step (d), an etchant is kept to contact the dummy pattern from before a complete remove of the SiGe layer to an end of the etching.

Abstract: A process for realizing an integrated electronic circuit makes it possible to obtain transistors with p-type conduction and transistors with n-type conduction, in respective active zones having crystal orientations adapted to each conduction type. In addition, each active zone is electrically insulated from a primary substrate of the circuit, so that the entire circuit is compatible with SOI technology.

Abstract: A method for fabricating a semiconductor element on a semiconductor substrate having a support substrate and a semiconductor layer above the support substrate. The method includes preparing the semiconductor substrate having a transistor formation region and an element isolation region both defined thereon; forming a pad oxide film on the semiconductor layer of the semiconductor substrate; forming an oxidation-resistant mask layer on the pad oxide film; forming a resist mask to cover the transistor formation region on the oxidation-resistant mask layer; performing a first etching process for etching the oxidation-resistant mask layer using the resist mask as a mask to expose the pad oxide film of the element isolation region; and removing the resist mask and oxidizing the semiconductor layer below the exposed pad oxide film by LOCOS using the exposed oxidation-resistant mask layer as a mask to form an element isolation layer.

Abstract: Even if the insulated isolation structure which makes element isolation using partial and full isolation combined use technology is manufactured, the manufacturing method of a semiconductor device which can manufacture the semiconductor device with which characteristics good as a semiconductor element formed in the SOI layer where insulated isolation was made are obtained is obtained. Etching to an inner wall oxide film and an SOI layer is performed by using as a mask the resist and trench mask which were patterned, and the trench for full isolation which penetrates an SOI layer and reaches an embedded insulating layer is formed. Although a part of CVD oxide films with which the resist is not formed in the upper part are removed at this time, since a silicon nitride film is protected by the CVD oxide film, the thickness of a silicon nitride film is kept constant.

Abstract: Methods of forming a fine pattern include forming an underlying layer on a substrate, forming preliminary hard mask patterns having a first pitch on the underlying layer, the preliminary hard mask patterns having a first width and being spaced apart from each other by a second width smaller than the first width. The underlying layer is etched using the preliminary hard mask patterns as etch masks to thereby form preliminary underlying patterns. The preliminary hard mask patterns are pulled back, thereby forming hard mask patterns on the preliminary underlying patterns. An overlayer is formed on the substrate exposing top surfaces of the hard mask patterns. The hard mask patterns and the preliminary underlying patterns disposed below the hard mask patterns are etched using the overlayer as an etch mask, thereby forming underlying patterns having a second pitch smaller than the first pitch, and the overlayer is removed.

Abstract: A semiconductor device includes a substrate, an insulating layer formed on the substrate, an active layer formed on the insulating layer, and a metal layer formed on a back surface of the substrate, the substrate and the metal layer being in ohmic contact. By bringing the substrate and the metal layer into ohmic contact, the resistance difference between the substrate and the metal layer can be reduced.

Abstract: To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.

Abstract: A through via in an ultra high resistivity wafer and related methods are disclosed. A method for forming a through via comprises: providing a semiconductor wafer including a first silicon layer, a buried dielectric layer, and a substrate; forming a device on the first silicon; and forming a via from a side of the substrate opposite to the buried dielectric layer and through the substrate. Also disclosed is a method for providing a wafer varied resistivity using the through vias and buried dielectric.

Abstract: An FTI structure is employed in an isolation region making contact in a Y direction with a P-type impurity region serving as a drain region of a PMOS transistor. First, second and third N-type impurity layers serving as body regions are connected to a high potential line via fourth, fifth and sixth N-type impurity layers, respectively, and further via a seventh N-type impurity layer. The fourth to sixth N-type impurity layers are provided between an insulating layer of an SOI substrate and an element isolation insulating film in a PTI region.

Abstract: A through silicon via chip stack package includes a substrate; a plurality of chips stacked over the substrate and provided with chip selection pads, through silicon vias and rewirings connecting the chip selection pad and the through silicon via respectively, the through silicon via being connected to one another; and outside connection terminals attached to a lower surface of the substrate, wherein the rewirings in each of stacked chips are formed so as to have connection structures between the chip selection pads and the through silicon vias which are different from one another in each of the chips.

Abstract: An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.

Abstract: A method of avoiding substrate noise in an integrated circuit includes steps of receiving as input an integrated circuit design that includes at least a portion of a block for placement and routing on a substrate and an outer boundary of the block. An end cell is selected from a set of end cells for terminating the block in an outer area that extends from the outer boundary to an end cell boundary outside the block. The selected end cell is placed in the outer area to isolate the block electrically from the substrate.

Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

Abstract: Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.

Abstract: An integrated circuit structure, a trigger device and a method of electrostatic discharge protection, the integrated circuit structure including: a substrate having a top surface defining a horizontal direction, the substrate of a first dopant type; a first horizontal layer in the substrate, the first layer of a second dopant type; and a second horizontal layer of the first dopant type, the second layer on top of the first layer and between the top surface of the substrate and the first layer, the second layer electrically modulated by the first layer.

Abstract: A semiconductor device having wiring levels on opposite sides and a method of fabricating a semiconductor structure having contacts to devices and wiring levels on opposite sides. The method including fabricating a device on a silicon-on-insulator substrate with first contacts to the devices and wiring levels on a first side to the first contacts, removing a lower silicon layer to expose the buried oxide layer, forming second contacts to the devices through the buried oxide layer and forming wiring levels over the buried oxide layer to the second contacts.

Abstract: The present invention provides an integrated circuit and a method of manufacture therefor. The integrated circuit (100), in one embodiment without limitation, includes a dielectric layer (120) located over a wafer substrate (110), and a semiconductor substrate (130) located over the dielectric layer (120), the semiconductor substrate (130) having one or more transistor devices (160) located therein or thereon. The integrated circuit (100) may further include an interconnect (180) extending entirely through the semiconductor substrate (130) and the dielectric layer (120), thereby electrically contacting the wafer substrate (110), and one or more isolation structures (150) extending entirely through the semiconductor substrate (130) to the dielectric layer (120).

Abstract: A method of manufacturing a semiconductor device, includes preparing a semiconductor substrate, bonding a first semiconductor layer onto a part of the semiconductor substrate with a first insulating layer interposed therebetween, forming a second insulating layer on a side of the first semiconductor layer, epitaxially growing a second semiconductor layer in a region on the semiconductor substrate other than a region formed with the first insulating layer, forming a first semiconductor element in the first semiconductor layer on the first insulating layer, and forming a second semiconductor element in the second semiconductor layer on the second insulating layer.

Abstract: Disclosed herein is a method comprised of providing a wafer comprised of a bulk substrate, an insulating layer positioned above the bulk substrate, and a semiconducting layer positioned above the insulating layer, forming an opening in the semiconducting layer and the insulating layer to thereby expose a surface area of the bulk substrate, forming an alignment mark in the bulk substrate within the exposed surface area of the bulk substrate, and forming a layer of material above the alignment mark and in the opening. A wafer is also disclosed herein that is comprised of a bulk substrate, an insulating layer positioned above the bulk substrate, a semiconducting layer positioned above the insulating layer, an opening formed in the semiconducting layer and the insulating layer, an alignment mark formed in the bulk substrate within an area defined by the opening, and a layer of material positioned above the alignment mark and within the opening.

Abstract: A method of forming a semiconductor device, including providing a substrate having a first insulative layer on a surface of the substrate, and a device layer on a surface of the first insulative layer, forming a spacer around the first insulative layer and the device layer, removing a portion of the substrate adjacent to the first insulative layer in a first region and a non-adjacent second region of the substrate, such that an opening is formed in the first and second regions of the substrate, leaving the substrate adjacent to the first insulative layer in a third region of the substrate, filling the opening within the first and second regions of the substrate, planarizing a surface of the device, and forming a device within the device layer, such that diffusion regions of the device are formed within the device layer above the first and second regions of the substrate, and a channel region of the device is formed above the third region of the substrate.

Abstract: The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least partially filled with a semiconductive material that comprises at least one atomic percent of an element other than silicon. The mask is removed and a first semiconductor circuit component is formed over the first portion of the substrate. Also, a second semiconductor circuit component is formed over the semiconductive material that at least partially fills the trench. The invention also includes semiconductor constructions.

Abstract: The present invention relates to a method for isolating semiconductor devices. The method includes the steps of: forming a patterned pad nitride layer pattern to open at least one isolation region on the substrate; forming a first trench and a second trench by etching the exposed substrate; depositing a first oxide layer to fill the first trench by performing an atomic layer deposition (ALD) method; etching a portion of the first oxide layer which is filled into the wide trench; and depositing a second oxide layer by performing a deposition method.

Abstract: An active matrix substrate includes a load circuit including a first active element performing a switching operation of a load, the first active element including a semiconductor film of a substantially polycrystalline state; a drive circuit including a second active element controlling driving the load, the second active element including a semiconductor film of a substantially single crystalline state, a hole being provided to one of a part and a peripheral part of the semiconductor film, the hole functioning a starting point for crystallizing the semiconductor film; and a substrate on a same plane of which the load circuit and the drive circuit are formed.

Abstract: The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).

Abstract: A semiconductor device includes a common diffusion structure formed in each region of a substrate in which semiconductor components are formed. The diffusion structures are separated into sections by trenches to form semiconductor components. The trenches define sizes of the semiconductor components and isolate the semiconductor components from the surrounding area.

Abstract: A method for producing a detection/test tape includes depositing a material onto a surface of at least one first substrate to form a plurality of element structures. Electrodes are deposited on a surface of each of the plurality of element structures, and the element structures are bonded to a second substrate, where the second substrate is conductive or has a conductive layer, and the second substrate is carried on a carrier plate. The at least one first substrate is removed from the element structures and second side electrodes are deposited on a second surface of each of the plurality of element structures. An insulative material is inserted around the element structures to electrically isolate the two substrates used to bond the element structures. A second side of the element structures is then bonded to another substrate, where the other substrate is conductive or has a conductive layer. Thereafter, the carrier plate carrying the second substrate is removed.

Abstract: The present invention provides a method of fabricating a patterned silicon-on-insulator substrate which includes dual depth SOI regions or both SOI and non-SOI regions within the same substrate. The method of the present invention includes forming a silicon mask having at least one opening on a surface of Si-containing material, recessing the Si-containing material through the at least one opening using an etching process to provide a structure having at least one recess region and a non-recessed region, and forming a first buried insulating region in the non-recessed region and a second buried insulating region in the recessed region. In accordance with the present invention, the first buried insulating region in the non-recessed region is located above the second buried isolation region in the recessed region. A lift-off step can be employed to remove the first buried insulating region and the material that lies above to provide a substrate containing both SOI and non-SOI regions.

Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51< prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.

Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.

Abstract: A method of forming shallow trenches used, for example, in shallow trench isolation includes the steps of providing a p-type silicon substrate, forming a layer in the p-type silicon substrate, wherein the layer includes p-type silicon interposed between n-type silicon. The p-type silicon layer interposed between the n-type silicon is then subject to an anodization process to form porous silicon. The porous silicon regions are then oxidized. The porosity of the silicon layer may be controlled to create an isolation region that is either substantially flush with, above, or below an upper surface of the n-type top layer. For example, by adjusting the anodization time, a retrograde cross-sectional profile of the shallow trench can be obtained that leads to improved isolation between adjacent devices.

Abstract: A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. An SiGe layer is grown in the channel of the nFET channel and a Si:C layer is grown in the pFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component in an overlying grown epitaxial layer. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel. In a further implementation, the SiGe layer is grown in both the nFET and pFET channels. In this implementation, the stress level in the pFET channel should be greater than approximately 3 GPa.

Abstract: A method of fabricating a trench capacitor of a mixed mode integrated circuit includes forming shallow trench isolation regions for isolating active/passive devices on a semiconductor substrate. The lower electrode layer of the polysilicon layer, the dielectric layer, and the upper electrode layer are formed in sequence in a plurality of shallow trench isolation regions to form a trench capacitor. The present invention uses a trench capacitor to substitute for the 3-dimensional structure capacitor to overcome the disadvantages of the conventional capacitor, resulting in increasing the surface area of electrode and the capacitance.

Abstract: A semiconductor chip comprises a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.

Abstract: A method for forming at least one conductive line intended to receive high-frequency or high-value currents, formed above a given portion of a solid substrate outside of which are formed other elements, including the steps of digging at least one trench in the solid substrate; forming an insulating area in the trench; and forming said conductive line above the insulating area.

Abstract: A high performance semiconductor device and the method for making same is disclosed with an improved drive current. The semiconductor device has source and drain regions built on an active region, a length of the device being different than a width thereof. One or more isolation regions are fabricated surrounding the active region, the isolation regions are then filled with an predetermined isolation material whose volume shrinkage exceeds 0.5% after an anneal process. A gate electrode is formed over the active region, and one or more dielectric spacers are made next to the gate electrode. Then, a contact etch stopper layer is put over the device, wherein the isolation regions, spacers and contact etch layer contribute to modulating a net strain imposed on the active region so as to improve the drive current.

Abstract: The present invention discloses a method for manufacturing semiconductor device wherein a channel implant process of a transistor in a DRAM is performed in a self-aligned manner without using any mask. In accordance with the method, a device isolation film defining an active region on a semiconductor substrate. The device isolation film extrudes upward higher than the active region. The active region is subjected to a tilt ion implant process for implanting a impurity into the active region from two directions using the device isolation film as a mask so that a impurity concentration of the active region adjacent to the device isolation film is one half of that of the active region between the active region adjacent to the device isolation film. A stacked structure of a gate oxide film and a gate electrode are formed on the active region to complete the formation process of the semiconductor device.

Abstract: In a trench isolation structure of a semiconductor device, oxide liners are formed within the trenches, wherein a non-oxidizable mask is employed during various oxidation steps, thereby creating different types of liner oxides and thus different types of corner rounding and thus mechanical stress. Therefore, for a specified type of circuit elements, the characteristics of the corresponding isolation trenches may be tailored to achieve an optimum device performance.

Abstract: Field effect transistor with increased charge carrier mobility due to stress in the current channel 22. The stress is in the direction of current flow (longitudinal). In PFET device, the stress is compressive; in NFET devices, the stress is tensile. The stress is created by a compressive film 34 in an area 32 under the channel. The compressive film pushes up on the channel 22, causing it to bend. In PFET devices, the compressive film is disposed under ends 31 of the channel (e.g. under the source and drain), thereby causing compression in an upper portion 22A of the channel. In NFET devices, the compressive film is disposed under a middle portion 40 of the channel (e.g. under the gate), thereby causing tension in the, upper portion of the channel. Therefore, both NFET and PFET device can be enhanced. A method for making the devices is included.

Abstract: A method of filling intervals between protruding structures is provided. A substrate with a plurality of protruding structures thereon is provided. The protruding structures are distributed over the substrate such that intervals are formed between adjacent protruding structures. A first dielectric layer is formed over the substrate so that the dielectric material fills the intervals between the protruding structures and covers the protruding structures as well. The first dielectric layer has a plurality of apertures therein located at a level above a top section of the protruding structures. A chemical/mechanical polishing operation is performed to remove a portion of the dielectric layer and expose the apertures to form a plurality of openings. An anisotropic etching operation is performed to increase the width of these openings. Finally, a second dielectric layer is formed over the first dielectric layer to fill the openings completely.

Abstract: Temperature sensitive devices may be shielded from temperature generating devices on the same integrated circuit by appropriately providing a trench that thermally isolates the heat generating devices from the temperature sensitive devices. In one embodiment, the trench may be formed by a back side etch completely through an integrated circuit wafer. The resulting trench may be filled with a thermally insulating material.

Abstract: An integrated circuit chip comprises a periphery portion and a memory portion. The memory portion includes a data storage layer and a logic layer formed underneath the data storage layer and is separated therefrom by an intermediate layer. A first conductive layer is formed within the intermediate layer to communicatively couple the periphery and memory portions of the integrated circuit chip, and a second conductive layer is formed within the intermediate layer to communicatively couple the periphery and memory portions of the integrated circuit chip. The first and second conductive layers provide addressing and data retrieval between the memory portion and the periphery portion.

Abstract: Example methods of fabricating a silicon on insulator substrate are disclosed. One example method may include forming a plurality of trenches on a substrate, forming an insulation layer on the trenches, removing a portion of the insulation layer formed on the trenches to partially expose the substrate, and forming a silicon on insulator film in the substrate via the exposed portions of the substrate.

Abstract: Certain embodiments relate to methods for making a semiconductor device that inhibit the formation of a parasitic device. A method for making a semiconductor device includes a delimiting step and a dopant implantation step. The delimiting step partially oxidizes a single-crystal silicon layer provided on a semiconductor substrate 11 with an insulating layer therebetween to form a plurality of isolated single-crystal-silicon-layer segments 13a delimited by the insulating layer 16. In the implantation step, dopant ions 18 are implanted into the single-crystal-silicon-layer segments 13a to activate the single-crystal-silicon-layer segments 13a. In this implantation step, the dopant is implanted into the single-crystal-silicon-layer segments 13a by an implantation energy which is set so that the position of the maximum of the dopant concentration lies at bottom edges Ea and Eb of each single-crystal-silicon-layer segment 13a.

Abstract: A technique for reducing an on-resistance of a transistor is provided. A power MOSFET of the present invention has a semiconductor material which is disposed under a polysilicon gate and composed of polysilicon into which impurities are doped at low concentration. Therefore, a depletion layer is expanded to the inside of the semiconductor material under the polysilicon gate. Since the electric field strengths are uniform from the surface of a drain layer to a depth of the bottom surface of the semiconductor material and a high electric field is not generated at one site, the avalanche breakdown voltage of the transistor is increased. Therefore, the concentration of impurities in drain layer can be made higher than that in a conventional transistor and thereby the on-resistance of the transistor 1 can be reduced.