Abstract: A method of patterning a dummy layer is provided using the dark/clear ratio. First, the area of devices and the area of relevant devices are defined. The relevant devices are usually positioned around the devices. The devices, the relevant devices, and other regions are united according to the design rules to form a non-dummy pattern region. Then a dummy pattern region is defined. There are many dummy bulks in the dummy pattern region. Next, a known dark/clear ratio of the non-dummy pattern region is provided. A density of the dummy patterns is obtained from the known dark/clear ratio, the length of the dummy bulk, the width of the dummy bulk and a equation. The equation is as follows: the known dark/clear ratio=(the length-the parameter)(the width-the parameter)/[the length.times.the width-(the length-the parameter)(the width-the parameter)]. After obtaining the parameter, each dummy bulk is divided into two regions including a clear region and a dark region.

Abstract: A deposited film formation method comprises the steps of:(a) feeding a gas of an organometallic compound containing molybdenum atom and hydrogen gas onto a substrate having an electron donative surface; and(b) maintaining the temperature of the electron donative surface within the range of the decomposition temperature of the organometallic compound or lower and 800.degree. C. or lower to form a molybdenum film on the electron donative surface.

Abstract: An SOI semiconductor design methodology enables the implementation of simplified STI processes by the design and formation of a shallow trench isolation frame around an electrically active semiconductor region. The simplified STI processes include the fabrication of a trench by phase edge etching, trench sidewall oxidation, TEOS fill, and, finally a chemical or mechanical polish. The attribute which enables the simple process is that all isolation images can be current minimum or near minimum size, specifically no wider than twice the over-lay tolerance of the technology.

Abstract: In a method of a semiconductor device, an insulating film on a semiconductor substrate is formed. Then, a first mask on the insulating film in a first region is formed and the insulating film is removed using the first mask for isolation insulating films in the first region. In this case, an element to be formed in the first region has a first active region. Also, a second mask is formed on the insulating film in a second region. The second mask is different from the first mask. The insulting film is removed using the second mask for isolation insulating films in the second region. In this case, a first element to be formed in the first region has a first active region narrower than a second active region of a second element to be formed in the second region. Generally, the insulating film in the first region is removed and then the insulating film in the second region is removed.

Abstract: Isolation methods for integrated circuits use plasma chemical vapor deposition of an insulating layer followed by lift-off to remove at least portions of the insulating layer. In particular, a lift-off layer is formed on an integrated circuit substrate. The lift-off layer and the integrated circuit substrate beneath the lift-off layer are etched to form a trench in the integrated circuit substrate. The trench defines a first region on one side of the trench and a second region that is narrower than the first region on the other side of the trench. Plasma chemical vapor deposition is then performed to form an insulating layer filling the trench, on the first region and on the second region, with the insulating layer on the first region being thicker than on the second region. The insulating layer is then etched to expose the lift-off layer in the second region. The lift-off layer is then lifted off from the first region.

Abstract: A semiconductor device having an adjacent P-well and N-well, such as a complementary metal oxide semiconductor (CMOS) transistor, on a silicon on insulator (SOI) substrate has a latch-up problem caused by the parasitic bipolar effect. This invention provides a semiconductor device removing the latch-up problem and methods for fabricating the same. A semiconductor device according to the present invention has a T-shaped field oxide layer connected to a buried oxide layer of the SOI substrate to prevent the latch-up problem.

Abstract: The present invention presents a method in which semiconductor heterojunction and homojunction materials are selectively formed on silicon pedestals in an HMIC after the high temperature processing steps in fabricating the HMIC structure are completed.

Abstract: According to a preferred embodiment of the present invention, a stress-reducing region formed on a wafer allows standard bulk CMOS (non-SOI) devices and SOI devices to be reliably fabricated on the same wafer. The high-stress interface that typically exists between the SOI device regions and the non-SOI device regions is transferred to a region where the high-stress will be reduced and relaxed. Typically, this means that the high-stress interface will be fabricated so as to lie over a region of the wafer similar to Shallow Trench Isolation (STI) regions. In addition, by using another preferred embodiment of the present invention, a coplanar wafer surface can be maintained for a wafer which includes both bulk CMOS devices and SOI devices. This is accomplished by etching the silicon wafer in the SOI device regions prior to the oxygen implantation so that the surface of the area between the stress interface regions is lower than the overall surface of the remainder of the wafer. Then, when the SiO.sub.

Abstract: The present invention provides a method of fabricating fully dielectric isolated silicon (FDIS) by anodizing a buried doped silicon layer through trenches formed between active areas to form a porous silicon layer; oxidizing the porous silicon layer through the trenches to form a buried oxide layer; and by depositing a dielectric in the trenches. The process begins by forming a buried doped layer in a silicon substrate defining a silicon top layer over the conductive buried doped layer. The silicon top layer and the buried doped layer are patterned to form trenches that extend into but not through the buried doped layer. The trenches define isolated silicon regions. The buried doped layer is anodized to form a porous silicon layer. The porous silicon layer is converted into a buried oxide layer by oxidation. The oxidation step also forms a liner oxide layer on the tops and sidewalls of the isolated silicon regions.

Abstract: A method is provided for forming a transistor in which the gate is coupled to a second substrate dielectrically spaced above a first substrate. According to an embodiment, a polysilicon layer is formed across an interposing dielectric layer which is disposed across a single crystalline silicon substrate. The polysilicon layer is doped, making it the second semiconductor substrate. Trench isolation structures may be formed within the second substrate between ensuing active areas. A gate oxide is formed across the second substrate, and an opening is etched through the gate oxide down to the second substrate. A conductive material is formed within the opening, and polysilicon is deposited across the gate oxide. The polysilicon may be etched to form a gate conductor above the gate oxide. LDD implant areas are formed within the second substrate between the gate conductor and adjacent isolation structures.

Abstract: A bonded wafer 100 has a device substrate 16 with isolation trenches 30 defining device regions 18. Oxide dogbone structures are removed before filling trenches 30. Voids 36 in the trenches are spaced from the top of the trenches. The trenches are covered with an oxide layer 30 and filled with polysilicon 34. A LOCOS mask structure comprising a layer of CVD pad oxide and silicon nitride 50 cover the trenches and the adjacent device substrate regions.

Abstract: A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after etch back. In a silicon-on-insulator (SOI) device, dummy active areas are inserted between the active areas in order to maintain the thickness of the refill layer between the mesas to insure proper isolation between the active devices. The technique is also applicable to non-SOI devices.

Abstract: After partially burying an insulation layer in a first single-crystalline silicon substrate, and flattening, the first single-crystalline silicon substrate and a second single-crystalline substrate are formed with a low impurity concentration epitaxial layer. By grinding and polishing the first single crystalline silicon substrate, an ultra thin film SOI layer having thickness of about 0.1 .mu.m is formed. On the ultra thin film SOI layer, an insulation layer 8 for isolation is formed. Thus, an SOI substrate for integrating the power element and a control circuit element including the ultra thin film SOI layer in one chip can be provided.

Abstract: A buried silicide layer 111 in a bonded wafer 105 makes ohmic contact to a heavily doped buried layer 125. A dopant rapidly diffuses through the silicide layer and into the adjacent semiconductor to form the buried layer.

Abstract: For giving a device surface to a semiconductor device comprising a semiconductor substrate portion which has a substrate surface and a protruding portion protruding from the substrate surface, a method includes the steps of coating the substrate surface and the protruding portion with a first anti-polishing film, depositing an insulator film on the first anti-polishing film, and coating the insulator film with a second anti-polishing film. The insulator film has a first polishing rate for a polishing operation. The second anti-polishing film has a second polishing rate which can be slower than the first polishing rate for the polishing operation. Thereafter, the polishing operation is applied to the second anti-polishing film and to the insulator to make the device surface become substantially planarized. It is preferable that the first anti-polishing film has the second polishing rate for the polishing operation.

Abstract: According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.

Abstract: The present invention relates to a method of manufacturing a semiconductor device for forming an insulated gate field effect transistor in a completely isolated SOI layer, and has for its object to prevent depletion or inversion surely by introducing impurities of sufficiently high concentration into an SOI layer adjacent to an isolating film filled up between element regions of the SOI layer and a backing insulating layer and to aim at flattening of the SOI substrate surface, and further, includes the steps of implanting impurity ions into a semiconductor layer from an oblique direction so as to reach the semiconductor layer under an oxidation-preventive mask using the oxidation-preventive mask as a mask for ion implantation, heating the semiconductor layer in an oxidizing atmosphere with the oxidation-preventive mask so as to form a local oxide film to isolate the semiconductor layer, and also forming a impurity region with impurities implanted into the semiconductor layer in a region adjacent to the local

Abstract: An SOI structure (20) includes a semiconductor layer (15) formed on an insulating substrate (12). The semiconductor layer (15) is partitioned into an ESD protection portion (32) and a circuitry portion (34). A portion of the semiconductor layer (15) in the ESD protection portion (32) and a different portion of the semiconductor layer (15) in the circuitry portion (34) are differentially thinned. A device (60) which implements the desired circuit functions of the SOI structure (20) is fabricated in the circuitry portion (34). An ESD protection device (40) is fabricated in the ESD protection portion (32). The thick semiconductor layer (15) in the ESD protection portion (32) serves to distribute the ESD current and heat over a large area, thereby improving the ability of the SOI structure (20) to withstand an ESD event.

Abstract: A method for fabricating a semiconductor device having a bonded wafer structure capable of reducing crystal defect in a power element forming region thereof is disclosed A recess is formed in a control circuit element forming region of a first n- silicon substrate, then filled with a silicon oxide film and subjected to grinding and polishing to provide a mirror-surface. An n- epitaxial layer is formed on the surface of a second n+ silicon substrate, then the surface of the epitaxial layer is coupled to the surfaces of the silicon oxide film and second circuit region of the first substrate and heat-treated to be bonded thereto.