Bonding Of Plural Semiconductive Substrates Patents (Class 438/406)
  • Patent number: 10642671
    Abstract: A testing apparatus has first and second IOs, first and second comparators, a data combining module, and first and second data output circuits. The first and second comparators respectively receive first and second test data. The data combining module electrically connected to the first and second comparators receive compared first and second test data of the first and second comparators, and further receive a command code. The first and second data output circuits are respectively connected to the first and second IOs, and are further electrically connected to the data combining module. According to the command code, the data combining module outputs the compared first and second test data respectively to the first and second IOs through the first and second data output circuits, or respectively to the second and first IOs through the second and first data output circuits.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: May 5, 2020
    Assignee: ELITE SEMICONDUCTOR MEMORY TECNOLOGY INC.
    Inventor: Min-Chung Chou
  • Patent number: 10600675
    Abstract: A method may include providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising an insulator layer and a silicon layer. The silicon layer may be disposed on the insulator layer, where the silicon layer comprises a first silicon thickness variation. The method may include forming an oxide layer on the silicon layer, where the oxide layer has a uniform thickness. The method may include selectively etching the oxide layer on the silicon layer, wherein the oxide layer comprises a first non-uniform oxide thickness. After thermal processing of the SOI substrate in an oxygen ambient, the non-uniform oxide thickness may be configured to generate a second silicon thickness variation in the silicon layer, less than the first silicon thickness variation.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: March 24, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Andrew M. Waite, Morgan D. Evans, John Hautala
  • Patent number: 10403541
    Abstract: A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and comprises a region of nitrogen-reacted nanovoids in the front surface region; a silicon dioxide layer on the surface of the semiconductor handle substrate; a dielectric layer in contact with the silicon dioxide layer; and a semiconductor device layer in contact with the dielectric layer.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: September 3, 2019
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Qingmin Liu, Robert Wendell Standley
  • Patent number: 9837287
    Abstract: A method of forming a sealing structure for a bonded wafer is provided. The method includes providing the lower wafer and the upper wafer, forming a sealing material layer on each of the lower wafer and the upper wafer, forming a mask layer on the sealing material layer on each of the lower wafer and the upper wafer, etching the sealing material layer using the mask layer as an etch mask, so as to form a first protrusion at an edge of the lower wafer and a second protrusion at an edge of the upper wafer, and bonding the first protrusion and the second protrusion together to form the sealing structure. The sealing structure encloses a gap between the lower wafer and the upper wafer at an edge of the bonded wafer, so as to form a hermetically sealed cavity at the edge of the bonded wafer.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: December 5, 2017
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Yuankun Hou, Kuanchieh Yu, Yu Hua, Yuelin Zhao
  • Patent number: 9608119
    Abstract: Methods for fabricating semiconductor-metal-on-insulator (SMOI) structures include forming an acceptor wafer including an insulator material on a first semiconductor substrate, forming a donor wafer including a conductive material and an amorphous silicon material on a second semiconductor substrate, and bonding the amorphous silicon material of the donor wafer to the insulator material of the acceptor wafer. SMOI structures formed from such methods are also disclosed, as are semiconductor devices including such SMOI structures.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: March 28, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Ming Zhang, Andrew M. Bayless, John K. Zahurak
  • Patent number: 9583565
    Abstract: A method for manufacturing a semiconductor device comprises includes providing a substrate with a surface, forming an isolating layer on part of the surface, and forming a first semiconductor portion and spaced therefrom a second semiconductor portion on the surface of the substrate. The isolating layer is interposed between a side surface of the first semiconductor portion and a side surface of the second semiconductor portion which face each other. The method further includes forming a first side isolation layer on the side surface of the first semiconductor portion.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: February 28, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Poelzl
  • Patent number: 9500890
    Abstract: The method of manufacturing a device substrate includes forming a surface modifying layer on a process substrate. The surface modifying layer has a different hydrophobicity from that of the process substrate. The process substrate is disposed on a carrier substrate. The surface modifying layer is disposed between the process substrate and the carrier substrate. A device is formed on the process substrate. The process substrate is separated from the carrier substrate.
    Type: Grant
    Filed: June 10, 2014
    Date of Patent: November 22, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: TaeHwan Kim, Myeonghee Kim, Youngbae Kim, Jong Seong Kim, Myunghwan Park, Jonghwan Lee
  • Patent number: 9406507
    Abstract: Embodiments of the present disclosure relate to reducing dislocation density in a heteroepitaxial growth film and devices including heteroepitaxial films with reduced dislocation density. According to embodiments of the present disclosure, sidewalls of high aspect ratio trenches may be tilted or angled to allow defects in crystalline material formed in the high aspect ratio trenches to be terminated in the tilted sidewalls, including defects propagating along the length of the high aspect ratio trenches. Embodiments of the present disclosure may be used to reduce defects in heteroepitaxial growth on silicon (Si) for microelectronic applications, such as high mobility channels using Group III-V elements in field effect transistors.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: August 2, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Swaminathan T. Srinivasan, Fareen Adeni Khaja, Errol Antonio C. Sanchez, Patrick M. Martin
  • Patent number: 9362113
    Abstract: In a method for fabricating an engineered substrate for semiconductor epitaxy, an array of seed structures is assembled on a surface of the substrate. The seed structures in the array have substantially similar directional orientations of their crystal lattices, and are spatially separated from each other. Semiconductor materials are selectively epitaxially grown on the seed structures, such that a rate of growth of the semiconductor materials on the seed structures is substantially higher than a rate of growth of the semiconductor materials on regions of the surface. The semiconductor materials assume a lattice constant and directional orientation of crystal lattice that are substantially similar or identical to those of the seed structures. Related devices and methods are also discussed.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: June 7, 2016
    Assignee: Semprius, Inc.
    Inventors: Matthew Meitl, Scott Burroughs
  • Patent number: 9306026
    Abstract: A semiconductor structure includes: a germanium layer 30; and an aluminum oxynitride film 32 that is formed on the germanium layer, wherein: an EOT of the aluminum oxynitride film is 2 nm or less; Cit/Cacc is 0.4 or less; on a presumption that Au acting as a metal film is formed on the aluminum oxynitride film, the Cit is a capacitance value between the germanium layer and the metal film at a frequency of 1 MHz in a case where a voltage of the metal film with respect to the germanium layer is applied to an inversion region side by 0.5 V; and the Cacc is a capacitance value between the germanium layer and the metal film in an accumulation region.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: April 5, 2016
    Assignee: Japan Science and Technology Agency
    Inventors: Akira Toriumi, Toshiyuki Tabata
  • Patent number: 9236369
    Abstract: A method is disclosed that includes the steps outlined below. A first oxide layer is formed to divide a first semiconductor substrate into a first part and a second part. A second oxide layer is formed on the first part of the first semiconductor substrate. The first oxide layer is bonded to a third oxide layer of a second semiconductor substrate. The second part of first semiconductor substrate and the first oxide layer are removed to expose the first part of the first semiconductor substrate.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: January 12, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jing-Cheng Lin
  • Patent number: 9202754
    Abstract: A wafer is formed having a plurality of laser-to-slider submount features on a first surface. An etching process is used to form scribe lines between the submounts on the first surface of the wafer. The wafer is separated at the scribe lines to form the submounts.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: December 1, 2015
    Assignee: Seagate Technology LLC
    Inventors: Roger L. Hipwell, Jr., Dadi Setiadi
  • Patent number: 9190334
    Abstract: An integrated circuit on a semiconductor substrate has logic gates comprising FDSOI-type transistors made on said substrate, including at least one first transistor comprising a gate with a first work function, and including a transistor comprising a second work function, a memory including memory cells, each memory cell comprising FDSOI type transistors, including at least one third nMOS transistor with a gate presenting a third work function, the third transistor comprising a buried insulating layer and a ground plane at least one fourth pMOS transistor with a gate presenting said third work function, the fourth transistor comprising a buried insulating layer and a ground plane, the ground planes of the third and fourth transistors being made in a same well separating these ground planes from said substrate.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: November 17, 2015
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroelectronics (Crolles 2) SAS
    Inventors: Olivier Thomas, Jerome Mazurier, Nicolas Planes, Olivier Weber
  • Patent number: 9165905
    Abstract: A plurality of unpackaged substrates connected to one another is disclosed. The stepped structures on and/or in a first main area of a first substrate include a plurality of integrated circuits. The stepped structures run between the integrated circuits. The first conductor tracks extend from at least some contact connections of the respective integrated circuits as far as the stepped structures. The first substrate is connected on the side of the first main area to a further substrate. The first substrate is severed from a second main area opposite to the first main area such that the first substrate is divided into a plurality of substrate pieces. Each substrate piece has one of the integrated circuits. The first conductor tracks are accessible in interspaces between the substrate pieces. The second conductor tracks are formed from the second main area. At least some of the second conductor tracks lead from the second main area over side walls of the substrate pieces as far as the first conductor tracks.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: October 20, 2015
    Assignee: EPCOS AG
    Inventors: Hans Krueger, Alexander Schmajew, Alois Stelzl
  • Patent number: 9136141
    Abstract: A cap film which can prevent diffusion of hydrogen from the embrittled region and supply hydrogen to a region between the embrittled region and the surface of the semiconductor substrate is formed over the semiconductor substrate, and the semiconductor layer is transferred from the semiconductor substrate to the base substrate. In particular, the amount of hydrogen contained in the cap film formed over the semiconductor substrate is preferably greater than or equal to the irradiation amount of hydrogen ions.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: September 15, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Junichi Koezuka
  • Patent number: 9099354
    Abstract: The invention relates to an integrated circuit comprising a semi-conducting substrate and first and second cells. Each cell comprises first and second transistors of nMOS and pMOS type including first and second gate stacks including a gate metal. There are first and second ground planes under the first and second transistors and an oxide layer extending between the transistors and the ground planes. The gate metals of the nMOS and of a pMOS exhibit a first work function and the gate metal of the other pMOS exhibiting a second work function greater than the first work function. The difference between the work functions is between 55 and 85 meV and the first work function Wf1 satisfies the relation Wfmg?0.04?0.005*Xge<Wf1<Wfmg?0.03?0.005*Xge.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: August 4, 2015
    Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroelectronics (Crolles 2) SAS
    Inventors: Olivier Weber, Nicolas Planes, Rossella Ranica
  • Patent number: 9093499
    Abstract: A manufacture includes an IC comprising a stacking of a semiconducting substrate, a buried insulating layer, and a semiconducting layer, a first electronic component formed in and/or on the semiconductor layer, a bias circuit to generate a first bias voltage, first and second via-type interconnections, to which the bias circuit applies a same bias voltage equal to the first bias voltage, a first insulation trench separating the first electronic component from the first and second interconnections, a first ground plane having a first type of doping, placed beneath the buried insulating layer plumb with the first electronic component, and extending beneath the first insulation trench and up into contact the first interconnection, and a first well having a second type of doping opposite that of the first type, plumb with the first ground plane, and extending beneath the first insulation trench and up into contact with the second interconnection.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: July 28, 2015
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Jean-Philippe Noel, Bastien Giraud, Olivier Thomas
  • Patent number: 9076713
    Abstract: The invention relates to a method for fabricating a locally passivated germanium-on-insulator substrate wherein, in order to achieve good electron mobility, nitridized regions are provided at localized positions. Nitridizing is achieved using a plasma treatment. The resulting substrates also form part of the invention.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: July 7, 2015
    Assignees: Soitec, Commissariat à l'Énergie Atomique
    Inventors: Thomas Signamarcheix, Frederic Allibert, Chrystel Deguet
  • Patent number: 9059269
    Abstract: An approach for sinking heat from a transistor is provided. A method includes forming a substrate contact extending from a first portion of a silicon-on-insulator (SOI) island to a substrate. The method also includes forming a transistor in a second portion of the SOI island. The method further includes electrically isolating the substrate contact from the transistor by doping the first portion of the SOI island.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: June 16, 2015
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, Alvin J. Joseph, James A. Slinkman, Randy L. Wolf
  • Patent number: 9041147
    Abstract: According to a semiconductor substrate (40), a space (A) between a plurality of Si thin film (16), which are provide apart from one another on the insulating substrate (30), is (I) larger than a difference between elongation of part of the insulating substrate which part corresponds to the space (A) and elongation of each of Si wafers (10) when a change is made from room temperature to 600° C. and (II) smaller than 5 mm. This causes an increase in a region of each of a plurality of semiconductor thin films which region has a uniform thickness, and therefore prevents transferred semiconductor layers and the insulating substrate from being fractured or chipped.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: May 26, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masahiro Mitani
  • Patent number: 9029234
    Abstract: One of the wafers in a semiconductor wafer to wafer stack can be rotated a predefined number of positions, relative to a previous wafer in the stack, and bonded in the position in which the maximum number of good die are aligned. An adjustment circuit on each die reroutes signals received from a pad that has been relocated due to rotation. A communication channel formed from a pair of pads that are interconnected by a Through Substrate Vias can be placed in each die and can convey selected information from one die to the next. A code representative of the position orientation of each die can be recorded in a Programmable Read Only Memory located on each die, or may be down loaded from a remote source. Any additional wafer may be stacked serially, and each one may be rotated relative to the wafer that precedes it in the stack.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: May 12, 2015
    Assignee: International Business Machines Corporation
    Inventors: John Matthew Safran, Daniel Jacob Fainstein, Gary W. Maier, Yunsheng Song, Norman Whitelaw Robson
  • Patent number: 8999812
    Abstract: A graphene device may include a channel layer including graphene, a first electrode and second electrode on a first region and second region of the channel layer, respectively, and a capping layer covering the channel layer and the first and second electrodes. A region of the channel layer between the first and second electrodes is exposed by an opening in the capping layer. A gate insulating layer may be on the capping layer to cover the region of the channel layer, and a gate may be on the gate insulating layer.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: April 7, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wenxu Xianyu, Chang-youl Moon, Jeong-yub Lee, Chang-seung Lee
  • Patent number: 8987109
    Abstract: A method for manufacturing a bonded wafer includes: an ion implantation step of using a batch type ion implanter; a bonding step of bonding an ion implanted surface of a bond wafer to a surface of a base wafer directly or through an insulator film; and a delamination step of delaminating the bond wafer at an ion implanted layer, thereby manufacturing a bonded wafer having a thin film on the base wafer, wherein the ion implantation into the bond wafer carried out at the ion implantation step is divided into a plurality of processes, the bond wafer is rotated on its own axis a predetermined rotation angle after each ion implantation, and the next ion implantation is carried out at an arrangement position obtained by the rotation.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: March 24, 2015
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hiroji Aga, Isao Yokokawa, Nobuhiko Noto
  • Patent number: 8963337
    Abstract: A semiconductor wafer assembly formed by bonding a support wafer to a thin wafer using a double-sided bonding release tape. The support wafer provides support for the thin target wafer such that existing handling tools can accommodate transporting and processing the assembly without compromising the profile of the thin target wafer.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: February 24, 2015
    Assignee: Varian Semiconductor Equipment Associates
    Inventor: Arthur Paul Riaf
  • Patent number: 8951882
    Abstract: A method of fabricating an optoelectronic integrated circuit substrate includes defining a photonic device region on a first substrate, the photonic device region having a photonic device formed thereon, forming a trench in the photonic device region on a top surface of the first substrate, the trench having a first depth, filling the trench with a dielectric, bonding a second substrate on the first substrate to cover the trench, and thinning the second substrate to a first thickness.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seong-ho Cho
  • Patent number: 8898875
    Abstract: Providing a method for manufacturing a package capable of achieving reliable anodic bonding between the bonding material and a base board wafer even when the bonding material having a large resistance value is used. Providing a method for manufacturing a package by anodically bonding a bonding material, which is fixed in advance to an inner surface of a lid board wafer made of an insulator, to an inner surface of a base board wafer made of an insulator, the method including an anodic bonding step where an auxiliary bonding material serving as an anode is disposed on an outer surface of the lid board wafer, a cathode is disposed on an outer surface of the base board wafer, and a voltage is applied between the auxiliary bonding material and the cathode, wherein the auxiliary bonding material is made of a material that causes an anodic bonding reaction between the auxiliary bonding material and the lid board wafer in the anodic bonding step.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: December 2, 2014
    Assignee: Seiko Instruments Inc.
    Inventor: Takeshi Sugiyama
  • Patent number: 8883609
    Abstract: According to an embodiment, a method for manufacturing a semiconductor structure includes providing a first monocrystalline semiconductor portion having a first lattice constant in a reference direction and forming a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: November 11, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Mathias Plappert, Hans-Joachim Schulze
  • Patent number: 8883541
    Abstract: A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment, connections are established between a multiple photovoltaic cell portion and a circuitry portion of an integrated structure to enable self-powering of the circuitry portion by the multiple photovoltaic cell portion.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: November 11, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Yuanning Chen, Thomas P. Conroy, Jeffrey R. DeBord, Nagarajan Sridhar
  • Patent number: 8853055
    Abstract: A method for manufacturing a semiconductor device includes: (a) providing a base unit made of a material having a first lattice constant; (b) forming a first sacrificial layer made of a material having a second lattice constant on the base unit and a second sacrificial layer made of a material having a third lattice constant on the first sacrificial layer, the first lattice constant ranging between the second and third lattice constants so that two lattice stresses in opposite directions occur in the epitaxial substrate; (c) forming an epitaxial unit on the second sacrificial layer; (d) forming a permanent substrate on the epitaxial unit; and (e) removing the epitaxial unit.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: October 7, 2014
    Assignee: National Chung-Hsing University
    Inventors: Ray-Hua Horng, Ming-Chun Tseng, Fan-Lei Wu
  • Patent number: 8846480
    Abstract: A surface channel transistor is provided in a semiconductive device. The surface channel transistor is either a PMOS or an NMOS device. Epitaxial layers are disposed above the surface channel transistor to cause an increased bandgap phenomenon nearer the surface of the device. A process of forming the surface channel transistor includes grading the epitaxial layers.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: September 30, 2014
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Mantu Hudait, Marko Radosavljevic, Gilbert Dewey, Jack T. Kavalieros
  • Patent number: 8841742
    Abstract: Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming recesses in the donor structure, implanting ions into the donor structure to form a generally planar, inhomogeneous weakened zone therein, and providing material within the recesses. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: September 23, 2014
    Assignee: Soitec
    Inventors: Mariam Sadaka, Ionut Radu
  • Patent number: 8809123
    Abstract: Three dimensional integrated circuit (3DIC) structures and hybrid bonding methods for semiconductor wafers are disclosed. A 3DIC structure includes a first semiconductor device having first conductive pads disposed within a first insulating material on a top surface thereof, the first conductive pads having a first recess on a top surface thereof. The 3DIC structure includes a second semiconductor device having second conductive pads disposed within a second insulating material on a top surface thereof coupled to the first semiconductor device, the second conductive pads having a second recess on a top surface thereof. A sealing layer is disposed between the first conductive pads and the second conductive pads in the first recess and the second recess. The sealing layer bonds the first conductive pads to the second conductive pads. The first insulating material is bonded to the second insulating material.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Xin-Hua Huang, Lan-Lin Chao, Chia-Shiung Tsai
  • Patent number: 8803261
    Abstract: A method of fabricating a micro-electrical-mechanical system (MEMS) transducer comprises the steps of forming a membrane on a substrate, and forming a back-volume in the substrate. The step of forming a back-volume in the substrate comprises the steps of forming a first back-volume portion and a second back-volume portion, the first back-volume portion being separated from the second back-volume portion by a step in a sidewall of the back-volume. The cross-sectional area of the second back-volume portion can be made greater than the cross-sectional area of the membrane, thereby enabling the back-volume to be increased without being constrained by the cross-sectional area of the membrane. The back-volume may comprise a third back-volume portion. The third back-volume portion enables the effective diameter of the membrane to be formed more accurately.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: August 12, 2014
    Assignee: Wolfson Microelectronics plc
    Inventors: Anthony Bernard Traynor, Richard Ian Laming, Tsjerk H. Hoekstra
  • Patent number: 8785229
    Abstract: Methods of forming micromechanical resonators include forming first and second substrates having first and second semiconductor layers of first and second conductivity type therein, respectively. The first semiconductor layer of first conductivity type is bonded to the second semiconductor layer of second conductivity type to thereby define a first rectifying junction at an interface of the bonded semiconductor layers. A piezoelectric layer is formed on the first rectifying junction and at least a first electrode is formed on the piezoelectric layer.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: July 22, 2014
    Assignee: Integrated Device Technology, inc.
    Inventor: Wanling Pan
  • Patent number: 8785292
    Abstract: An anodic bonding apparatus includes a first electrode and a second electrode. The first electrode has a first surface, and the second electrode has a second surface facing the first surface. The first surface includes a first central area; a first substrate placing area for placing a laminated substrate; and a first peripheral area surrounding the first substrate placing area. The second surface includes a second central area corresponding to the first central area; a second substrate placing area surrounding the second central area; and a second peripheral area corresponding to the first peripheral area and surrounding the second substrate placing area. Further, the second electrode includes a curved portion curved toward the first electrode, so that a distance between the first central area and the second central area becomes smaller than a distance between the first peripheral area and the second peripheral area.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: July 22, 2014
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Shinichi Sueyoshi
  • Patent number: 8774582
    Abstract: “Hybrid photonic devices” describe devices wherein the optical portion—i.e., the optical mode, comprises both the silicon and III-V semiconductor regions, and thus the refractive index of the semiconductor materials and the refractive index of the bonding layer region directly effects the optical function of the device. Prior art devices utilize an optically compliant layer that is the same material as the III-V substrate; however, during the final sub-process of the bonding process, the substrates must be removed by acids. These acids can etch into the bonding layer, causing imperfections to propagate at the interface of the bonded material, adversely affecting the optical mode shape and propagation loss of the device. Embodiments of the invention utilize a semiconductor etch-selective bonding layer that is not affected by the final stages of the bonding process (e.g., substrate removal), and thus protects the bonding interface layer from being affected.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: July 8, 2014
    Assignee: Aurrion, Inc.
    Inventors: Matthew Jacob-Mitos, Gregory Alan Fish, Alexander W. Fang
  • Patent number: 8765508
    Abstract: Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: July 1, 2014
    Assignee: Soitec
    Inventor: Chantal Arena
  • Patent number: 8754424
    Abstract: Discontinuous bonds for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a first substrate and a second substrate, with at least one of the first substrate and the second substrate having a plurality of solid-state transducers. The second substrate can include a plurality of projections and a plurality of intermediate regions and can be bonded to the first substrate with a discontinuous bond. Individual solid-state transducers can be disposed at least partially within corresponding intermediate regions and the discontinuous bond can include bonding material bonding the individual solid-state transducers to blind ends of corresponding intermediate regions. Associated methods and systems of discontinuous bonds for semiconductor devices are disclosed herein.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: June 17, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Scott D. Schellhammer, Vladimir Odnoblyudov, Jeremy S. Frei
  • Patent number: 8748292
    Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: June 10, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Thomas A. Langdo, Matthew T. Currie, Richard Hammond, Anthony J. Lochtefeld, Eugene A. Fitzgerald
  • Patent number: 8741738
    Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to a semiconductor apparatus with a metallic alloy. An exemplary structure for an apparatus comprises a first silicon substrate; a second silicon substrate; and a contact connecting each of the first and second substrates, wherein the contact comprises a Ge layer adjacent to the first silicon substrate, a Cu layer adjacent to the second silicon substrate, and a metallic alloy between the Ge layer and Cu layer.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: June 3, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi Hsun Chiu, Ting-Ying Chien, Ching-Hou Su, Chyi-Tsong Ni
  • Patent number: 8735262
    Abstract: According to an embodiment, a method of forming a semiconductor device includes: providing a wafer having a semiconductor substrate with a first side a second side opposite the first side, and a dielectric region arranged on the first side; mounting the wafer with the first side on a carrier system; etching a deep vertical trench from the second side through the semiconductor substrate to the dielectric region, thereby insulating a mesa region from the remaining semiconductor substrate; and filling the deep vertical trench with a dielectric material.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: May 27, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hermann Gruber, Thomas Gross, Andreas Peter Meiser, Markus Zundel
  • Patent number: 8735263
    Abstract: An SOI substrate is manufactured by the following steps: a semiconductor substrate is irradiated with an ion beam in which the proportion of H2O+ to hydrogen ions (H3+) is lower than or equal to 3%, preferably lower than or equal to 0.3%, whereby an embrittled region is formed in the semiconductor substrate; a surface of the semiconductor substrate and a surface of a base substrate are disposed so as to be in contact with each other, whereby the semiconductor substrate and the base substrate are bonded; and a semiconductor layer is separated along the embrittled region from the semiconductor substrate which is bonded to the base substrate by heating the semiconductor substrate and the base substrate, so that the semiconductor layer is formed over the base substrate.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: May 27, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Kazuya Hanaoka
  • Patent number: 8730676
    Abstract: A composite component includes a first joining partner, at least one second joining partner and a first joining layer situated between the first joining partner and the second joining partner. In addition to the first joining layer, at least one second joining layer is provided between the first and the second joining partner; and at least one intermediate layer is situated between the first and the second joining layer.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: May 20, 2014
    Assignee: Robert Bosch GmbH
    Inventors: Michele Hirsch, Michael Guenther
  • Patent number: 8728867
    Abstract: A manufacturing of a semiconductor device includes forming one of a layer with a first metal and the layer with a second metal on one of a semiconductor chip mounting area of a support plate and a back surface of the semiconductor chip; forming the other of the layer with the first metal and the layer with the second metal on an area corresponding to a part of the area, in which one of the layer with the first metal and the layer with the second metal, of the other one of the semiconductor chip mounting area and the back surface of the semiconductor chip; and forming a layer which includes an alloy with the first metal and the second metal after positioning the semiconductor chip in the semiconductor chip mounting area to bond the semiconductor chip with the semiconductor chip mounting area.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: May 20, 2014
    Assignee: Fujitsu Limited
    Inventors: Kozo Shimizu, Keishiro Okamoto, Nobuhiro Imaizumi, Tadahiro Imada, Keiji Watanabe
  • Patent number: 8709913
    Abstract: Disclosed are a microelectronic assembly of two elements and a method of forming same. A microelectronic element includes a major surface, and a dielectric layer and at least one bond pad exposed at the major surface. The microelectronic element may contain a plurality of active circuit elements. A first metal layer is deposited overlying the at least one bond pad and the dielectric layer. A second element having a second metal layer deposited thereon is provided, and the first metal layer is joined with the second metal layer. The assembly may be severed along dicing lanes into individual units each including a chip.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: April 29, 2014
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Belgacem Haba, Ilyas Mohammed, Piyush Savalia, Craig Mitchell
  • Patent number: 8709951
    Abstract: In accordance with the invention, there are methods of controlling the sidewall angle of a polysilicon gate from batch to batch while maintaining current bottom critical dimension control performance. The method can include generating a correlation between a sidewall angle of a gate and RF bias power and etch time of one or more etch steps during the formation of the gate, developing a statistical model for the sidewall angle as a function of one or more of polysilicon density, polythickness, and etcher, and predicting a sidewall angle using the statistical model for a given polydensity, a given polythickness, and a given etcher. The method can also include comparing the predicted sidewall angle with a target sidewall angle and determining an optimized RF bias power and optimized etch time of one or more etch steps during the formation of the gate using the correlation to match the target sidewall angle.
    Type: Grant
    Filed: July 19, 2007
    Date of Patent: April 29, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Jay S. Chun
  • Patent number: 8698256
    Abstract: A method of fabricating a micro-electrical-mechanical system (MEMS) transducer comprises the steps of forming a membrane on a substrate, and forming a back-volume in the substrate. The step of forming a back-volume in the substrate comprises the steps of forming a first back-volume portion and a second back-volume portion, the first back-volume portion being separated from the second back-volume portion by a step in a sidewall of the back-volume. The cross-sectional area of the second back-volume portion can be made greater than the cross-sectional area of the membrane, thereby enabling the back-volume to be increased without being constrained by the cross-sectional area of the membrane. The back-volume may comprise a third back-volume portion. The third back-volume portion enables the effective diameter of the membrane to be formed more accurately.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: April 15, 2014
    Assignee: Wolfson Microelectronics plc
    Inventors: Anthony Bernard Traynor, Richard Ian Laming, Tsjerk Hans Hoekstra
  • Patent number: 8679944
    Abstract: The invention provides a method of trimming a structure that includes a first wafer bonded to a second wafer, with the first wafer having a chamfered edge. The method includes a first trimming step carried out over a first depth that includes at least the thickness of the first wafer and over a first width determined from the edge of the first wafer. A second trimming step is then carried out over a second depth that includes at least the thickness of the first wafer and over a second width that is less than the first width.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: March 25, 2014
    Assignee: Soitec
    Inventors: Marcel Broekaart, Marion Migette, Sébastien Molinari, Eric Neyret
  • Patent number: 8673733
    Abstract: Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming a generally planar weakened zone within the first donor structure defined by implanted ions therein. At least one of a concentration of the implanted ions and an elemental composition of the implanted ions may be formed to vary laterally across the generally planar weakened zone. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: March 18, 2014
    Assignee: Soitec
    Inventors: Mariam Sadaka, Ionut Radu
  • Patent number: 8673740
    Abstract: A method is for formation of an electrically conducting through-via within a first semiconductor support having a front face and comprising a silicon substrate. The method may include forming of a first insulating layer on top of the front face of the first semiconductor support, fabricating a handle including, within an additional rigid semiconductor support having an intermediate semiconductor layer, and forming on either side of the intermediate semiconductor layer of a porous region and of an additional insulating layer. The method may also include direct bonding of the first insulating layer and of the additional insulating layer, and thinning of the silicon substrate of the first semiconductor support so as to form a back face opposite to the front face.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 18, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Julien Cuzzocrea, Laurent-Luc Chapelon