Nondopant Implantation Patents (Class 438/407)
  • Patent number: 10707303
    Abstract: A semiconductor device, comprising a semiconductor substrate; an isolation layer disposed on the semiconductor substrate; a first active region and a second active region disposed at least partially above the isolation layer; a first gate structure and a second gate structure disposed on the isolation layer, the first active region, and the second active region; and an isolation pillar disposed on the isolation layer, between the first and second active regions, and between and in contact with the first and second gate structures, wherein the isolation pillar has an inverted-T shape. A method for making the semiconductor device. A system configured to implement the method and manufacture the semiconductor device.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haiting Wang, Hui Zang, Zhenyu Owen Hu
  • Patent number: 9190560
    Abstract: A method of forming a vertical III-nitride based light emitting diode structure and a vertical III-nitride based light emitting diode structure can be provided. The method comprises forming a III-nitride based light emitting structure on a silicon-on-insulator (SOI) substrate; forming a metal-based electrode structure on the III-nitride based light emitting structure; and removing the SOI substrate by a layer transfer process such that the metal-based electrode structure functions as a metal-based substrate of the light emitting structure.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: November 17, 2015
    Assignee: Agency for Science Technology and Research
    Inventors: Tripathy Sudhiranjan, Lin Vivian Kaixin, Teo Siew Lang, Dolmanan Surani Bin
  • Patent number: 9111995
    Abstract: A method for improving anti-radiation performance of SOI structure that includes implementing particle implantations of high-energy neutrons, protons and ?-rays to a buried oxide layer of an SOI structure, and then performing annealing process. The high-energy particle implantation introduces displacement damage to the buried oxide layer of the SOI structure.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: August 18, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Yinxue Lv, Jinshun Bi, Jiajun Luo, Zhengsheng Han, Tianchun Ye
  • Patent number: 9105747
    Abstract: A method of forming an integrated circuit device is disclosed. A polycrystalline silicon layer is formed in direct contact with a dielectric material so that the dielectric material induces a stress in the polycrystalline silicon layer as the polycrystalline silicon layer is formed. A MOS transistor that includes a gate including the polycrystalline silicon is then completed.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: August 11, 2015
    Assignee: Infineon Technologies AG
    Inventors: Matthias Hierlemann, Chandrasekhar Sarma
  • Patent number: 9029250
    Abstract: A method for producing semiconductor regions including impurities includes forming a trench in a first surface of a semiconductor body. Impurity atoms are implanted into a bottom of the trench. The trench is extended deeper into the semiconductor body, thereby forming a deeper trench. Impurity atoms are implanted into a bottom of the deeper trench.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Jens Peter Konrath, Ronny Kern, Hans-Joachim Schulze
  • Patent number: 8932934
    Abstract: A process is provided for methods of reducing contamination of the self-forming barrier of an ultra-low k layer during semiconductor fabrication. In one aspect, a method includes: providing a cured ultra-low k film which contains at least one trench, and the pores of the film are filled with a pore-stuffing material; removing exposed pore-stuffing material at the surface of the trench to form exposed pores; and forming a self-forming barrier layer on the surface of the trench.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: January 13, 2015
    Assignee: Global Foundries Inc.
    Inventors: Moosung M. Chae, Errol Todd Ryan, Nicholas Vincent Licausi, Christian Witt, Ailian Zhao, Ming He, Sean X. Lin, Xunyuan Zhang, Kunaljeet Tanwar
  • Patent number: 8889529
    Abstract: Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, and/or emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. A highly doped epitaxial semiconductor layer comprising a highly doped hydrogenated crystalline semiconductor material layer portion is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. Minority carriers within the highly doped epitaxial semiconductor layer have a diffusion length that is larger than a thickness of the highly doped epitaxial semiconductor layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoar-Tabari, Tak H. Ning, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8890291
    Abstract: A method of manufacturing a silicon wafer provides a silicon wafer which can reduce the precipitation of oxygen to prevent a wafer deformation from being generated and can prevent a slip extension due to boat scratches and transfer scratches serving as a reason for a decrease in wafer strength, even when the wafer is provided to a rapid temperature-rising-and-falling thermal treatment process.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: November 18, 2014
    Assignee: Sumco Corporation
    Inventors: Toshiaki Ono, Wataru Ito, Jun Fujise
  • Patent number: 8772878
    Abstract: A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities prior to forming the corresponding strained semiconductor alloy, thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor and an N-channel transistor, while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: July 8, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Vassilios Papageorgiou, Belinda Hannon
  • Patent number: 8748285
    Abstract: A semiconductor structure includes a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a handle wafer, a buried oxide (BOX) layer on top of the handle wafer, and a top silicon layer on top of the BOX layer; and an implantation region located in the top silicon layer, the implantation region comprising a noble gas.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: June 10, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, William F. Clark, Jr., Richard A. Phelps, BethAnn Rainey, Yun Shi, James A. Slinkman
  • Patent number: 8741720
    Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: June 3, 2014
    Assignee: Intel Corporation
    Inventors: Giuseppe Curello, Ian R. Post, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark T. Bohr
  • Patent number: 8703596
    Abstract: The semiconductor device includes a silicon substrate having a channel region, a gate electrode formed over the channel region, buried semiconductor regions formed in a surface of the silicon substrate on both sides of the gate electrode, for applying to the surface of the silicon substrate a first stress in a first direction parallel to the surface of the silicon substrate, and stressor films formed on the silicon substrate between the channel region and the buried semiconductor regions in contact with the silicon substrate, for applying to the silicon substrate a second stress in a second direction which is opposite to the first direction.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: April 22, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoyoshi Tamura
  • Patent number: 8664078
    Abstract: An object is to provide a semiconductor device in which, through a simpler process, junction capacitance and power consumption can be reduced more than a conventional semiconductor device, and a manufacturing method thereof. An insulating film including an opening is formed over a base substrate and a part of a bond substrate is transferred to the base substrate, with the insulating film interposed therebetween, whereby a semiconductor film including a cavity between the semiconductor film and the base substrate is formed over the base substrate. Then, a semiconductor device including a semiconductor element such as a transistor is manufactured using the semiconductor film. The transistor includes a cavity between the base substrate and the semiconductor film used as an active layer. One cavity may be provided or a plurality of cavities may be provided.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: March 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hidekazu Miyairi
  • Patent number: 8658513
    Abstract: An improved method of creating LED arrays is disclosed. A p-type layer, multi-quantum well and n-type layer are disposed on a substrate. The device is then etched to expose portions of the n-type layer. To create the necessary electrical isolation between adjacent LEDs, an ion implantation is performed to create a non-conductive implanted region. In some embodiments, an implanted region extends through the p-type layer, MQW and n-type layer. In another embodiment, a first implanted region is created in the n-type layer. In addition, a second implanted region is created in the p-type layer and multi-quantum well immediately adjacent to etched n-type layer. In some embodiments, the ion implantation is done perpendicular to the substrate. In other embodiments, the implant is performed at an angle.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: February 25, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Fareen Adeni Khaja, Deepak Ramappa, San Yu, Chi-Chun Chen
  • Patent number: 8629047
    Abstract: Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiyuan Cheng, Calvin Sheen
  • Patent number: 8587039
    Abstract: A semiconductor device is formed in a semiconductor layer. A gate stack is formed over the semiconductor layer and comprises a first conductive layer and a second layer over the first layer. The first layer is more conductive and provides more stopping power to an implant than the second layer. A species is implanted into the second layer. Source/drain regions are formed in the semiconductor layer on opposing sides of the gate stack. The gate stack is heated after the step of implanting to cause the gate stack to exert stress in the semiconductor layer in a region under the gate stack.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: November 19, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Brian A. Winstead, Konstantin V. Loiko, Voon-Yew Thean
  • Patent number: 8563399
    Abstract: The invention relates to a detachable substrate for the electronics, optics or optoelectronics industry, that includes a detachable layer resting on a buried weakened region. This substrate is remarkable in that this buried weakened region consists of a semiconductor material that is denser in the liquid state than in the solid state and that contains in places precipitates of naturally volatile impurities. The invention also relates to a process for fabricating and detaching a detachable substrate.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: October 22, 2013
    Assignee: Soitec
    Inventor: Michel Bruel
  • Patent number: 8546238
    Abstract: A method for transferring a micro-technological layer includes preparing a substrate having a porous layer buried beneath a useful surface, forming an embrittled zone between it and the surface, bonding the substrate to a supporting substrate, causing detachment at the porous layer by mechanical stress to obtain a first substrate remnant, and a bare surfaced detached layer joined to the supporting substrate, performing technological steps on the bared surface of the detached layer, bonding the detached layer, by the surface to which the technological steps had been applied, to a second supporting substrate, causing detachment, at the embrittled zone, by heat treatment to obtain a detached layer remnant joined to the second supporting substrate, and the detached layer remnant joined to the first supporting substrate.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: October 1, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies
    Inventors: Aurelie Tauzin, Anne-Sophie Stragier
  • Patent number: 8502284
    Abstract: The semiconductor device includes a silicon substrate having a channel region, a gate electrode formed over the channel region, buried semiconductor regions formed in a surface of the silicon substrate on both sides of the gate electrode, for applying to the surface of the silicon substrate a first stress in a first direction parallel to the surface of the silicon substrate, and stressor films formed on the silicon substrate between the channel region and the buried semiconductor regions in contact with the silicon substrate, for applying to the silicon substrate a second stress in a second direction which is opposite to the first direction.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: August 6, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoyoshi Tamura
  • Patent number: 8471307
    Abstract: An integrated circuit containing a PMOS transistor with p-channel source/drain (PSD) regions which include a three layer PSD stack containing Si—Ge, carbon and boron. The first PSD layer is Si—Ge and includes carbon at a density between 5×1019 and 2×1020 atoms/cm3. The second PSD layer is Si—Ge and includes carbon at a density between 5×1019 atoms/cm3 and 2×1020 atoms/cm3 and boron at a density above 5×1019 atoms/cm3. The third PSD layer is silicon or Si—Ge, includes boron at a density above 5×1019 atoms/cm3 and is substantially free of carbon. After formation of the three layer epitaxial stack, the first PSD layer has a boron density less than 10 percent of the boron density in the second PSD layer. A process for forming an integrated circuit containing a PMOS transistor with a three layer PSD stack in PSD recesses.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: June 25, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Rajesh B. Khamankar, Haowen Bu, Douglas Tad Grider
  • Patent number: 8409975
    Abstract: A method for decreasing polysilicon gate resistance in a carbon co-implantation process which includes: depositing a first salicide block layer on a formed gate of a MOS device and etching it to form a first spacer of a side surface of the gate of the MOS device; performing a P-type heavily doped boron implantation process and a thermal annealing treatment, so as to decrease the resistance of the polysilicon gate; removing said first spacer, performing a lightly doped drain process, and performing a carbon co-implantation process at the same time, so as to form ultra-shallow junctions at the interfaces between a substrate and source region and drain region below the gate; re-depositing a second salicide block layer on the gate and etching the mask to form a second spacer; forming a self-aligned silicide on the surface of the MOS device. The invention can decrease the resistance of the P-type polysilicon gate.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: April 2, 2013
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventor: Liujiang Yu
  • Patent number: 8404570
    Abstract: Graded core/shell semiconductor nanorods and shapped nanorods are disclosed comprising Group II-VI, Group III-V and Group IV semiconductors and methods of making the same. Also disclosed are nanorod barcodes using core/shell nanorods where the core is a semiconductor or metal material, and with or without a shell. Methods of labeling analytes using the nanorod barcodes are also disclosed.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: March 26, 2013
    Assignee: The Regents of the University of California
    Inventors: A. Paul Alivisatos, Erik C. Scher, Liberato Manna
  • Patent number: 8368170
    Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: February 5, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Kong-Beng Thei, Mong-Song Liang
  • Patent number: 8354720
    Abstract: A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a plurality of spacers disposed on laterally opposing sides of the gate stack; source and drain regions proximate to the spacers, and a channel region subjacent to the gate stack and disposed between the source and drain regions; and a stressor subjacent to the channel region, and embedded within the semiconductor substrate, the embedded stressor being formed of a triangular-shape.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: January 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Shu-Jen Han, Pranita Kulkarni, Philip J. Oldiges
  • Patent number: 8338258
    Abstract: A method of fabricating an embedded stressor within a semiconductor structure and a semiconductor structure including the embedded stressor includes forming forming a dummy gate stack over a substrate of stressor material, anistropically etching sidewall portions of the substrate subjacent to the dummy gate stack to form the embedded stressor having angled sidewall portions, forming conductive material onto the angled sidewall portions of the embedded stressor, removing the dummy gate stack, planarizing the conductive material, and forming a gate stack on the conductive material.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: December 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Shu-Jen Han, Pranita Kulkarni, Philip J. Oldiges
  • Patent number: 8216951
    Abstract: Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: July 10, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhiyuan Cheng, Calvin Sheen
  • Patent number: 8193068
    Abstract: To provide an SOI substrate with an SOI layer that can be put into practical use, even when a substrate with a low allowable temperature limit such as a glass substrate is used, and to provide a semiconductor substrate formed using such an SOI substrate. In order to bond a single-crystalline semiconductor substrate to a base substrate such as a glass substrate, a silicon oxide film formed by CVD with organic silane as a source material is used as a bonding layer, for example. Accordingly, an SOL substrate with a strong bond portion can be formed even when a substrate with an allowable temperature limit of less than or equal to 700° C. such as a glass substrate is used. A semiconductor layer separated from the single-crystalline semiconductor substrate is irradiated with a laser beam so that the surface of the semiconductor layer is planarized and the crystallinity thereof is recovered.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: June 5, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Eiji Higa, Yoji Nagano, Tatsuya Mizoi, Akihisa Shimomura
  • Patent number: 8153450
    Abstract: At oxygen ion implanting steps in manufacture of a SIMOX wafer, a path is formed inside or on a back surface of wafer holding means, and oxygen ions are implanted while heating an outer peripheral portion of the wafer that is in contact with the wafer holding means by flowing a heated fluid through this path. An in-plane temperature of a wafer held at the time of ion implantation is prevented from becoming uneven, and in-plane film thicknesses of both an SOI layer and a BOX layer are uniformed.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: April 10, 2012
    Assignee: Sumco Corporation
    Inventor: Bong-Gyun Ko
  • Patent number: 8115271
    Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: February 14, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry Chuang, Kong-Beng Thei, Mong-Song Liang
  • Patent number: 8114754
    Abstract: Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to the substrate using the glass may be utilized to control a strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the substrate using the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control a strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: February 14, 2012
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventor: Fabrice Letertre
  • Patent number: 8093494
    Abstract: A process for forming functionalized nanorods. The process includes providing a substrate, modifying the substrate by depositing a self-assembled monolayer of a bi-functional molecule on the substrate, wherein the monolayer is chosen such that one side of the bi-functional molecule binds to the substrate surface and the other side shows an independent affinity for binding to a nanocrystal surface, so as to form a modified substrate. The process further includes contacting the modified substrate with a solution containing nanocrystal colloids, forming a bound monolayer of nanocrystals on the substrate surface, depositing a polymer layer over the monolayer of nanocrystals to partially cover the monolayer of nanocrystals, so as to leave a layer of exposed nanocrystals, functionalizing the exposed nanocrystals, to form functionalized nanocrystals, and then releasing the functionalized nanocrystals from the substrate.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: January 10, 2012
    Assignee: The Regents of the University of California
    Inventors: Ilan Gur, Delia Milliron, A. Paul Alivisatos, Haitao Liu
  • Patent number: 8053327
    Abstract: An integrated circuit system is provided including providing a substrate, forming an isolation structure base in the substrate without removal of the substrate, and forming a first transistor in the substrate next to the isolation structure base.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: November 8, 2011
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Shailendra Mishra, Lee Wee Teo, Yong Meng Lee, Zhao Lun, Chung Woh Lai, Shyue Seng Tan, Jeffrey Chee, Johnny Widodo
  • Patent number: 8043929
    Abstract: Hetero-semiconductor structures possessing an SOI structure containing a silicon-germanium mixed crystal are produced at a low cost and high productivity. The semiconductor substrates comprise a first layer formed of silicon having germanium added thereto, a second layer formed of an oxide and adjoined to the first layer, and a third layer derived from the same source as the first layer, but having an enriched content of germanium as a result of thermal oxidation and thinning of the third layer.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: October 25, 2011
    Assignee: Siltronic AG
    Inventors: Josef Brunner, Hiroyuki Deai, Atsushi Ikari, Martin Grassl, Atsuki Matsumura, Wilfried von Ammon
  • Patent number: 8030183
    Abstract: The method includes: a first step of colliding ions implanted from a surface of a SIMOX wafer into a silicon layer underneath a BOX layer against crystal defects to destroy the crystal defects; and a second step of heating the wafer obtained in the first step to recrystallize the silicon layer. If the ions to be implanted into the silicon layer are oxygen ions, then the first step initiates ion implantation with the temperature of the SIMOX wafer being 50° C. or lower, and sets an ion dose to 5×1015 atoms/cm2 to 1.5×1016 atoms/cm2 and implantation energy to 150 keV or higher but not higher than 220 keV. Consequently, crystal defects present in the silicon layer underneath the BOX layer of the SIMOX wafer are reduced.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: October 4, 2011
    Assignee: Sumco Corporation
    Inventor: Ryusuke Kasamatsu
  • Patent number: 8017492
    Abstract: A method for fabricating a semiconductor device according to the present invention is a method for fabricating a semiconductor device including a substrate layer including a plurality of first regions each having an active region and a plurality of second regions each being provided between adjacent ones of the first region. The fabrication method includes an isolation insulation film formation step of forming an isolation insulation film in each of the second regions so that a surface of the isolation insulation film becomes at the same height as that of a surface of a gate oxide film covering the active region, a peeling layer formation step of forming a peeling layer by ion-implanting hydrogen into the substrate layer after the isolation insulation film formation step, and a separation step of separating part of the substrate layer along the peeling layer.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: September 13, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasumori Fukushima, Masao Moriguchi, Yutaka Takafuji
  • Patent number: 7998828
    Abstract: A method of forming a metal ion transistor comprises forming a first electrode in a first isolation layer; forming a second isolation layer over the first isolation layer; forming a first cell region of a low dielectric constant (low-k) dielectric over the first electrode in the second isolation layer, the first cell region isolated from the second isolation layer; forming a cap layer over the second isolation layer and the first cell region, at least thinning the cap layer over the first cell region; depositing a layer of the low-k dielectric over the second isolation layer and the first cell region; forming metal ions in the low-k dielectric layer; patterning the low-k dielectric layer to form a second cell region; sealing the second cell region using a liner; and forming a second electrode contacting the second cell region and a third electrode contacting the second cell region.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: August 16, 2011
    Assignees: International Business Machines Corporation, Infineon Technologies North America
    Inventors: Fen Chen, Armin Fischer
  • Patent number: 7977202
    Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: July 12, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry Chuang, Kong-Beng Thei, Mong-Song Liang
  • Patent number: 7972947
    Abstract: In a method for fabricating a semiconductor element in a substrate, first implantation ions are implanted into the substrate, whereby micro-cavities are produced in a first partial region of the substrate. Furthermore, pre-amorphization ions are implanted into the substrate, whereby a second partial region of the substrate is at least partly amorphized, and whereby crystal defects are produced in the substrate. Furthermore, second implantation ions are implanted into the second partial region of the substrate. Furthermore, the substrate is heated, such that at least some of the crystal defects are eliminated using the second implantation ions. Furthermore, dopant atoms are implanted into the second partial region of the substrate, wherein the semiconductor element is formed using the dopant atoms.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: July 5, 2011
    Assignees: Infineon Technologies AG, IMEC VZW.
    Inventors: Luis-Felipe Giles, Thomas Hoffmann, Chris Stapelmann
  • Patent number: 7960243
    Abstract: A semiconductor device (10) is formed in a semiconductor layer (12). A gate stack (16,18) is formed over the semiconductor layer and comprises a first conductive layer (22) and a second layer (24) over the first layer. The first layer is more conductive and provides more stopping power to an implant than the second layer. A species (46) is implanted into the second layer. Source/drain regions (52) are formed in the semiconductor layer on opposing sides of the gate stack. The gate stack is heated after the step of implanting to cause the gate stack to exert stress in the semiconductor layer in a region under the gate stack.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: June 14, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Brian A. Winstead, Konstantin V. Loiko, Voon-Yew Thean
  • Patent number: 7943468
    Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: May 17, 2011
    Assignee: Intel Corporation
    Inventors: Giuseppe Curello, Ian R. Post, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark T. Bohr
  • Patent number: 7927975
    Abstract: Electronic apparatus, systems, and methods include a semiconductor layer bonded to a bulk region of a wafer or a substrate, in which the semiconductor layer can be bonded to the bulk region using electromagnetic radiation. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: February 4, 2009
    Date of Patent: April 19, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Nishant Sinha, Gurtej S. Sandhu, John Smythe
  • Patent number: 7915137
    Abstract: Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: March 29, 2011
    Assignee: Advanced Analogic Technologies, Inc.
    Inventor: Richard K. Williams
  • Patent number: 7897476
    Abstract: To provide an SOI substrate with an SOI layer that can be put into practical use, even when a substrate with a low allowable temperature limit such as a glass substrate is used, and to provide a semiconductor substrate formed using such an SOI substrate. In order to bond a single-crystalline semiconductor substrate to a base substrate such as a glass substrate, a silicon oxide film formed by CVD with organic silane as a source material is used as a bonding layer, for example. Accordingly, an SOI substrate with a strong bond portion can be formed even when a substrate with an allowable temperature limit of less than or equal to 700° C. such as a glass substrate is used. A semiconductor layer separated from the single-crystalline semiconductor substrate is irradiated with a laser beam so that the surface of the semiconductor layer is planarized and the crystallinity thereof is recovered.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: March 1, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Eiji Higa, Yoji Nagano, Tatsuya Mizoi, Akihisa Shimomura
  • Patent number: 7892939
    Abstract: The prevention of active area loss in the STI model is disclosed which results in an improved device performance in devices manufactured according to the process flow. The process generally shared among the multiple various embodiments inverts the current conventional STI structure towards a process flow where an insulator is patterned with tapered trenches. A segregation layer is formed beneath the surface of the insulator in the tapered trenches. The tapered trenches are then filled with a semiconductor material which is further processed to create a number of active devices. Therefore, the active devices are created in patterned dielectric instead of the STI being created in the semiconductor substrate of the active devices.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: February 22, 2011
    Assignee: Infineon Technologies AG
    Inventors: Roland Hampp, Manfred Eller, Jin-Ping Han, Matthias Lipinski
  • Patent number: 7883956
    Abstract: Methods of forming coplanar active regions and isolation regions and structures thereof are disclosed. One embodiment includes shallow-trench-isolation (STI) formation in a semiconductor-on-insulator (SOI) layer on a substrate of a semiconductor structure; and bonding a handle wafer to the STI and SOI layer to form an intermediate structure. The intermediate structure may have a single layer including at least one STI region and at least one SOI region therein disposed between the damaged substrate and the handle wafer. The method may also include cleaving the hydrogen implanted substrate and removing any residual substrate to expose a surface of the at least one STI region and a surface of the at least one SOI region. The exposed surface of the at least one STI region forms an isolation region and the exposed surface of the at least one SOI region forms an active region, which are coplanar to each other.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: February 8, 2011
    Assignee: International Business Machines Corporation
    Inventor: Huilong Zhu
  • Patent number: 7884000
    Abstract: A method for manufacturing SIMOX wafer, wherein roughness (Rms) of an SOI layer and roughness (Rms) of an interface between the SOI layer and a BOX layer can be reduced. The method includes forming a first ion-implanted layer containing highly concentrated oxygen within a wafer; forming a second ion-implanted amorphous layer; and a high temperature heat treatment, transforming the first and second ion-implanted layers into a BOX layer by holding the wafer at a temperature between 1300° C. or more and a temperature less than a silicon melting point in an atmosphere containing oxygen, wherein when a first dose amount in forming the first ion-implanted layer is set to 2×1017 to 3×1017 atoms/cm2, the first implantation energy set to 165 to 240 keV and a second dose amount in forming the second ion-implanted layer is set to 1x1014 to 1x1016 atoms/cm2.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: February 8, 2011
    Assignee: Sumco Corporation
    Inventors: Yoshiro Aoki, Riyuusuke Kasamatsu, Yukio Komatsu
  • Patent number: 7838387
    Abstract: A silicon wafer includes a principal face for forming electronic devices; an end region; and a tapered region which is located between the principal face and the end region, in which the thickness of the silicon wafer is gradually reduced, and which has a slope that makes an angle of greater than zero degree and less than 9.5 degrees or an angle of greater than 19 degrees with the principal face. An SOI wafer prepared by forming a buried oxide layer in a silicon wafer includes a principal face, end region, and tapered region that are substantially the same as those described above. A method for manufacturing an SOI wafer includes the steps of implanting oxygen ions into a silicon wafer; and heat-treating the resulting silicon wafer such that a buried oxide layer is formed in the silicon wafer.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: November 23, 2010
    Assignee: Sumco Corporation
    Inventors: Eiji Kamiyama, Seiichi Nakamura, Tetsuya Nakai
  • Patent number: 7825016
    Abstract: In a method for fabricating a semiconductor element in a substrate, micro-cavities are formed in the substrate. Furthermore, doping atoms are implanted into the substrate, whereby crystal defects are produced in the substrate. The substrate is heated, so that at least some of the crystal defects are eliminated using the micro-cavities, and the semiconductor element is formed using the doping atoms.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: November 2, 2010
    Assignee: Infineon Technologies AG
    Inventor: Luis-Felipe Giles
  • Patent number: 7820524
    Abstract: A manufacturing method of an SOI substrate which possesses a base substrate having low heat resistance and a very thin semiconductor layer having high planarity is demonstrated. The method includes: implanting hydrogen ions into a semiconductor substrate to form an ion implantation layer; bonding the semiconductor substrate and a base substrate such as a glass substrate, placing a bonding layer therebetween; heating the substrates bonded to each other to separate the semiconductor substrate from the base substrate, leaving a thin semiconductor layer over the base substrate; irradiating the surface of the thin semiconductor layer with laser light to improve the planarity and recover the crystallinity of the thin semiconductor layer; and thinning the thin semiconductor layer. This method allows the formation of an SOI substrate which has a single-crystalline semiconductor layer with a thickness of 100 nm or less over a base substrate.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: October 26, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Akihisa Shimomura, Tatsuya Mizoi, Eiji Higa, Yoji Nagano
  • Patent number: RE43450
    Abstract: An object of the present invention is to provide a technology of reducing a nickel element in the silicon film which is crystallized by using nickel. An extremely small amount of nickel is introduced into an amorphous silicon film which is formed on the glass substrate. Then this amorphous silicon film is crystallized by heating. At this time, the nickel element remains in the crystallized silicon film. Then an amorphous silicon film is formed on the surface of the silicon film crystallized with the action of nickel. Then the amorphous silicon film is further heat treated. By carrying out this heat treatment, the nickel element is dispersed from the crystallized silicon film into the amorphous silicon film with the result that the nickel density in the crystallized silicon film is lowered.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: June 5, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Akiharu Miyanaga, Satoshi Teramoto