Abstract: A method is provided for fabricating thin membrane structures in localized surface regions of a single crystal substrate. In the method, ion implantation masks are patterned on the surface of the single crystal substrate with openings that define the localized surface regions. Foreign ions are implanted through the openings into the single crystal substrate to modify the chemical and/or structural properties of subsurface layers at predetermined depths underneath super layers of material. These subsurface layers are removed by selective etching. The removal of the subsurface layers leaves the super layers of material intact as membrane structures on top of openings or channels corresponding to the space of the removed subsurface layers. At least one portion or end of a membrane structure remains attached to the single crystal substrate.

Abstract: The present invention provides a method for forming low-defect density changed-orientation Si by amorphization/templated recrystallization (ATR) processes in which regions of Si having a first crystal orientation are amorphized by ion implantation and then recrystallized into the orientation of a template layer having a different orientation. More generally, the invention relates to the high temperature annealing conditions needed to eliminate the defects remaining in Si-containing single crystal semiconductor materials formed by ion-implant-induced amorphization and templated recrystallization from a layer whose orientation may be the same or different from the amorphous layer's original orientation. The key component of the inventive method is a thermal treatment for minutes to hours in the the temperature range 1250-1330° C. to remove the defects remaining after the initial recrystallization anneal.

Abstract: A semiconductor memory cell structure having 4F2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the substrate over the active region and a capacitor is formed on the semiconductor post. A vertical access transistor having a gate structure formed on the semiconductor post is configured to electrically couple the respective memory cell capacitor to the active region when accessed.

Abstract: The present invention provides an epitaxial imprinting process for fabricating a hybrid substrate that includes a bottom semiconductor layer; a continuous buried insulating layer present atop said bottom semiconductor layer; and a top semiconductor layer present on said continuous buried insulating layer, wherein said top semiconductor layer includes separate planar semiconductor regions that have different crystal orientations, said separate planar semiconductor regions are isolated from each other. The epitaxial printing process of the present invention utilizing epitaxial growth, wafer bonding and a recrystallization anneal.

Abstract: According to the present invention, an oxide film with the film quality almost equivalent to that of the thermal oxide can be formed by the low-temperature treatment. After removing an insulator on the active region of the substrate which constitutes a semiconductor wafer, an insulator made of, for example, silicon oxide is deposited on the main surface of the semiconductor wafer by the low pressure CVD method. This insulator is a film to form a gate insulator of MISFET in a later step. Subsequently, a plasma treatment is performed in an atmosphere containing oxygen (oxygen plasma treatment) to the insulator in the manner as schematically shown by the arrows. By so doing, the film quality of the insulator formed by the CVD method can be improved to the extent almost equivalent to that of the insulator formed of the thermal oxide.

Abstract: A microelectronics device including a semiconductor device located at least partially over a substrate, a bombarded area located at least partially over the substrate and adjacent the semiconductor device, and a bombarded attenuator interposing the semiconductor device and the bombarded area.

Abstract: A method of forming an SOI semiconductor substrate and the SOI semiconductor substrate formed thereby, is provided. The method includes forming sequentially buried oxide, diffusion barrier and SOI layers on a semiconductor substrate. The diffusion barrier layer is formed by an insulating layer having a lower impurity diffusion coefficient as compared with the buried oxide layer. The diffusion barrier layer serves to prevent impurities implanted into the SOI layer from being diffused into the buried oxide layer or the semiconductor substrate.

Abstract: An ion implanter having a source, a workpiece support and a transport system for delivering ions from the source to an ion implantation chamber that contains the workpiece support. The implanter includes one or more removable inserts mounted to an interior of either the transport system or the ion implantation chamber for collecting material entering either the transport system or the ion implantation chamber due to collisions between ions and the workpiece within the ion implantation chamber during ion processing of the workpiece. A temperature control coupled to the one or more removable inserts for maintaining the temperature of the insert at a controlled temperature to promote formation of a film on said insert during ion treatment due to collisions between ions and said workpiece.

Abstract: A method of filling a gap defined by adjacent raised features on a substrate includes providing a flow of a silicon-containing processing gas to a chamber housing the substrate and providing a flow of an oxidizing gas to the chamber. The method also includes depositing a first portion of a film as a substantially conformal layer in the gap by causing a reaction between the silicon-containing processing gas and the oxidizing gas. Depositing the conformal layer includes varying over time a ratio of the (silicon-containing processing gas):(oxidizing gas) and regulating the chamber to a pressure in a range from about 200 torr to about 760 torr throughout deposition of the conformal layer. The method also includes depositing a second portion of the film as a bulk layer.

Abstract: Enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods are provided for implementing enhanced SOI BOX structures. An oxygen implant step is performed from a backside into a thinned silicon substrate layer. An anneal step forms thick buried oxide (BOX) regions from oxygen implants in the silicon substrate layer. The oxygen implant step forms an isolated region near the oxygen implants. A backside implant step selectively dopes the isolated region for forming a backgate for an SOI device being formed including a selected one of anti-fuse (AF) devices, and SOI transistors including PFET and NFET devices.

Abstract: A method for producing a semiconductor device with an SOI substrate having a support substrate 1 and a semiconductor layer 3 that interpose a first insulating film 2 between them includes the following steps. An element region and an element-separation region 4 are formed in the semiconductor layer 3. A gate insulating film 5 is formed on the semiconductor layer 3. A gate electrode 6 is formed on the gate insulating film 5. A second insulating film 7 is formed. The gate insulating film 5 is removed. First thickness adjustment is performed. Ion implantation introducing low concentration impurities is performed on the thickness-adjusted semiconductor layers 3 and 8. A first sidewall portion 7a is formed on the side surfaces of the gate electrode 6. A second sidewall portion 10a is formed on the side surfaces of the first sidewall portion 7a.

Abstract: The present invention provides a method of fabricating a patterned silicon-on-insulator substrate which includes dual depth SOI regions or both SOI and non-SOI regions within the same substrate. The method of the present invention includes forming a silicon mask having at least one opening on a surface of Si-containing material, recessing the Si-containing material through the at least one opening using an etching process to provide a structure having at least one recess region and a non-recessed region, and forming a first buried insulating region in the non-recessed region and a second buried insulating region in the recessed region. In accordance with the present invention, the first buried insulating region in the non-recessed region is located above the second buried isolation region in the recessed region. A lift-off step can be employed to remove the first buried insulating region and the material that lies above to provide a substrate containing both SOI and non-SOI regions.

Abstract: The present invention provides a method for generating silicon-on-insulator (SOI) wafers that exhibit a high electrical resistivity. In one embodiment of a method according to the teachings of the invention, a SIMOX process is sandwiched between two Full Oxygen Precipitation (FOP) cycles that sequester interstitial oxygen present in the substrate in the form of oxide precipitates, thereby enhancing the electrical resistivity of the susbtrate.

Abstract: This invention concerns a non-volatile memory device with a polarizable layer. The apparatus concerns a substrate, a buried oxide layer within the substrate, and a polarizable layer within the substrate. The polarizable layer is formed in a buried oxide layer of a silicon-on-insulator substrate for the fabrication of non-volatile memory. The process of creating the polarizable layer comprises implanting, through the active silicon layer, Si ions into the buried oxide layer at an ion implantation energy selected so that the implanted ion has its peak concentration between 5–50 nm from the silicon/buried oxide interface. The implantation step can occur while externally heating the silicon-on-insulator substrate at a temperature between 25–300 degrees Celsius. An annealing step may be completed to repair any damage the implantation may have created in the silicon-on-insulator substrate.

Abstract: A semiconductor substrate is provided, and at least one first mask is formed above the semiconductor substrate. The first mask has a plurality of thicknesses and blocks at least one semi-insulating region. A second mask is thereafter formed on a surface of the semiconductor substrate. The second mask covers the semi-insulating region. The semi-insulating region is implanted with a high energy beam of particles by utilizing the second mask and the first mask as particle hindering masks. Finally, the second mask is removed.

Abstract: Flash lamp apparatuses that generate electromagnetic radiation with wavelengths greater than and/or less than a defined range of wavelengths are disclosed.

Abstract: The semiconductor device has a low-resistance layer provided under the interconnection extending from the signal input to a gate of MOSFET. The low-resistance layer decreases the substrate resistance and the noise characteristic of the semiconductor device can also be improved. The low-resistance layer can be provided on a surface of the substrate or a polysilicon interconnection.

Abstract: A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implanted-ion rich region in the Si-containing substrate. The implanted-ion rich region has a sufficient ion concentration such that during a subsequent anneal at high temperatures a barrier layer that is resistant to Ge diffusion is formed. Next, a Ge-containing layer is formed on a surface of the Si-containing substrate, and thereafter a heating step is performed at a temperature which permits formation of the barrier layer and interdiffusion of Ge thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer.

Abstract: A method for fabricating a strained silicon film to a silicon on insulation (SOI) wafer. A layer of oxide is deposited onto a wafer that has a stack structure of a first base substrate, a layer of relaxed film-and a second layer of strained film. The SOI wafer has a stack structure of a second base substrate and a layer of oxidized film. The SOI wafer is attached to the wafer and is heated at a first temperature. This causes a silicon dioxide (SiO2) dangling bond to form on the second base substrate of the SOI wafer, transferring the strained film from one wafer to the other.

Abstract: A method utilizing in-place bonding and amorphization/templated recrystallization (ATR) is provided for making bulk and semiconductor-on-insulator substrates having coplanar semiconductor layers of different crystallographic orientations. First and second semiconductor layers having different orientations are bonded to opposite sides of a sacrificial spacer layer. Selected areas in one of the semiconductor layers are amorphized; in-place bonding is then performed in a wet etch solution to remove the sacrificial layer and leave the semiconductor layers bonded to each other. The amorphized regions are recrystallized across the bonded interface, using the semiconductor on the non-amorphized side of the bonded interface as a template.

Abstract: A method of forming substrates, e.g., silicon on insulator, silicon on silicon. The method includes providing a donor substrate, e.g., silicon wafer. The method also includes forming a cleave layer on the donor substrate that contains the cleave plane, the plane of eventual separation. In a specific embodiment, the cleave layer comprising silicon germanium. The method also includes forming a device layer (e.g., epitaxial silicon) on the cleave layer. The method also includes introducing particles into the cleave layer to add stress in the cleave layer. The particles within the cleave layer are then redistributed to form a high concentration region of the particles in the vicinity of the cleave plane, where the redistribution of the particles is carried out in a manner substantially free from microbubble or microcavity formation of the particles in the cleave plane. That is, the particles are generally at a low dose, which is defined herein as a lack of microbubble or microcavity formation in the cleave plane.

Abstract: This invention relates to a method of fabricating a bonded product comprising at least two components that are bonded together, the method comprising the steps of: a) bringing the components together; and b) heating the components; wherein at least one of the components comprises a nanomaterial and wherein steps (a) and (b) are performed in such a manner that the components are bonded together by heating at least part of the nanomaterial. The method allows the components to be welded together at lower temperatures than for prior art methods. The method also provides a more reliable form of bonding and improves the strength of the bond formed.

Abstract: An ion implantation system for producing silicon wafers having relatively low defect densities, e.g., below about 1×106/cm2, includes a fluid port in the ion implantation chamber for introducing a background gas into the chamber during the ion implantation process. The introduced gas, such as water vapor, reduces the defect density of the top silicon layer that is separated from the buried silicon dioxide layer.

Abstract: A method of fabricating a chalcogenide random access memory (CRAM) is provided. The method is to provide a substrate having a bottom electrode thereon and then form a chalcogenide film and a patterned mask corresponding to the bottom electrode sequentially over the substrate. Thereafter, using the patterned mask, an ion implantation is performed to convert a portion of the chalcogenide film into a modified region while the chalcogenide film underneath the patterned mask is prevented from receiving any dopants and hence is kept as a non-modified region. The modified region has a lower conductivity than the non-modified region. After that, the patterned mask is removed and then a top electrode is formed over the non-modified region. Utilizing the ion implantation as a modifying treatment, the contact area between the chalcogenide film and the bottom electrode is decreased and the operating current of the CRAM is reduced.

Abstract: A semiconductor configuration has a base layer made of semiconductor material and formed, in particular, by a substrate. An insulation layer is arranged above the base layer, and a layer made of monocrystalline silicon adjoins the insulation layer. A passivating substance is present, with the formation of Si—X bonds, in the region of the interface between the insulation layer and the monocrystalline silicon layer. The bond energy of the Si—X bond is greater than the bond energy of an Si—H bond.

Abstract: A semiconductor device includes a single crystal substrate and a dielectric layer overlying the substrate. The dielectric layer includes at least one opening having a first portion and an overlying second portion. The first portion has a depth and width, such that an aspect ratio of the depth to width is greater than one. The semiconductor device further includes a first material having a first portion and a second portion, the first portion of the first material filling the first portion of the at least one opening. Defects for relaxing strain at an interface between the first material and the substrate material exist only within the first portion of the first material due to the aspect ratio being greater than one. The second portion of the first material is substantially defect free. Furthermore, the second portion of the first material and an overlying second material different than the first material fill the overlying second portion of the at least one opening.

Abstract: A method for forming a reliable and ultra-thin oxide layer, such as a gate oxide layer of an MOS transistor, comprises an annealing step immediately performed prior to oxidizing a substrate. The annealing step is performed in an inert gas ambient to avoid oxidation of the semiconductor surface prior to achieving a required low oxidizing temperature. Preferably, the annealing step and the oxidizing step are carried out as an in situ process, thereby minimizing the thermal budget of the overall process.

Abstract: A method is disclosed for forming a semiconductor wafer having a strained Si or SiGe layer on an insulator layer. The method produces a structure having a SiGe buffer layer between the insulator layer and the strained Si or SiGe layer, but eliminates the need for Si epitaxy after bonding. The method also eliminates interfacial contamination between strained Si and SiGe buffer layer, and allows the formation of Si/SiGe layers having a total thickness exceeding the critical thickness of the strained Si layer.

Abstract: A method of fabricating substrates while minimizing loss of starting material of an ingot, wherein a layer is transferred onto a support. The technique includes forming a flat front face on a raw ingot of material, implanting atomic species through the front face to a controlled mean implantation depth to create a zone of weakness that defines a top layer of the ingot, bonding a support to the front face of the ingot, wherein the support has a surface area that is smaller than a surface area of the front face of the ingot, and detaching from the ingot at the zone of weakness that portion of the top layer that is bonded to the support to form the substrate.

Abstract: The invention relates to discrete, spaced-apart ferroelectric polymer memory device embodiments. The ferroelectric polymer memory device is fabricated by spin-on polymer processing and etching using photolithographic technology. The size of the discrete, spaced-apart ferroelectric polymer structures may be tied to a specific photolithography minimum feature dimension. The invention also relates to a process for making embodiments of a polymer memory device that includes discrete, spaced-apart ferroelectric polymer structures. The discrete, spaced-apart ferroelectric polymer structures may have a minimum feature that is tied to the current photolithography that may reduce the voltage and increase the switching speed.

Abstract: An N?-type silicon substrate (1) has a bottom surface and an upper surface which are opposed to each other. In the bottom surface of the N?-type silicon substrate (1), a P-type impurity diffusion layer (3) of high concentration is entirely formed by diffusing a P-type impurity. In the upper surface of the N?-type silicon substrate (1), a P-type isolation region (2) is partially formed by diffusing a P-type impurity. The P-type isolation region (2) has a bottom surface reaching an upper surface of the P-type impurity diffusion layer (3). As viewed from the upper surface side of the N?-type silicon substrate (1), the P-type isolation region (2) is formed, surrounding an N? region (1a) which is part of the N?-type silicon substrate (1). The N? region (1a) surrounded by the P-type isolation region (2) is defined as an element formation region of the N?-type silicon substrate (1).

Abstract: Disclosed herein is a method of providing improved electrical isolation in a separation by ion implanted oxide (SIMOX) process of making an SOI wafer. The method includes implanting ions into a substrate in a base dose implant conducted at a first energy level, implanting ions into the substrate at a second energy level in a second implant while the substrate is held at room temperature, and annealing the substrate to cause the implanted ions to be redistributed throughout the buried oxide (BOX) layer of the SOI wafer.

Abstract: A method is for commercially producing by the SIMOX technique a perfect partial SOI structure avoiding exposure of a buried oxide film through the surface thereof and forming no step between an SOI region and a non-SOI region.

Abstract: An SOI semiconductor device includes at least an SOI substrate including an insulating film and a semiconductor layer formed on the insulating film; and an active semiconductor element formed on the semiconductor layer. The active semiconductor element is formed in an element formation region surrounded by an isolating region for isolating the semiconductor layer in a form of an island. A gettering layer containing a high concentration impurity is formed in a portion of the semiconductor layer excluding the element formation region in which the active semiconductor element is formed, and the gettering layer is not formed in the element formation region in which the active semiconductor element is formed.

Abstract: A method for forming a semiconductor on insulator structure includes forming a semiconductor layer on an insulating substrate, where the substrate is a different material than the semiconductor layer, and has a coefficient of thermal expansion substantially equal to that of the semiconductor layer. The semiconductor layer can also be formed having a thickness such that, it does not yield due to temperature-induced strain at device processing temperatures. A silicon layer bonded to a silicon oxycarbide glass substrate provides a silicon on insulator wafer in which circuitry for electronic devices is fabricated.

Abstract: The present invention provides a method for generating silicon-on-insulator (SOI) wafers that exhibit a high electrical resistivity. In one embodiment of a method according to the teachings of the invention, a SIMOX process is sandwiched between two Full Oxygen Precipitation (FOP) cycles that sequester interstitial oxygen present in the substrate in the form of oxide precipitates, thereby enhancing the electrical resistivity of the susbtrate.

Abstract: The present invention provides a SOI wafer produced by an ion implantation delamination method wherein a width of a SOI island region in a terrace portion generated in an edge portion of the SOI wafer where a surface of a base wafer is exposed is narrower than 1 mm and a density of pit-shaped defects having a size of 0.19 &mgr;m or more existing in a surface of a SOI layer detected by a LPD inspection is 1 counts/cm2 or less, and also provides a method for producing the SOI wafer. Thereby, there is provided a SOI wafer produced by an ion implantation delamination method wherein generation of SOI islands generated in delamination can be suppressed and a defect density of LPDs existing in a surface of the SOI wafer can be reduced, and a method for producing the same, so that device failure can be reduced.

Abstract: One aspect of this disclosure relates to a method for straining a transistor body region. In various embodiments, oxygen ions are implanted to a predetermined depth in a localized region of a semiconductor substrate, and the substrate is annealed. Oxide growth within the semiconductor substrate forms a local oxide region within the semiconductor substrate. A portion of the substrate forms a semiconductor layer over the local oxide region. In various embodiments, the semiconductor layer is an ultra-thin semiconductor layer having a thickness of approximately 300 Å or less. The oxide growth strains the semiconductor layer. An active region, including the body region, of the transistor is formed in the strained semiconductor layer. Other aspects are provided herein.

Abstract: The aim of the invention is a method for producing a layer (2) of a first material embedded in a substrate (1) comprising at least one second material. The method comprises the following stages: formation in the substrate (1), at the level of the desired embedded layer, of a layer of microcavities intended to serve as centers of nucleation to produce said first material in said second material, formation of precipitate embryos from the nucleation centers formed, the precipitate embryos corresponding to the first material, growth of the precipitates from the embryos through species concentration corresponding to the first material and carried to the microcavity layer.

Abstract: A method of fabricating a silicon-on-insulator (SOI) having a superficial Si-containing layer that has a reduced number of tile and divot defects is provided. The method includes the steps of: implanting oxygen ions into a surface of a Si-containing substrate, the implanted oxygen ions having a concentration sufficient to form a buried oxide region during a subsequent annealing step; and annealing the substrate containing implanted oxygen ions under conditions wherein the implanted oxygen ions form a buried oxide region which electrically isolates a superficial Si-containing layer from a bottom Si-containing layer. Moreover, the annealing conditions employed are capable of reducing the number of tile or divot defects present in the superficial Si-containing layer so as to allow optical detection of any other defect that has a lower density than the tile or divot defect. The present invention also relates to the SOI substrate that is produced using the inventive method.

Abstract: The present invention provides a method for creation of high quality semiconductor-on-insulator structures, e.g., silicon-on-insulator structures, using implantation of sub-stoichiometric doses of oxygen at multiple energies. The method employs sequential steps of ion implantation and high temperature annealing to produce structures with a top silicon layer having a thickness ranging from 10-250 nm and a buried oxide layer having a thickness 30-300 nm. The buried oxide layer has a breakdown field greater than 5 MV/cm. Further, the density of silicon inclusions in the BOX region is less than 2×107 cm−2. The process of the invention can be used to create an entire SOI wafer, or be used to create patterned SOI, regions where SOI regions are integrated with non-SOI regions.

Abstract: This invention discloses a method for fabricating SOI material, incorporating an amorphous process introduced by ion implantation in the conventional SIMOX methods, which enhances diffusion of various atoms in the amorphous region in annealing process. It realizes under a lower temperature annealing to eliminate threading dislocations and other crystal defects in the top silicon layer and silicon islands, pinholes and other silicon segregation products in the buried oxide layer and fabricate high quality of SOI material. Another method for forming SOI material is also described, incorporating an amorphous process introduced by ion implantation in the SIMNI or SIMON methods. It forms amorphous buried nitride or oxynitride layer, a top single crystal silicon layer and a sharp interface between the top layer and the buried layer.

Abstract: The present invention provides a SIMOX substrate produced by employing an oxygen ion implantation amount in a low dose range, which substrate is a high quality SOI substrate having an increased thickness of a BOX layer, and a method of producing the same, and more specifically, provides a method of producing a SIMOX substrate wherein a buried oxide layer and a surface silicon layer are formed by applying the implantation of oxygen ions in a silicon substrate and a high temperature heat treatment thereafter, characterized by: forming the buried oxide layer through applying a high temperature heat treatment after an oxygen ion implantation; then applying an additional oxygen ion implantation so that the peak position of the distribution of implanted oxygen is located at a portion lower than the interface between the buried oxide layer, already formed, and the substrate thereunder; and then applying another high temperature heat treatment, and a SIMOX substrate produced by said method having a surface silicon la

Abstract: A method for forming a semiconductor-on-insulator (SOI) substrate is described incorporating the steps of heating a substrate, implanting oxygen into a heated substrate, cooling the substrate, implanting into a cooled substrate and annealing. The steps of implanting may be at several energies to provide a plurality of depths and corresponding buried damaged regions. Prior to implanting, the step of cleaning the substrate surface and/or forming a patterned mask thereon may be performed. The invention overcomes the problem of raising the quality of buried oxide and its properties such as surface roughness, uniform thickness and breakdown voltage Vbd.

Abstract: A SIMOX substrate having a buried oxide layer and a surface single crystal silicon layer formed therein is produced by a method which comprises implanting oxygen ions into a silicon single crystal substrate and subsequently performing a heat treatment at an elevated temperature on the substrate. The method is characterized by performing the former stage of the heat treatment at a temperature of not lower than 1150° C. and lower than the melting point of single crystal silicon in an atmosphere obtained by adding oxygen under a partial pressure of not more than 1% to an inert gas and subsequently performing at least part of the latter stage of the heat treatment by increasing the partial pressure of oxygen within a range in which no internal oxidation is suffered to occur in the buried oxide layer. It can also be prepared by performing the former stage of the high temperature heat treatment at a temperature of not lower than 1150° C.

Abstract: A semiconductor substrate of the present invention is a DSP wafer or Semi-DSP wafer (FIG. 2) having a flatness of an SFQR value ≦70 (nm) and containing boron at a concentration not lower than 5×1016 (atoms/cm3) nor higher than 2×1017 (atoms/cm3) within 95% or more of rectangular regions of 25×8 (mm2) arranged on a front face of the substrate. Specifically, a silicon crystal layer by an epitaxial growth is formed on a front face of a silicon substrate having the above substrate boron concentration.

Abstract: Non-alloyed, low resistivity contacts for semiconductors using Group III-V and Group II-VI compounds and methods of making are disclosed. Co-implantation techniques are disclosed.

Abstract: There is provided a process for fabrication of a SIMOX substrate wherein oxygen ions are implanted into a single crystal silicon substrate and then subjected to a high-temperature heat treatment to form a buried oxide layer and a surface single crystal silicon layer, wherein the single crystal silicon substrate used has a mean resistivity of 100 &OHgr;cm or greater, and there is conducted a step of maintaining a temperature of from 800° C. to 1250° C. for a predetermined time in the final stage of the high-temperature heat treatment, as well as a SIMOX substrate wherein the mean resistivity of the substrate obtained by the process is 100 &OHgr;cm or greater.

Abstract: A silicon-on-insulator (SOI) device and a method for manufacturing the same includes a substrate, which includes a base layer, a buried oxide layer, and a semiconductor layer, and an isolation layer which is formed in a trench that defines an active region on the semiconductor layer. The trench comprises a first region having a depth smaller than the thickness of the semiconductor layer and a second region having a depth as much as the thickness of the semiconductor layer. The isolation layer includes an oxide layer and a nitride liner that are sequentially formed along the surface of the trench and a dielectric layer that fills the trench.

Abstract: A method of forming a semiconductor on insulator structure in a monolithic semiconducting substrate with a bulk semiconductor structure. A first portion of a surface of the monolithic semiconducting substrate is recessed without effecting a second portion of the surface of the monolithic semiconducting substrate. An insulator precursor species is implanted beneath the surface of the recessed first portion of the monolithic semiconducting substrate, and a trench is etched around the implanted and recessed first portion of the monolithic semiconducting substrate. The insulator precursor species is activated to form an insulator layer beneath the surface of the recessed first portion of the monolithic semiconducting substrate. The semiconductor on insulator structure is formed in the first portion of the monolithic semiconducting substrate, and the bulk semiconductor structure is formed in the second portion of the monolithic semiconducting substrate.