Abstract: A crossbar structure includes a first layer or layers including first p-type regions and first n-type regions, a second layer or layers including second p-type regions and second n-type regions, and a resistance programmable material formed between the first layer(s) and the second layer(s), wherein the first layer(s) and the second layer(s) include first and second intersecting wiring portions forming a crossbar array.

Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

Abstract: A method for manufacturing a semiconductor wafer electrostatic clamp, comprising providing a mounting plate, forming an insulative layer on an insulating portion of the mounting plate, forming a first electrode on a first portion of the mounting plate, forming a second electrode on a second portion of the mounting plate, forming a first segment having a first conductivity over the first electrode, forming a first region having a second conductivity over the first segment that creates an n-p type composite, forming a second segment having a third conductivity formed over the over the second electrode, forming a second region having a fourth conductivity formed over the second region that creates an p-n type composite.

Abstract: A method of producing an element separation structure includes the steps of: forming a first thermal oxide film on the substrate; forming a silicon nitride film on the first thermal oxide film; removing the first thermal oxide film and the silicon nitride film in an element separation structure forming region; forming a groove portion in the element separation structure forming region; forming a groove portion oxide film in the groove portion; forming a pre-filling oxide film for filling the groove portion; removing the pre-filling oxide film; forming a resist layer on the silicon nitride film and the pre-filling oxide film; forming a resist mask on the element separation structure forming region; removing the silicon nitride film and the first thermal oxide film; forming a second thermal oxide film on the substrate; and removing the second thermal oxide film and leveling the pre-filling oxide film to form a filling portion.

Abstract: A method of making an energy conversion device includes forming a plurality of pores within a substrate and forming a junction region within each of the plurality of pores. Each of the junction regions has a depletion region and each of the plurality of pores defines an opening size in the substrate and a spacing from adjacent pores so that the depletion regions of each of the pores is at least substantially in contact with the depletion region of the pores which are adjacent.

Abstract: By forming an additional doped region with increased junction depth at areas in which contact regions may connect to drain and source regions, any contact irregularities may be embedded into the additional doped region, thereby reducing the risk for leakage currents or short circuits between the drain and source region and the well region that may be conventionally caused by the contact irregularity. Moreover, additionally or alternatively, the surface topography of the semiconductor region and the adjacent isolation trench may be modified prior to the formation of metal silicide regions and contact plugs to enhance the lithography procedure for forming respective contact openings in an interlayer dielectric material. For this purpose, the isolation trench may be brought to an equal or higher level compared to the adjacent semiconductor region.

Abstract: A method for manufacturing a semiconductor device includes forming an insulation film over a semiconductor substrate having a conduction layer; forming a trench pattern over the insulation film; etching an upper portion of the insulation film by using the trench pattern as a mask to form a trench; removing the trench pattern; forming a spacer film over the insulation film having the trench; etching the space film to form a spacer by using a blanket etching process, the spacer remaining over an edge of an inner portion of the trench; etching the insulation film to form a via hole by using as a mask the spacer; completely removing the spacer; forming a barrier film over sidewalls of the trench and the via hole; and forming a metal line with which fills inner portions of the trench and the via hole.

Abstract: A non-gated diode structure of a silicon-on-insulator, having a silicon-on-insulator substrate, a pair of isolating structures, a first type doped region and a second type doped region. The silicon-on-insulation substrate has a stack of a substrate, an insulation layer and a silicon layer. The isolating structures are located in the silicon layer to define a well region. The first and second type doped regions are located in the well and are adjacent to the isolating structures. Such a non-gated diode structure can be applied to an electrostatic discharge protection circuit to increase the electrostatic discharge protection voltage or current. In addition, a fabrication method of the non-gated diode is also introduced. This non-gated diode can be also fabricated in the general bulk CMOS process, and used in the on-chip ESD protection circuits.

Abstract: The present invention relates to a semiconductor processing system that employs infrared-based thermopile detector for process control, by analyzing a material of interest, based on absorption of infrared light at a characteristic wavelength by such material. Specifically, an infrared light beam is transmitted through a linear transmission path from an infrared light source through a sampling region containing material of interest into the thermopile detector. The linear transmission path reduces the risk of signal loss during transmission of the infrared light. The transmission path of the infrared light may comprise a highly smooth and reflective inner surface for minimizing such signal loss during transmission.

Abstract: Methods of de-fluorinating a wafer surface after damascene processing and prior to photoresist removal are disclosed, as is a related structure. In one embodiment, the method places the wafer surface in a chamber and exposes the wafer surface to a plasma from a source gas including at least one of nitrogen (N2) and/or hydrogen (H2) at a low power density or ion density. The exposing step removes the chemisorbed and physisorbed fluorine residue present on the wafer surface (and chamber), and improves ultra low dielectric (ULK) interconnect structure robustness and integrity. The exposing step is operative due to the efficacy of hydrogen and nitrogen radicals at removing fluorine-based species and also due to the presence of a minimal amount of ion energy in the plasma. The low power density nitrogen and/or hydrogen-containing plasma process enables negligible ash/adhesion promoter interaction and reduces integration complexity during dual damascene processing of low-k OSG-based materials.

Abstract: A semiconductor device has a semiconductor substrate of a first conductivity; and a first electrode formation region and a second electrode formation region formed adjacent to an inner surface of the semiconductor substrate. The first electrode formation regions and the second electrode formation regions are isolated from each other via an element isolation region. An upper first-type impurity layer and a lower first-type impurity layer are formed in one of the first electrode formation region and the second electrode formation region, the lower first-type impurity layer has a different first-type impurity concentration from the upper first-type impurity layer and is formed under the upper first-type impurity layer. A second-type impurity layer and a first-type impurity layer are formed in the other electrode formation region and the first-type impurity layer is formed under a part of the second-type impurity layer having second-type impurities.

Abstract: Disclosed is an etching method for semiconductor processing by which a pattern loading phenomenon is reduced. First, plasma is generated while setting a bias power applied to a wafer to zero and applying a source power. After a predetermined time period, an etching process is implemented onto a predetermined layer formed on the wafer by setting the bias power to a predetermined value. Since by-products generated during preceding etching processes can be readily removed during an etching using plasma, an etching process change due to a difference of pattern densities can be reduced. In addition, a progressive pattern loading generated as the number of processed wafers increase, can be prevented.

Abstract: A method of forming retrograde n-wells and p-wells. A first mask is formed on the substrate and the n-well implants are carried out. Then the mask is thinned, and a deep p implant is carried out with the thinned n-well mask in place. This prevents Vt shifts in FETs formed in the n-well adjacent the nwell-pwell interface. The thinned mask is then removed, a p-well mask is put in place, and the remainder of the p-well implants are carried out.

Abstract: An edge termination is produced that is capable of handling high voltages. The edge termination is produced in a base material wafer that is produced in accordance with the principle of lateral charge compensation. The edge termination is formed in the base material wafer by implanting a rapidly diffusing dopant. Preferred dopants are selenium and sulfur. The high-voltage withstand strength is effected by a resulting doping profile which increases towards the edge termination.

Abstract: The dynamic random access memory (DRAM) cells in a semiconductor chip are isolated from the peripheral circuitry by forming the DRAM cells directly in the substrate while the peripheral and other functional circuits are formed in wells that are isolated from the substrate. In addition to providing isolation, the placement of the DRAM cells also reduces the leakage current in the cells, thereby increasing the time that a DRAM cell can hold a charge without being refreshed.

Abstract: A device and method for fabricating a gate structure are disclosed. A first conductive material is deposited in a trench formed in a substrate and the first conductive material is recessed to a level below a top surface of the substrate in the trench. A dielectric layer is conformally deposited in contact with the first conductive material in the trench and in contact with sidewalls of the trench. A hole is formed in the dielectric layer to expose the first conductive layer, and the hole is filled with a conductive material. A gate stack is formed over the trench such that an electrical connection is made to the first conductive layer in the trench by employing the conductive material through the dielectric layer.

Abstract: It is an object to obtain a semiconductor device comprising a channel stop structure which is excellent in an effect of stabilizing a breakdown voltage and a method of manufacturing the semiconductor device. A silicon oxide film (2) is formed on an upper surface of an N−-type silicon substrate (1). An N+-type impurity implantation region (4) is formed in an upper surface (3) of the N−-type silicon substrate (1) in a portion exposed from the silicon oxide film (2). A deeper trench (5) than the N+-type impurity implantation region (4) is formed in the upper surface (3) of the N−-type silicon substrate (1). A silicon oxide film (6) is formed on an inner wall of the trench (5). A polysilicon film (7) is formed to fill in the trench (5). An aluminum electrode (8) is formed on the upper surface (3) of the N−-type silicon substrate (1).

Abstract: A device and a method are provided for isolating a circuit well from a substrate of the same conductivity type. In particular, an integrated circuit is provided which includes a circuit well arranged over a semiconductor substrate with no layer of opposite conductivity type arranged between the well and the substrate. The integrated circuit may further include a pair of isolation wells extending along opposite lateral boundaries of the circuit well. The isolation wells and circuit well may be adapted such that a single continuous depletion region underlying the circuit well may be formed upon application of an isolation voltage between the substrate and the pair of isolation wells. The formation of such a depletion region may beneficially isolate the circuit well from the underlying substrate.

Abstract: The invention relates to a phase-change memory device that uses SOI in a chalcogenide volume of memory material. Parasitic capacitance, both vertical and lateral, are reduced or eliminated in the inventive structure.

Abstract: Techniques to isolate noise-sensitive circuits from noise generated by nearby circuits. In one design, a quiet region is formed on a die when surrounded by a deep n-well formed on top of a p-type substrate. The deep n-well is heavily doped n-type and forms a depletion region at the junction with the p-type substrate. The depth and width of the depletion region is dependent on the doping concentration of the deep n-well and the amount of reverse bias voltage applied to the deep n-well. In general, a wider and deeper depletion region may be formed by more heavily doping the deep n-well and applying a higher reverse bias voltage. By properly constructing the deep n-well and applying a high reverse bias voltage, a deep and wide depletion region may be formed to provide a barrier against noise from entering the quiet region.

Abstract: An emitter substructure and methods for manufacturing the substructure are described. A substrate has a p-region formed at a surface of the substrate. A n-tank is formed such that the p-region surrounds a periphery of the n-tank. An emitter is formed on and electrically coupled to the n-tank. A dielectric layer is formed on the substrate that includes an opening surrounding the emitter. An extraction grid is formed on the dielectric layer. The extraction grid includes an opening surrounding and in close proximity to a tip of the emitter. An insulating region is formed at a lower boundary of the n-tank. The insulating region electrically isolates the emitter and the n-tank along at least a portion of the lower boundary beneath the opening. The insulating region thus functions to displace a depletion region associated with a boundary between the p-region and the n-tank from an area that can be illuminated by photons traveling through the extraction grid or openings in the extraction grid.

Abstract: The thermal resistance Rth parameter is determined for a field effect transistor formed with a semiconductor film on a buried insulating material in SOI (semiconductor on insulator) technology. A p-n junction is formed with one of a drain region or a source region of the field effect transistor. The p-n junction is biased at a bias voltage. The p-n junction is heated to a plurality of temperatures. A current conducted through the p-n junction is measured at each of the plurality of temperatures of the p-n junction to generate a current versus temperature characteristic for the p-n junction. A respective current flowing through the p-n junction is measured as the field effect transistor is biased to dissipate each of a plurality of power dissipation levels and with the p-n junction being biased at the bias voltage.

Abstract: A power integrated circuit device with multiple guard rings and field plates overlying regions between each of the guard rings. Each of the field plates form overlying a dielectric layer also between each of the guard rings. Multiple field plates can exist between each of such guard rings. At least one field plate couples to a main junction region, and another field plate couples to a peripheral region, typically a scribe line. The present power device structure with multiple guard rings and field plates provides a resulting guard ring structure which allows for such device to achieve higher voltage applications.

Abstract: A bipolar complementary metal oxide semiconductor device has a c-well fabricated using profile engineering (a multi-energy implant using accurate dosages and energies determined by advance simulation) to provide a higher c-well implant dose while creating a narrow region with relatively low concentration in the collector depletion range to avoid low base-collector breakdown. This achieves a much lower collector series resistance to pull-up a frequency response, a collector sheet resistance which can be as low as 150 &OHgr;/sq., and fT may be increased to 20 GHz or higher.

Abstract: A circuit that includes an isolation boundary formed to a depth in a substrate defining an active area of the substrate, a primary junction formed in the active area to a primary junction depth in the substrate to collect electron/hole pairs, and a secondary junction formed in the active area adjacent to the isolation boundary to a secondary junction depth at least equal to the isolation boundary depth.

Abstract: A method for forming doped p-type gate is disclosed as the following description. The method includes that, firstly, a semiconductor substrate is provided. The semiconductor substrate is etched to form a concave portion as a shallow trench isolation. A first silicon dioxide is filled into the shallow trench isolation. A n-type well is formed into the semiconductor substrate. A silicon germanium layer, named as the doped p-type layer is formed on the surface of semiconductor substrate and the surface of shallow trench isolation. A silicon nitride layer, named as the anti-reflection layer is formed on the surface of silicon germanium layer. The portions of silicon nitride layer and the portions of silicon germanium layer are etched as a gate region. The source/drain extension is formed. A second silicon dioxide layer is deposited over the surface of semiconductor substrate and the surface of nitride layer. The second silicon dioxide layer is etched as a spacer beside the sidewall of gate region.

Abstract: A resist pattern with openings provided at the regions where N+ diffusion layers will be eventually formed is formed on a silicon substrate and thereafter, an N-type impurity is ion-doped to form N+ diffusion layers. Thereafter, gate electrodes are formed via a gate oxide film and then sidewall oxide films are formed, on the semiconductor substrate. Thereafter, an ion implantation of a P-type impurity is performed with a dose two orders of magnitude smaller than that of the N-type impurity for element isolation, with the gate electrodes and the sidewall oxide films being employed as a mask, thereby forming P-type impurity regions. The P-type impurity regions are caused to diffuse due to thermal processing in the following step. However, the element isolating P-type impurity regions resulted from the diffusion diffuse only into immediately under the sidewall oxide films at most, thus preventing the channel width from being narrowed.

Abstract: A semiconductor device includes a lead frame, a semiconductor chip, a resin-encapsulated portion, and tie bars. The semiconductor chip is mounted on a die pad of the lead frame. The resin-encapsulated portion resin-encapsulates the semiconductor chip. The tie bars are provided to outer lead portions of the lead frame to prevent resin leakage during resin encapsulation, and are cut and removed in a finishing step of resin encapsulation. A plating surface is formed on a sectional surface of each of the tie bars. A semiconductor device manufacturing method and apparatus are also disclosed.

Abstract: Disclosed is an electron discharging apparatus capable of fully accelerating electrons emitted from an electron discharging portion consisting of a pn-junction by effect of securing a greater exposure area of an accelerating electrode against said electron discharging portion. The inventive electron discharging apparatus comprises; a pn-junction formed on a surface side of a semiconductor substrate; an insulating film formed on the semiconductor substrate; a first aperture portion formed through a first insulating film formed on the pn-junction; and an accelerating electrode which is formed on the first insulating film by way of surrounding periphery of the first aperture portion. The accelerating electrode is formed so that inner edge portion of the accelerating electrode is projected into the first aperture portion area.

Abstract: To provide a process for manufacturing a semiconductor integrated circuit device in which ion implantation of an embedded diffused layer for forming triple-well and oxide film etching for forming two types of gate oxide films having different thicknesses is performed by only one photoetching step, the process being capable of reducing the manufacturing cost, and speeding up the circuit operation by making the gate oxide film of the peripheral unit thinner than that of the I/O circuit unit. A resist mask having a given width ranging in a given range which will be formed on the silicon oxide film is formed in a gate forming area in a region where an embedded N-type layer will be formed in a P-type silicon substrate and it is desired to make the thickness of the gate oxide film thicker. The embedded N-type layer is also formed even immediately below the resist mask by conducting an ion implantation at a given energy via the resist mask.

Abstract: Surface to surface electrical isolation of integrated circuits has been achieved by forming N type moats that penetrate the silicon as deeply as required, including across the full thickness of a wafer. The process for creating the moats is based on transmutation doping in which naturally occurring isotopes present in the silicon are converted to phosphorus. Several methods for bringing about the transmutation doping are available including neutron, proton, and deuteron bombardment. By using suitable masking, the bombardment effects can be confined to specific areas which then become the isolation moats. Four different embodiments of the invention are described together with processes for manufacturing them.

Abstract: A vertical type power MOSFET made of silicon carbide includes a surface channel layer doped with nitrogen as dopant with a concentration equal to or less than 1.times.10.sup.15 cm.sup.-3. Accordingly, when a gate oxide film is formed on the surface channel layer, an amount of silicon nitride produced in the gate oxide film and at the interface between the gate oxide film and the surface channel layer becomes extremely small. As a result, carrier traps are prevented from being produced by silicon nitride, resulting in stable FET characteristics and high reliability to the gate oxide film.

Abstract: The top surface of a P-type semiconductor substrate is partitioned into an active region to be formed with an element and an isolation region surrounding the active region. The isolation region is composed of trench portions and dummy semiconductor portions. An interlayer insulating film is deposited on the substrate, followed by a wire formed thereon. In each of the semiconductor portions, an impurity diffusion layer is formed simultaneously with the implantation of ions into the element so that a PN junction is formed between the impurity diffusion layer and the silicon substrate. A capacitance component of the wiring-to-substrate capacitance in the region containing the semiconductor portions is obtained by adding in series the capacitance in the impurity diffusion layer to the capacitance in the interlayer insulating film, which is smaller than the capacitance only in the inter layer insulating film.

Abstract: A thin silicon epitaxial layer, formed on a silicon substrate, is subdivided into electrically isolated pockets by a grid of oxidized regions of epitaxial silicon material which extend through the epitaxial layer to a laterally extending PN junction.

Abstract: A semiconductor process including forming a gate dielectric on a semiconductor substrate. First and second conductive gates are then formed on the gate dielectric. The conductive gates are aligned over respective channel regions of the substrate. The channel regions are laterally displaced between respective pairs of source/drain regions. A first interlevel dielectric is then deposited on the substrate and source/drain vias are then formed in the interlevel dielectric. The source/drain vias terminate on the pairs of source/drain regions. Thereafter, a source/drain impurity is introduced into the source/drain regions to form source/drain structures. A conductivity type of the source/drain structures is opposite a conductivity type of the field region. The first interlevel dielectric substantially prevents the source/drain impurity from entering the field region of the semiconductor substrate.

Abstract: A stacked layer including a first oxide, a nitride layer, a second oxide layer and an oxynitride layer is formed on the top of the first oxide layer. An etching is performed through a photoresist to etch the oxynitride, the second oxide and nitride. Oxide spacers are formed on the side walls of the pattern structure, the oxynitride layer is also removed during the formation of the oxide spacers. Trenches are generated by a dry etching technique. The second oxide and the oxide spacers are removed. Next, a thermal oxidation is performed to rounding the corners of the trench openings. A gap filling material is refilled into the trenches and formed on the nitride. Next, a chemical mechanical polishing (CMP) is used to remove the top of the CVD-oxide and the nitride layer. The residual nitride layer, the CVD-oxide and pad oxide are removed to create trench isolation structures with rounding corners.

Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, an active layer in the substrate and a silicon carbide buried layer which provides a conduction barrier between the substrate and at least a portion of the active layer. The buried layer is preferably formed by implanting second conductivity type dopants into the substrate so that a P-N junction barrier is provided between the active layer and the substrate. The buried layer may also be formed by implanting electrically inactive ions into the substrate so that a relatively high resistance barrier is provided between the active layer and the substrate. The electrically inactive ions are preferably selected from the group consisting of argon, neon, carbon and silicon, although other ions which are electrically inactive in silicon carbide may be used.

Abstract: A semiconductor circuit includes a semiconductor layer having a surface and a monolithic output stage formed in the semiconductor layer. The monolithic output stage extends to the surface of the semiconductor layer and has a periphery within the semiconductor layer, an output terminal, and a supply terminal. A barrier well is formed in the semiconductor layer and adjacent to at least a portion of the periphery of the monolithic output stage. The barrier well extends to the surface of the semiconductor layer and has a first conductivity. A diode having first and second diode regions is disposed in the semiconductor layer. The first diode region is coupled to the supply terminal. The diode is operable to prevent current flow from the barrier well to the supply terminal when the voltage between the supply and output terminals has a first polarity.

Abstract: An epitaxial pinched resistor includes a semiconductor substrate of a first conductivity type having a surface on which an epitaxial layer of a second conductivity type grown. An up isolation region of the first conductivity type is diffused from the surface of the semiconductor substrate up into the epitaxial layer. A first down isolation region of the first conductivity type is diffused down into the epitaxial layer and overlapping with the up isolation region. The first down isolation region and the up isolation region isolate a portion of the epitaxial layer to be used to conduct a current. A second down isolation region of the first conductivity type is diffused down into the epitaxial layer between first and second contact surface areas of the epitaxial layer and into the portion of the epitaxial layer used to conduct the current.

Abstract: In an NPN bipolar transistor having a special structure in which each impurity region is formed by ion implantation, a width of a base region is significantly reduced, and therefore, current amplification factor hfe is increased, resulting in improvement in performance thereof. Furthermore, a Bi-CMOS transistor can be manufactured using a CMOS process. The use of the bipolar transistor having a special structure for a driving circuit allows implementation of a driving circuit having large driving force with slight increase in cost.

Abstract: A process for doping a P-type substrate (50) by forming a layer (52) of silicon nitride, implanting N-type impurities through this layer (FIG. 7), forming a resist mask (54) which leaves at least one area of the substrate (FIG. 8) containing a part of the nitride layer exposed, implanting N-type impurities first with an insufficient energy and then with a sufficient energy to traverse the nitride layer, subjecting (FIG. 9) the substrate to a high temperature treatment in an oxidizing environment to form silicon dioxide pads (55) on the areas of the substrate not covered by the nitride layer, removing the nitride layer and performing an implantation of P-type impurities into the areas delimited by the pads. The process then continues with the removal of the pads and, in the conventional manner, with the formation of an epitaxial layer and selective doping of this to form P-type and N-type regions in it.

Abstract: To accomplish the above objectives, the present invention provides a method of fabricating a collector well in a semiconductor BiCMOS device. The method begins by providing a substrate having c-well areas, N-well areas, and P-well areas. The substrate has n-plug doped regions in said c-well areas. A stress release oxide layer is grown over the substrate surface. A first nitride layer 27 is formed over the stress release oxide layer 26. A C-well mask 29having C-well mask openings 28A is formed over C-well areas 28 and openings are formed in the first nitride layer. Impurities are implanted through the opening forming collector-well regions. The c-well mask is then removed. A n-well photoresist mask having n-well mask openings 42A is formed over the first nitride layer and openings are etched in the first nitride layer over N-well areas 40. Ions impurities are implanted through the n-well nitride opening 42A forming n-well regions 44 in the n-well area in the substrate 10. The n-well mask 42 is then removed.