Abstract: In a method of producing a trench insulation in a silicon substrate a first silicon-oxide layer is deposited on a front surface of a sequence of layers including the silicon substrate. Then the first silicon-oxide layer is structured so as to define a mask for a subsequent production of a trench. A trench is etched with a predetermined depth in the silicon substrate making use of the mask and filled with a silicon oxide. Then a first polysilicon layer is conformally deposited on the first silicon-oxide layer and on the oxide-filled trench. The first polysilicon layer is removed in such a way that a polysilicon cover remains on the oxide-filled trench, and the first silicon-oxide layer is removed.

Abstract: A semiconductor device is provided having at least two neighboring transistors and an STI region therebetween. The STI region is provided with a voltage bias to minimize subthreshold leakage current between the neighboring transistors. A method of fabricating such a semiconductor device is also provided.

Abstract: The filling of sub-0.25 &mgr;m trenches with dielectric material may lead to the formation of a void. Typically, the void may be closed by oxidation. When the trench includes non-oxidizable sidewall portions, insufficient closure may result. Therefore, an oxidizable spacer layer is conformally deposited prior to depositing the bulk dielectric, so that the sidewalls of the trench may be oxidized along the entire depth of the trench, thereby allowing the complete closure of the void.

Abstract: A recession resistant coated ceramic part. The ceramic part has a ceramic substrate and a recession resistant coating disposed on the substrate. The coating includes a plurality of layers diffusion bonded to each other and to the substrate respectively. The top most layer is characterized by a greater resistance to recession due to oxidation than that of the substrate.

Abstract: A method of forming an electrical isolation trench in a silicon-on-insulator (SOI) structure. The method comprises forming a first oxide layer on top of the upper silicon layer of the SOI structure, forming a polysilicon layer on top of said oxide layer, forming a second oxide layer on top of said polysilicon layer, patterning the first oxide layer, polysilicon layer, and second oxide layer to provide an etch mask, etching the upper silicon layer of the SOI structure to form said trench, and removing said second oxide layer and said polysilicon layer.

Abstract: A dual depth trench isolation structure formed between active devices and conductive well regions of same conductivity type which comprises a first inter-well isolation structure having a first isolation trench depth, a second inter-well isolation structure having a second isolation trench depth which combine to form a dual depth trench containing the dual depth trench isolation structure comprising the first inter-well isolation structure and the second inter-well isolation structure, with the dual depth trench isolation interposed at the boundary of an n-well conductive region and a p-well conductive region, a first intra-well isolation structure having a first isolation trench depth, the first intra-well isolation structure interposed between a pair of p-channel transistors residing in the n-well region, and a second intra-well isolation structure having a second isolation trench depth, the second intra-well isolation structure interposed between a pair of n-channel transistors residing in the p-well regio

Abstract: A process for fabricating an integrated circuit sensor/actuator is described. High aspect ratio deep silicon beams are formed by a process of deep trench etch and silicon undercut release etch by using oxide spacers to protect the silicon beam sidewalls during release etch. An oxide layer is then formed, followed by deposition of a controlled thickness of polysilicon which is then thermally oxidized. The polysilicon layer inside the trenches gets fully oxidized resulting in void-free trench isolation. This process creates a silicon island or beam on three sides leaving the third side for interfacing with the sensor/actuator beams. The sensor/actuator is formed by a similar process of deep trench etch and release etch process on the same substrate. These suspended beams of the sensors and actuators are bridged with the silicon islands from the fourth side. The above process finally results in suspended silicon beams connected to electrically isolated silicon islands.

Abstract: After a trench is formed into a substrate, a polysilicon layer is formed on sidewalls and a bottom of the trench. A thermal oxidation is performed on the polysilicon layer such that a polysilicon oxide layer is formed thereon. Then, a portion of the polysilicon oxide layer is removed such that the polysilicon layer is exposed on the bottom of the trench while the sidewalls of the trench are still covered by the polysilicon oxide layer. A TEOS-ozone oxide layer is deposited on the substrate to fill the trench. Since the bottom of the trench has a better condition for the deposition of TEOS-ozone oxide layer than that of the sidewalls, a gap fill quality can be enhanced.

Abstract: In a semiconductor device having an STI structure, a space is formed by causing a recession in an oxide film on a surface of a substrate with regard to a sidewall surface of a device isolation trench at an edge of the device isolation trench, and a Si film is formed so as to fill the trench. Further, the oxide film is removed from the surface of the substrate while leaving the Si film, and the trench is filled with an oxide film. Further, the Si film is oxidized to form an oxide film forming a part of the oxide film.

Abstract: A method of forming a recessed polysilicon contact is provided. The method includes: forming a trench in a substrate; overfilling the trench with polysilicon; removing the polysilicon outside of the trench to provide a substantially planar surface; oxidizing the surface of the polysilicon in the trench using plasma oxidation; and removing an upper portion of the polysilicon from the trench.

Abstract: A method of manufacturing a semiconductor trench device comprises forming a dielectric on a substrate, the dielectric having an underlying oxide layer adjacent the substrate, etching a trench in the dielectric and the substrate, forming a recess in the underlying oxide layer, filling the recess with a nitride plug, filling the trench a conductive material and oxidizing the dielectric and the conductive material, wherein the nitride plug controls a shape of a corner of the trench.

Abstract: A novel process for isolating devices on a semiconductor substrate is disclosed. An isolation layer is first formed over the semiconductor substrate and patterned into at least two isolation mesas on the substrate. Next, a blanket semiconductor layer is formed over the substrate with a thickness sufficient to cover the isolation mesas. The semiconductor layer is subjected to planarization until the isolation mesas are exposed, thus resulting in a semiconductor region between the two isolation mesas to serve as an active region for semiconductor devices.

Abstract: A method of forming an inverted staircase shaped STI structure comprising the following steps. A semiconductor substrate having an overlying oxide layer is provided. The substrate having at least a pair of active areas defining an STI region therebetween. The oxide layer is etched a first time within the active areas to form first step trenches. The first step trenches having exposed sidewalls. Continuous side wall spacers are formed on said exposed first step trench sidewalls. The oxide layer is etched X+1 more successive times using the previously formed step side wall spacers as masks to form successive step trenches within the active areas. Each of the successive step trenches having exposed sidewalls and have side wall spacers successively formed on the successive step trench exposed sidewalls. The oxide layer is etched a final time using the previously formed step side wall spacers as masks to form final step trenches exposing the substrate within the active areas.

Abstract: A method for forming an isolation layer of a semiconductor device is disclosed. The method has a wet etching separately performed two times or more without a conventional chemical mechanical polishing process. In the method, a silicon substrate in which an active region and a field region are defined is provided, and a trench is formed in the silicon substrate within the field region. An insulating layer to be used as the isolation layer is then formed on the silicon substrate including the trench. Thus the trench is filled with the insulating layer. Next, a capping layer is formed on a resultant entire structure including the insulating layer, and selectively removed to expose an upper portion of the insulating layer in the active region. The exposed insulating layer in the active region is then removed by a first wet etching, and the residual capping layer is removed by a second wet etching. Accordingly, the isolation layer is obtained from the insulating layer remaining in the trench.

Abstract: A method for forming polysilicon-filled trench isolations is provided. The present method is characterized in that using nitrogen implantation to amorphize the top portion of the polysilicon filled in the trench isolation and then a nitrogen-implanted region formed in this top portion. The nitrogen-implanted region forms an oxynitride cap layer during the polysilicon oxidation. The oxynitride cap layer provides better erosive resistance to acidic solutions for stripping away photopresist layers used for several wells/Vth implantations than a silicon dioxide layer. The oxynitride cap layer also reduces the gate-to-channel fringing field because its dielectric constant is higher than that of silicon dioxide. Moreover, the nitrogen-implanted region in the top portion of the polysilicon decreases the polysilicon oxidation time so that the channel edge oxidation is reduced.

Abstract: A film substrate of an electronic displaying element, an electronic optical element, a touch panel, or a solar battery is disclosed which is composed mainly of an organic polymer having water solubility of 0 to 5 g based on 100 g of 25° C water and having acetone solubility of 25 to 100 g based on 100 g of 25° C acetone and an inorganic condensation polymer of a reactive metal compound capable of being condensed.

Abstract: A silicon oxide film (6aa) is formed on an upper surface of an SOI layer (3), a silicon nitride film (6bb) is formed on the silicon oxide film (6aa), and a silicon oxide film (6cc) is formed on the silicon nitride film (6bb). Using the silicon nitride film (6bb) as an etch stopper, anisotropic dry etching is performed on the silicon oxide film (6cc) in first and second device formation regions. Then, using the silicon oxide film (6aa) as an etch stopper, anisotropic dry etching is performed on the silicon nitride film (6bb) in the first and second device formation regions. The silicon oxide film (6aa) in the first and second device formation regions is removed by wet etching using hydrofluoric acid to expose the upper surface of the SOI layer (3). A method of manufacturing a semiconductor device is provided which is capable of avoiding the formation of a damaged layer in a main surface of an SOI substrate when such a device isolation structure is formed.

Abstract: A method of manufacturing a shallow trench isolation (STI) with an air gap that is formed by decomposing an organic filler material through a cap layer. A pad layer and a barrier layer are formed over the substrate. The pad layer and the barrier layer are patterned to form a trench opening. We form a trench in substrate by etching through the trench opening. A first liner layer is formed on the sidewalls of the trench. A second liner layer over the barrier layer and the first liner layer. A filler material is formed on the second liner layer to fill the trench. In an important step, a cap layer is deposited over the filler material and the second liner layer. The filler material is subjected to a plasma and heated to vaporize the filler material so that the filler material diffuses through the cap layer to form a gap. An insulating layer is deposited over the cap layer. The insulating layer is planarized. The barrier layer is removed.

Abstract: An improved method of trench isolation formation includes, for one embodiment, applying a polysilicon layer above a planarized trench, and converting the polysilicon to oxide prior to etching the active areas. This converted oxide is denser than the materials usually used to fill the trench, such as TEOS, and results in less over-etching of the trench isolation region. The quality of the dielectric isolation is consequently improved, and in particular, less leakage current flows across the trench isolation region. Moreover, less leakage current flows from a subsequently formed local interconnect layer.

Abstract: An ultranarrow insulated trench isolation structure is formed in a semiconductor substrate without creating voids in the insulating material which adversely affect the performance of finished devices. Embodiments include forming a narrow trench in the semiconductor substrate, then forming a spacer on the sidewalls of the trench, as by depositing and anisotropically etching a layer of silicon dioxide, amorphous silicon, or silicon oxynitride. The trench is then refilled as by conventional LPCVD, PECVD or HDP techniques, and the spacers are oxidized, if necessary. Since the spacers, in effect, create sloped trench walls, the trench fill can be performed, even at a high deposition rate, with substantially fewer voids than conventional processes, while also reducing reentrance of the trench walls.

Abstract: A method of fabricating a salicide layer in an electrostatic discharge protection device. On a MOS transistor having a gate, a source region and a drain region, a salicide block layer is formed. The salicide layer is patterned to remaining covering the drain region only, and leaving the source region and other portions of the substrate exposed. The anti-reflection coating layer is then removed to expose the gate. A salicide layer is formed on the exposed source region, the gate and other exposed portion of the substrate, while the drain region is free from the salicide layer for being covered with the salicide block layer.

Abstract: The fabrication method provides for an etched isolation trench to be lined, if appropriate firstly with a thin thermal oxide layer, and then with an oxidizable auxiliary layer. The auxiliary layer consumes oxygen during subsequent thermal processes, thereby avoiding oxidation of deeper structures, in particular of an insulation collar in a capacitor trench.

Abstract: A method of manufacturing a shallow trench isolation in a substrate. The substrate has a pad oxide layer and a mask layer formed thereon in sequence and a trench penetrating through the mask layer and the pad oxide layer and into the substrate. A thermal oxidation process is performed to form a liner oxide layer on a portion of the substrate exposed by the trench. A spacer is formed on the sidewall of the mask layer, the pad oxide layer and the trench. An oxidation process is performed to oxidize a portion of the substrate under a portion of the liner oxide layer located on the bottom of the trench. An insulating layer is formed over the substrate and filling the trench. A planarization process is performed to remove a portion of the insulating layer until the mask layer is exposed. The mask layer and the pad oxide layer are removed.

Abstract: According to the invention, there is provided an inbred corn plant designated 01HGI4. This invention thus relates to the plants, seeds and tissue cultures of the inbred corn plant 01HGI4, and to methods for producing a corn plant produced by crossing the inbred corn plant 01HGI4 with itself or with another corn plant, such as another inbred. This invention further relates to corn seeds and plants produced by crossing the inbred plant 01HGI4 with another corn plant, such as another inbred, and to crosses with related species. This invention further relates to the inbred and hybrid genetic complements of the inbred corn plant 01HGI4, and also to the RFLP and genetic isozyme typing profiles of inbred corn plant 01HGI4.

Abstract: The method includes forming a pad oxide, a polysilicon layer over a substrate. Next, an oxide layer is formed over the polysilicon layer. An opening is formed in the oxide layer, the polysilicon layer, and the pad layer. A trench is formed by etching the substrate using the oxide layer as a mask. A sidewall structure is then formed on the opening. Next, an exposed portion of the substrate is etched by using the sidewall structure as a mask. The sidewall structure and the oxide layer are then removed. An oxide and an oxynitride layer are then formed on the aforesaid feature. A semiconductor layer is then formed over the oxynitride layer. A portion of the semiconductor layer is oxidized for forming an insulating layer. Finally, a refilling layer is formed over the insulating layer and the substrate is planarized for having a planar surface.

Abstract: A trench isolation structure in a semiconductor substrate includes a trench opening in the surface of the substrate and a seamless oxide layer filling the trench. The seamless oxide layer is formed by forming a first oxide layer in the trench, adding a silicon material overlying the first oxide layer and within a gap on the first oxide layer between the trench sidewalls that tend to be produced in the preceding step, and oxidizing the silicon material to form a second oxide layer. The deposited silicon material expands during oxidation, filling the trench opening to produce a seamless oxide fill of the trench. This seamless trench isolation structure prevents accumulation of materials that reduce the yield of the finished semiconductor product.

Abstract: The present invention relates to a device isolation structure and a device solation method in a semiconductor power IC. The device isolation structure according to the present invention includes: a semiconductor substrate including a high voltage region and a low voltage region; a trench overlapping the high voltage device region of the semiconductor substrate and an interfacing region formed between the high voltage device region and the low voltage device region; a fourth insulating film, a fifth insulating film, and a conductive film sequentially layered in the trench; a first insulating film pattern formed on the semiconductor substrate including the trench; and field insulating films respectively formed on the trench and on a portion of an upper surface of the semiconductor substrate which is exposed out of the first insulating film pattern.

Abstract: A semiconductor device structure with differential field oxide thicknesses. A single field oxidation step produces a nitrided field oxide region (322) that is thinner than a non-nitrided field oxide region (324). The bird's beak (326) of the nitrided field oxide (322) encroaches less into the active cell region than the bird's beak (328) of the thicker non-nitrided field oxide (324). The differential field oxide thicknesses allow isolation of multi-voltage integrated circuit devices, such as flash memory devices, while increasing available active cell area for a given design rule.

Abstract: In an NPN transistor of this invention having a trench isolation structure, for example, an N.sup.+ -type buried layer and an N.sup.- -type epitaxial layer are stacked on an element forming region of a P.sup.+ -type substrate, and a trench having polysilicon filled therein is formed in a portion adjacent to the element forming region. Further, a field oxide film is formed to extend from the trench having polysilicon filled therein over to the adjacent element isolation region without extending into the element forming region. Thus, a distance from the front end portion of the field oxide film on the element forming region side to the trench is reduced to reduce the element area. Therefore, the parasitic capacitance can be reduced and the power consumption of a circuit can be reduced.

Abstract: A method to form a shallow trench isolation (STI) structure includes forming a trench on a semiconductor substrate. Then a channel stop is formed under the trench. A pad oxide layer and a silicon nitride layer are sequentially formed over the substrate. A side-wall spacer is formed over the silicon nitride layer on each side of the trench. An oxidation process is performed to oxidize the side-wall spacer. Another side-wall spacer and oxidation are repeatedly performed until the trench is filled with oxide. An oxide layer is formed over the substrate. Then an active ion etching process is performed to remove the layers above the substrate other than the trench region. The STI structure then is formed.

Abstract: A method for forming a STI structure is provided. The method contains sequenitially forming a pad oxide layer and a mask layer on a semiconductor substrate. Several trenches in the substrate through the mask layer and the pad oxide layer. The trenches has a wider trench and a narrower trench. A liner oxide layer is formed at each sidewall of the trenches in the substrate. A spacer is formed on each sidewall of the wider trench, in which the narrower trench simultaneously is filled with same insulating material. A conformal polysilicon layer is formed over the substrate, in which the wider trench is not completely filled yet. An insulating plug is formed to fill the wider trench. Using the insulating plug as an etching mask a portion of the polysilicon layer is removed by etching. As a result, a polysilicon pivot sidewall of the remaining polysilicon layer due to etching may occur. The polysilicon pivot sidewall is compensated with polysilicon.

Abstract: An STI fabrication method for a semiconductor device is disclosed, which includes the steps of forming a trench on a semiconductor substrate, forming a conductive film on the trench, ion-implanting a germanium into the conductive film, and oxidizing the conductive film.

Abstract: Method for improving the topography over trench structures in which the provision of extra poly-semiconductor material e.g. polysilicon or nitrate or oxide in the regions of the trench edges and, if necessary, the subsequent oxidation of the extra material prevents the occurrence of regions of high mechanical stress.

Abstract: The method in the present invention is proposed for forming trench isolation in a semiconductor substrate. The method includes the steps as follows. At first, a pad layer is formed over the substrate. A first stacked layer is then formed over the pad layer. Next, a second stacked layer is formed over the first stacked layer. An opening is defined in the second stacked layer, the first stacked layer, and the pad layer. The opening extends down to the substrate. A portion of the substrate is then removed for forming an upper-half portion of a trench by using the second stacked layer as a mask. A sidewall structure is formed on the opening. Next, a portion of the substrate is removed for forming a lower-half portion of the trench by using the sidewall structure as a mask. The sidewall structure and the second stacked layer are removed. Following with the formation of a first insulating layer over the trench, a second insulating layer is formed over the first insulating layer and over the first stacked layer.

Abstract: A process for forming, on a semiconductor substrate, an isolation structure between two zones of an integrated circuit wherein active regions of electronic components integrated thereto have already been defined, comprises the steps of:defining an isolation region on a layer of silicon oxide overlying a silicon layer;selectively etching the silicon to provide the isolation region;growing thermal oxide over the interior surfaces of the isolation structure;depositing dielectric conformingly; andoxidizing the deposited dielectric.

Abstract: A side wall masked isolation (SWAMI) technique for isolating active regions on an integrated circuit involves reducing the "bird's beak" structure. The technique involves forming an isolation recess in the substrate, and then lining the recess with a layer of silicon dioxide, and then a layer of silicon nitride. Then, oxide spacers are formed on each of the sidewalls of the recess. The recess is then anisotropically etched until the substrate at the bottom of the recess is exposed. This etch process involves removing portion of both the silicon dioxide and the silicon nitride layers formed at the bottom of the recess. Subsequently, a layer of polycrystalline silicon material is deposited in the recess and is then etched back and oxidized to form a field oxide. Since the polycrystalline silicon is oxidized, the result is negligible oxide encroachment resulting in a reduction in the "bird's beak" structure.

Abstract: A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a trench in the semiconductor substrate between said first active region and said second active region. A first dielectric layer is then formed on said trench and a polysilicon layer is deposited on said first dielectric layer. The polysilicon layer is then thermally oxidized to form a second dielectric layer. Preferably the first dielectric is a thermal oxide 40 to 500 angstroms in thickness consuming less than 200 angstroms of said first active region and said second active region. The polysilicon layer is preferably between 1000 to 2000 angstroms.

Abstract: The present invention provides a method of manufacturing a semiconductor device to prevent the generation of crystalline defects due to shorting between interconnects resulting from etch residue as a result of the generation of vertical bird's beaks on top of the trench during field oxidation layer formation. The method includes forming an epitaxial layer over a semiconductor substrate, depositing a first SiO.sub.2 layer, an SiN layer and a second SiO.sub.2 layer in that order upon said epitaxial layer and forming a trench from the second SiO.sub.2 layer extending into the semiconductor substrate. A third SiO.sub.2 layer is formed coating said trench with a region of said third Si0.sub.2 layer removed adjacent to said first SiO.sub.2 layer to expose a portion of said epitaxial layer within said trench. The trench is then filled with a first polysilicon layer to coat the third SiO.sub.2 layer and the first SiO.sub.2 layer followed by removal of the second SiO.sub.

Abstract: A method for forming an isolation wall in a silicon semiconductor substrate wherein a trench is etched into the silicon using a hard mask, a layer of silicon dioxide is formed on the side walls of the trench, a filling of polysilicon is placed in the region between the side wall layers, the polysilicon is planarized by etching while the hard mask remains in place, and the hard mask then is stripped from the silicon, permitting field oxide to be grown over the trench region.

Abstract: A method for fabricating shallow trench isolation using a gradient-doped polysilicon trench-fill and a chemical/mechanical polishing that improves substrate planarity was achieved. The method involves forming shallow trenches in a silicon substrate having a silicon nitride layer on the surface. After selectively oxidizing silicon exposed in the trenches, a second silicon nitride layer is deposited, and a composite polysilicon layer consisting of an undoped polysilicon layer and a gradient-doped polysilicon layer is deposited filling the trenches. The composite polysilicon layer is then chemical/mechanically polished back. The gradient-doped polysilicon layer improves the removal rate uniformity across the substrate (wafer) by removing the heavily doped regions at a faster rate than undoped or lightly doped regions. This results in improved global planarity which improves the polysilicon dishing in the trenches near the edge of the substrate.

Abstract: Trenches 72 are formed in substrate 17 late in the fabrication process. In order to avoid trench sidewall stresses that cause defects in the substrate monocrystalline lattice, the trenches are filled after a final thick thermal oxide layer, such as a LOCOS layer 25, is grown. The trenches 72 are also filled after a final deep diffusion, i.e. a diffusion in excess of one micron.

Abstract: To form NPN and PNP transistors on the same base for example to obtain a complementary bipolar transistor it has been necessary to make an epitaxial layer a thick film, and this has resulted in deterioration of the characteristics of the NPN transistor. Also, because a step of forming an alignment mark has been necessary this has increased the number of manufacturing steps needed to make a complementary bipolar transistor. This invention provides a semiconductor device manufacturing method which solves this problem as follows: After a first opening 13 (alignment mark 16) and a second opening 14 are formed in an insulating film 12 formed on a semiconductor base 11 and a doping mask 15 is then formed on the semiconductor base 11, a third opening 17 is formed thereon with the alignment mark 16 as a reference.