Polysilicon Containing Sidewall Patents (Class 438/446)
  • Patent number: 5834360
    Abstract: A method is provided for forming an isolation structure at a semiconducting surface of a body, and the isolation structure formed thereby. A masking layer is formed over selected regions of the substrate surface; the masking layer preferably comprising a nitride layer overlying a pad oxide layer. The masking layer is patterned and etched to form openings exposing selected regions of the substrate surface. Recesses are formed into the substrate in the openings. Preferably a portion of the pad oxide layer is isotropically etched under the nitride layer forming an undercut region. An etch stop layer is formed over the substrate in the recesses filling in the undercut along the sidewalls. A second masking layer, preferably of nitride is formed over the etch stop layer and anisotropically etched to form nitride sidewalls in the openings. The etch stop layer may be etched away from the horizontal surfaces.
    Type: Grant
    Filed: July 31, 1996
    Date of Patent: November 10, 1998
    Assignee: STMicroelectronics, Inc.
    Inventors: Mark R. Tesauro, Frank R. Bryant
  • Patent number: 5824594
    Abstract: An integrated circuit device is isolated by forming a pad oxide layer on an integrated circuit substrate. A mask pattern is formed on the pad layer. The mask pattern includes sidewalls which selectively expose the pad oxide layer between the sidewalls. A silicon spacer is formed on the sidewalls. An oxidation barrier film is formed on the silicon spacer and on the exposed pad oxide layer. The integrated circuit substrate is then oxidized through the oxidation barrier film to form a device isolating layer. The oxidation barrier film on the exposed pad oxide layer is thinner than the oxidation barrier film on the sidewalls. Thus, oxidation of the silicon spacer is delayed relative to the substrate.
    Type: Grant
    Filed: April 14, 1997
    Date of Patent: October 20, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-eui Kim, Young-dae Kim
  • Patent number: 5763316
    Abstract: A process for creating field oxide isolation for the micron and sub-micron devices in the high density integrated circuits has been developed. The junction leakage problem resulted from the trenches in the substrate formed after the removal of the silicon nitride mask, is avoided. The encroachment of the "bird's beak" into the small active device region is also minimized by this invention. These goals are accomplished by the addition of a polysilicon or amorphous silicon refill layer in the trenches after the removal of the silicon nitride oxidation mask in the isolation region, prior to field oxide oxidation process.
    Type: Grant
    Filed: February 19, 1997
    Date of Patent: June 9, 1998
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Fu Chen, Bao-Ru Yang, Wen-Cheng Chang
  • Patent number: 5658822
    Abstract: An improved local oxidation of silicon (LOCOS) method with recessed silicon substrate and double polysilicon/silicon nitride spacer is disclosed. The present invention includes forming a pad oxide layer on a semiconductor substrate and then forming a first silicon nitride layer on the pad oxide layer. An active region is defined by patterning and etching the pad oxide layer and the first silicon nitride layer using a photoresist mask. Thereafter, a silicon oxide layer and a second silicon nitride layer is formed. Next, a polysilicon layer is deposited over the second silicon nitride layer. The polysilicon layer, the second silicon nitride layer, and the silicon oxide layer are etched back to form a double polysilicon/silicon nitride spacer. Finally, an isolation region in the substrate is formed.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: August 19, 1997
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shye-Lin Wu, Hsi-Chuan Chen, Ming-Hong Kuo
  • Patent number: 5629230
    Abstract: A semiconductor processing method of forming a field oxide region on a semiconductor substrate includes, a) providing a patterned first masking layer over a desired active area region of a semiconductor substrate, the first masking layer having at least one side edge; b) providing a silicon sidewall spacer over the side edge of the patterned first masking layer, the silicon sidewall spacer having a laterally outward projecting foot portion; c) oxidizing the substrate and the silicon sidewall spacer to form a field oxide region on the substrate; d) stripping the first masking layer from the substrate; and e) providing a gate oxide layer over the substrate. The invention enables taking advantage of process techniques which minimize the size of field oxide bird's beaks without sacrificing upper field oxide topography.
    Type: Grant
    Filed: August 1, 1995
    Date of Patent: May 13, 1997
    Assignee: Micron Technology, Inc.
    Inventors: Pierre C. Fazan, Nanseng Jeng, David L. Dickerson