Abstract: Integrated circuit structures might include a semiconductor material, a first active area in the semiconductor material, a second active area in the semiconductor material, and an isolation structure comprising a dielectric material deposited in a trench formed in the semiconductor material between the first active area and the second active area. The isolation structure might further include a first edge portion extending below a surface of the semiconductor material to a first depth, a second edge portion extending below the surface of the semiconductor material to the first depth, and an interior portion between the first edge portion and the second edge portion, and extending below the surface of the semiconductor material to a second depth, less than the first depth.

Abstract: A system and method for placement and simulation of a cell in proximity to a cell with a diffusion break is herein disclosed. According to one embodiment, an integrated circuit is designed to include a first cell that has a first edge and a second edge opposite the first edge. The first cell may also include a diffusion region that extends from the first edge to the second edge with a diffusion break separating the diffusion region. The diffusion break may be spaced away from the second edge by a distance that degrades a metric (e.g., a delay, a slew, dynamic power, or leakage) of a second cell placed next to the second edge beyond a threshold level.

Abstract: A method of fabricating an integrated circuit includes depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon including a gate electrode on a gate dielectric. The first dielectric material is etched to form sidewall spacers on sidewalls of the gate stack. A top surface of the first dielectric material is chemically converted to a second dielectric material by adding at least one element to provide surface converted sidewall spacers. The second dielectric material is chemically bonded across a transition region to the first dielectric material.

Abstract: A method of manufacturing a semiconductor package substrate has a simplified process and an upper and lower pattern alignment problem is solved. A semiconductor package substrate is manufactured by the method. The method of manufacturing a semiconductor package substrate includes forming a first groove in one surface of a base substrate of a conductive material, filling the first groove with resin, and etching another surface of the base substrate to expose the resin filling the first groove.

Abstract: A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed. Afterwards, a filler is formed at least in the trench and a planarization process is then performed on the filler. Since the planarization process is performed only on the filler, so the dishing phenomenon can effectively be avoided.

Abstract: Substrate material is oxidised around side walls of a set of channels. A shielding structure means there is more oxide growth at the top than the bottom with the result that the non-oxidised substrate material area between the channels forms a tapered shape with a pointed tip at the top. These pointed substrate areas are then used to form cathodes.

Abstract: A method of etching a silicon substrate includes providing a silicon substrate including a first surface and a second surface. A plurality of grooves spaced apart from each other are etched from the first surface of the silicon substrate. A dielectric material is deposited on the first surface of the silicon substrate and into the plurality of grooves. A hole through the silicon substrate is etched from the second surface of the substrate to the dielectric material. A portion of the hole is located between the plurality of grooves.

Abstract: Methods for fabricating conductive metal lines of a semiconductor device are described herein. In one embodiment, such a method may comprise depositing a conductive material over a substrate, and depositing a first barrier layer on the conductive layer. Such a method may also comprise patterning a mask on the first barrier layer, the pattern comprising a layout of the conductive lines. Such an exemplary method may also comprise etching the conductive material and the first barrier layer using the patterned mask to form the conductive lines. In addition, a low temperature post-flow may be performed on the structure. The method may also include depositing a dielectric material over and between the patterned conductive lines.

Abstract: One illustrative method disclosed herein includes performing at least one etching process on a semiconducting substrate to form a plurality of trenches and a plurality of fins for the FinFET device in the substrate, forming a first layer of insulating material in the trenches, wherein an upper surface of the first layer of insulating material is below an upper surface of the substrate, forming an isolation layer within the trenches above the first layer of insulating material, wherein the isolation layer has an upper surface that is below the upper surface of the substrate, forming a second layer of insulating material above the isolation layer, wherein the second layer of insulating material has an upper surface that is below the upper surface of the substrate, and forming a gate electrode structure above the second layer of insulating material.

Abstract: A shallow trench isolation (STI) structure and methods of forming a STI structure are disclosed. An embodiment is a method for forming a semiconductor structure. The method includes forming a recess in a semiconductor substrate; forming a first material on sidewalls of the recess; forming a widened recessed portion through a bottom surface of the recess; removing the first material from the sidewalls of the recess; and forming a dielectric material in the recess and the widened recessed portion. The bottom surface of the recess is exposed through the first material, and the bottom surface of the recess has a first width. The widened recessed portion has a second width. The second width is greater than the first width.

Abstract: A silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) with an isolation formed at a low temperature and methods for constructing the same. An example method includes infusing an insulation material at a low temperature to form a silicon-based insulator between the active regions.

Abstract: A semiconductor light emitting device has a light emitting element, a first electrode layer, a second electrode layer, a seed electrode layer and a plated layer. The light emitting element has a nitride-based III-V compound semiconductor on a substrate. The light emitting element having a light extraction surface. The first electrode layer on the light extraction surface. The second electrode layer is provided on a surface opposite to the light extraction surface of the light emitting element. The seed electrode layer is configured to cover the entire surface of the second electrode layer. The plated layer is provided on the seed electrode layer. The light emitting element has a light emitting layer, a first conductive type semiconductor layer, and a second conductive type semiconductor layer.

Abstract: A substrate structure is produced by forming a first material layer on a substrate having a recess, removing the first material layer from the portion of the substrate except for the recess using a second material that reacts with the first material, and forming a deposition film from the first material layer using a third material that reacts with the first material. A method of manufacturing a device may include the method of forming a substrate structure.

Abstract: This disclosure presents manufacturing methods and apparatus designs for making TFSSs from both sides of a re-usable semiconductor template, thus effectively increasing the substrate manufacturing throughput and reducing the substrate manufacturing cost. This approach also reduces the amortized starting template cost per manufactured substrate (TFSS) by about a factor of 2 for a given number of template reuse cycles.

Abstract: There is provided a method for producing an ink jet head. The method includes: first oxidizing in which, in an SOI substrate having a first SiO2 layer between a first Si layer and a second Si layer, among the first Si layer and the second Si layer, at least the first Si layer is thermally oxidized to form a second SiO2 layer; forming a nozzle hole by removing a part of the second SiO2 layer and a part of the first Si layer between the first SiO2 layer and the second SiO2 layer, by performing an etching treatment until at least the first SiO2 layer is exposed; second oxidizing in which a side wall of at least the first Si layer in the formed nozzle hole is thermally oxidized to form an SiO2 layer; opening the nozzle hole by subjecting the SiO2 layers in the nozzle hole other than at the side wall to an anisotropic dry etching treatment until at least the second Si layer is exposed; and forming a nozzle by removing the second Si layer.

Abstract: A method of manufacturing a semiconductor device, includes forming an insulating film of a material having a low relative dielectric constant on a substrate, forming an SiOCH film on the insulating film in a chamber, forming an SiO2 film continuously on the SiOCH film by reducing a carbon concentration therein in the chamber in which plasma is being generated, performing a plasma etching on the insulating film by using the SiOCH film and the SiO2 film as a hardmask layer, to form a trench in the insulating film, and performing wet etching on a surface of the trench formed in the insulating film, to remove a layer damaged by the plasma etching and process residues.

Abstract: Provided are a lead frame, a semiconductor package, and a method of manufacturing the lead frame and the semiconductor package. The lead frame includes: a die pad on which a semiconductor chip is installable; a plurality of lead patterns formed around a circumference of the die pad; an insulating organic material filling etching spaces interposed between the die pad and the lead patterns and structurally supporting the die pad and the lead patterns; and a pre-plating layer formed on both upper and lower surfaces of the die pad and the lead patterns.

Abstract: A high breakdown voltage circuit containing a high breakdown voltage MOSFET in LSI, unlike a quintessential internal circuit, has an operating voltage fixed in a high state due to the relation with the outside and, therefore, miniaturization by the voltage lowering can not be applied, differing from ordinary cases. Consequently, the voltage lowering of an internal circuit part results in a furthermore enlargement of occupying area in the chip. The present inventors evaluated various measures for the problem, and made it clear that such problems as compatibility with the CMOSFET circuit configuration and device configuration, etc. constitute obstacles.

Abstract: A method of fabricating a semiconductor device including at least one of the following steps: forming an oxide layer on and/or over a silicon substrate. Forming a first photoresist pattern on and/or over the oxide layer. Forming a trench by etching the oxide layer and the substrate using the first photoresist pattern as a mask. Removing the first photoresist pattern. Filling the trench with a trench oxide layer. Planarizing the trench oxide layer. Forming an etch stop layer on and/or over the trench oxide layer. Forming a second photoresist pattern on and/or over the etch stop layer. Etching the etch stop layer and the trench oxide layer using the second photoresist pattern as an etch mask. Removing the second photoresist pattern and the etch stop layer.

Abstract: The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (12) of silicon which comprises an active region (A) with a transistor (T) and a passive region (P) surrounding the active region (A) and which is provided with a buried conducting region (1) of a metallic material that is connected to a conductive region (2) of a metallic material sunken from the surface of the semiconductor body (12), by which the buried conductive region (1) is made electrically connectable at the surface of the semiconductor body (12). According to the invention, the buried conducting region (1) is made at the location of the active region (A) of the semiconductor body (12). In this way, a very low buried resistance can be locally created in the active region (A) in the semiconductor body (12), using a metallic material that has completely different crystallographic properties from the surrounding silicon. This is made possible by using a method according to the invention.

Abstract: First, on a semiconductor region of a first conductivity type, a trapping film is formed which stores information by accumulating charges. Then, the trapping film is formed with a plurality of openings, and impurity ions of a second conductivity type are implanted into the semiconductor region from the formed openings, thereby forming a plurality of diffused layers of the second conductivity type in portions of the semiconductor region located below the openings, respectively. An insulating film is formed to cover edges of the trapping film located toward the openings, and then the semiconductor region is subjected to a thermal process in an atmosphere containing oxygen to oxidize upper portions of the diffused layers. Thereby, insulating oxide films are formed in the upper portions of the diffused layers, respectively. Subsequently, a conductive film is formed over the trapping film including the edges thereof to form an electrode.

Abstract: Roughly described, methods and systems for improving integrated circuit layouts and fabrication processes in order to better account for stress effects. Dummy features can be added to a layout either in order to improve uniformity, or to relax known undesirable stress, or to introduce known desirable stress. The dummy features can include dummy diffusion regions added to relax stress, and dummy trenches added either to relax or enhance stress. A trench can relax stress by filling it with a stress-neutral material or a tensile strained material. A trench can increase stress by filling it with a compressive strained material. Preferably dummy diffusion regions and stress relaxation trenches are disposed longitudinally to at least the channel regions of N-channel transistors, and transversely to at least the channel regions of both N-channel and P-channel transistors. Preferably stress enhancement trenches are disposed longitudinally to at least the channel regions of P-channel transistors.

Abstract: A semiconductor device and methods for its fabrication are provided. The semiconductor device comprises a trench formed in the semiconductor substrate and bounded by a trench wall extending from the semiconductor surface to a trench bottom. A drain region and a source region, spaced apart along the length of the trench, are formed along the trench wall, each extending from the surface toward the bottom. A channel region is formed in the substrate along the trench wall between the drain region and the source region and extending along the length of the trench parallel to the substrate surface. A gate insulator and a gate electrode are formed overlying the channel.

Abstract: The current invention provides methods of fabricating a capacitive micromachined ultrasonic transducer (CMUT) that includes oxidizing a substrate to form an oxide layer on a surface of the substrate having an oxidation-enabling material, depositing and patterning an oxidation-blocking layer to form a post region and a cavity region on the substrate surface and remove the oxidation-blocking layer and oxide layer at the post region. The invention further includes thermally oxidizing the substrate to grow one or more oxide posts from the post region, where the post defines the vertical critical dimension of the device, and bonding a membrane layer onto the post to form a membrane of the device. A maximum allowed second oxidation thickness t2 can be determined, that is partially based on a desired step height and a device size, and a first oxidation thickness t1 can be determined that is partially based on the determined thickness t2.

Abstract: In one aspect, there is provided a method of manufacturing a semiconductor device that comprises placing a blocking layer, a CMP stop layer and a bulk oxide layer over an oxide cap layer that is located over gate structures and source/drains located adjacent thereto. The bulk oxide layer and the CMP stop layer are removed with a CMP process to expose the top of gate electrodes and are removed from over the source/drain areas with a wet etch. The CMP stop layer has a CMP removal rate that is less than a CMP removal rate of the bulk oxide layer and has a wet etch removal rate that is greater than a wet etch removal rate of the blocking layer.

Abstract: A residue treatment system includes a treatment tank which treats residue with etching fluid, the residue being generated in a trench formed in an insulating film by dry etching; a measurement unit which measures a characteristic amount of the etching fluid; and a control unit which calculates treatment time for removing the residue on the basis of a value obtained by measuring the characteristic amount, the control unit calculating the treatment time by using correlation between an etching rate of the insulating film and the characteristic amount.

Abstract: An oxide pattern forming method comprises forming an oxide layer on a semiconductor substrate, implanting boron ions of not less than 1.0×1016 atoms/cm2 onto the oxide layer in a given region, and wet-etching the oxide layer in the remaining region where the boron ions are not implanted.

Abstract: A method for fabricating an isolation layer in a semiconductor device includes providing a substrate, forming a trench over the substrate, forming a liner nitride layer and a liner oxide layer along a surface of the trench, forming an insulation layer having an etch selectivity ratio different from that of the liner oxide layer over the liner oxide layer, forming a spin on dielectric (SOD) oxide layer to fill a portion of the trench over the insulation layer, and forming a high density plasma (HDP) oxide layer for filling the remaining a portion of the trench.

Abstract: Even if the insulated isolation structure which makes element isolation using partial and full isolation combined use technology is manufactured, the manufacturing method of a semiconductor device which can manufacture the semiconductor device with which characteristics good as a semiconductor element formed in the SOI layer where insulated isolation was made are obtained is obtained. Etching to an inner wall oxide film and an SOI layer is performed by using as a mask the resist and trench mask which were patterned, and the trench for full isolation which penetrates an SOI layer and reaches an embedded insulating layer is formed. Although a part of CVD oxide films with which the resist is not formed in the upper part are removed at this time, since a silicon nitride film is protected by the CVD oxide film, the thickness of a silicon nitride film is kept constant.

Abstract: A film structure of a ferroelectric single crystal which can be beneficially used in the fabrication of high-performance electric or electronic parts or devices is prepared by adhering a ferroelectric single crystal plate to a substrate by a conductive adhesive or metal layer, the ferroelectric single crystal plate being polished before or after the adhesion with the substrate.

Abstract: A semiconductor integrated circuit device and a method of manufacturing the same. The surface of a substrate of an active region surrounded by an element isolation trench is horizontally flat in the center portion of the active region but falls toward the side wall of the element isolation trench in the shoulder portion of the active region. This inclined surface contains two inclined surfaces having different inclination angles. The first inclined surface near the center portion of the active region is relatively steep and the second inclined surface near the side wall of the element isolation trench is gentler than the first inclined surface. The surface of the substrate in the shoulder portion of the active region is wholly rounded and has no angular portion.

Abstract: A novel silicon micromirror structure for improving image fidelity in laser pattern generators is presented. In some embodiments, the micromirror is formed from monocrystalline silicon. Analytical—and finite element analysis of the structure as well as an outline of a fabrication scheme to realize the structure are given. The spring constant of the micromirror structure can be designed independently of the stiffness of the mirror-surface. This makes it possible to design a mirror with very good planarity, resistance to sagging during actuation, and it reduces influence from stress in reflectivity-increasing multilayer coatings.

Abstract: An isolation method of active area for semiconductor forms an isolated active area in a substrate. The substrate is a p-type silicon substrate. A pad oxide layer is formed on the substrate. A patterned sacrificial layer and an upper mask layer are formed on the pad oxide layer, where the upper mask layer is formed over the isolation region of the substrate. A gap is formed between the patterned sacrificial layer and the upper mask layer. An implantation process is performed to dope ions into the substrate through the gap, which forms an n-type barrier to surround the active areas. Lastly, the patterned sacrificial layer is stripped, and an anodization process is utilized to convert p-type bulk silicon into porous silicon. Then, an oxidation process is performed to oxidize the porous silicon to form a silicon dioxide isolation region for the active areas.

Abstract: A trench is formed in the surface of a provided semiconductor body. An oxide is deposited in the trench and a cap is deposited on the oxide, wherein the combination of the cap and the oxide impart a mechanical stress on the semiconductor body.

Abstract: A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a depth. The method additionally includes forming a liner within the trench, the liner lining the sidewalls and bottom of the trench. Furthermore, the method includes filling the trench to a first depth with a first oxide. The first oxide is filled using a spin-on process. The method also includes performing a first densification process on the first oxide within the trench. In addition, the method includes depositing a second oxide within the trench using an HDP process to fill at least the entirety of the trench. The method also includes performing a second densification process on the first and second oxides within the trench.

Abstract: A plurality of trenches are provided in a semiconductor layer and integrated by thermal oxidation to form an insulating region having void parts therein. The thickness of the insulating region can be controlled by the depth of the trenches. This makes it possible to form the insulating region having a thickness larger than that formed by using a conventional LOCOS method, without increasing crystal defects and the like. By providing the insulating region, for example, below an electrode pad, a stray capacitance can be reduced. Moreover, the stray capacitance can be further reduced by the void parts inside the insulating region.

Abstract: A method for forming a feature in a substrate, where residue within the feature can be easily removed. An upper sidewall portion of the feature is formed, where the upper sidewall portion forms a void in the substrate. The upper sidewall portion has an upper sidewall angle. A lower sidewall portion of the feature is formed, where the lower sidewall portion forms a void in the substrate. The lower sidewall portion has a lower sidewall angle. The upper sidewall angle of the upper sidewall portion is shallower than the lower sidewall angle of the lower sidewall portion. By forming the feature with a shallower sidewall angle at the top of the feature, any debris within the feature is more susceptible to rinsing, etching, or other cleaning procedures, and thus the feature is more easily cleaned than standard features having relatively steeper sidewalls.

Abstract: The present invention is a front-side contact, back-side illuminated (FSC-BSL) photodiode arrays and front-side illuminated, back-side contact (FSL-BSC) photodiode arrays having improved characteristics, including high production throughput, low-cost manufacturing via implementation of batch processing techniques; uniform, as well as high, photocurrent density owing to presence of a large continuous homogeneous, heavily doped layer; and back to front intrachip connections via the homogenous, heavily doped layers on the front and back sides of the substrate.

Abstract: The present invention provides a process of manufacturing an isolation structure for use in a semiconductor device. The process includes forming an opening in a substrate through a patterned photoresist layer 225 and a hardmask layer 215 located over the substrate 205 with plasma, trimming the photoresist layer 225 with a plasma to create an exposed portion 215a of the hardmask layer 215, removing the exposed portion 215a with a plasma to create a trench guide opening 227, and creating a trench 230 through the trench guide opening 227 with a plasma.

Abstract: A FinFET and a fabrication method thereof. The FinFET device includes an SOI substrate realized through a substrate, a buried oxide layer formed on the substrate, and a silicon epitaxial layer formed on predetermined areas of the buried oxide layer. A gate oxide layer is formed on the silicon epitaxial layer, and a gate electrode is formed on the gate oxide layer. A field insulator is formed on exposed areas of the buried oxide layer to thereby separate adjacent silicon epitaxial layers. Side surfaces of the silicon epitaxial layer are flattened through heat treatment. The fabrication method for a FinFET device includes forming the gate oxidation layer and the gate electrode on the SOI substrate; forming the mask pattern on the gate electrode; forming the trench by etching using the mask pattern as a mask; performing heat treatment to flatten the side surfaces of the silicon epitaxial layer; and forming the field insulator in the trench.

Abstract: A method for rounding the bottom corners of a trench is described. In the method, an etching process is performed using a fluorocarbon compound with at least two carbon atoms, He and O2 as an etching gas to round the bottom corners of the trench.

Abstract: The invention forms integrated circuit devices of similar structure and dissimilar depth, such as interconnects and inductors, simultaneously. The invention deposits a conformal polymer over an area on a substrate with vias and an area without vias. Simultaneously, cavities are formed in the areas with and without vias. The depth of the cavities formed in the areas with vias will extend deeper into the substrate than the cavities formed in areas without vias. Such occurs because the polymer deposits unevenly along the surface of the substrate and more specifically, more thinly in areas with underlying depressions. Once filled with a conductive material, cavities which extend more deeply into the substrate, which were formed in areas with vias, become inductors, and the cavities which extend less deeply into the substrate, which were formed in areas without vias, become interconnects.

Abstract: A semiconductor substrate including a first region, a second region larger than the first region and an isolation region is provided. A mask layer is selectively formed on the first and second regions. A trench is formed on the isolation region. A first isolation material is deposited on the entire surface so that the trench is filled with the first material and the first material covers the first and second regions. The first material is subjected to a chemical mechanical polish so that the mask layer formed on the first region is exposed while the mask layer formed on the second region is still covered by the first material. Then, a second insulation material is deposited on the exposed mask layer and the first material. Finally, the second material is subjected to the chemical mechanical polish so that mask layer formed on the first and second regions is substantially exposed.

Abstract: Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.

Abstract: A method for forming a standoff structure for devices, e.g., optical devices, integrated circuit devices, micro-electrical mechanical systems (i.e., MEMS). The method includes providing a substrate (e.g., silicon wafer), which has a first surface region characterized by a <100> crystal orientation, a second surface region, and a thickness defined between the first surface region and the second surface region. The method includes protecting selected portions of the first surface region using a masking layer while leaving a plurality of unprotected regions. Each of the unprotected regions is to be associated with an opening through the thickness of the substrate. The method includes immersing the substrate into an etching solution. The method also includes causing removal of the plurality of unprotected regions to form a plurality of openings through the entirety of the thickness of the substrate using the etching solution.

Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.

Abstract: The present invention relates to a shallow trench isolation method of a semiconductor wafer which fills dielectric material into shallow trenches between components on the surface of the semiconductor wafer to electrically isolate the components. This method can prevent dishing phenomenon from occurring over the surface of some wider shallow trenches when a chemical-mechanical polishing method is used to polish the surface of the dielectric material filled in each shallow trench.

Abstract: An integrated circuit device structure can be formed by forming an implant mask having a window therein on a structure including upper and lower Si layers and an intermediate SiGex layer therebetween. Ions are implanted through the upper Si layer and into a portion of the intermediate SiGex layer exposed through the window in the implant mask and blocking implantation of ions into portions of the intermediate SiGex layer outside the window. The portions of the intermediate SiGex layer outside the window are etched and the portion of the intermediate SiGex layer exposed through the window having ions implanted therein is not substantially etched to form a patterned intermediate SiGex layer.

Abstract: According to one embodiment, a structure comprises a substrate and a field oxide region, where the field oxide region has a top surface, and where the top surface of the field oxide region comprises substantially no cavities caused by lateral etching. The structure further comprises a trench situated in the substrate, where the trench has a first sidewall and a second sidewall in the substrate, and where the trench is situated directly underneath the field oxide region. According to this embodiment, the trench is used as a deep trench isolation region in the substrate and is typically filled with polysilicon. A thermally grown oxide liner is situated on the first and the second sidewalls of the trench, where the oxide liner is formed after removal of a hard mask. The hard mask may be densified TEOS oxide or HDP oxide and may be removed in an anisotropic dry etch process.

Abstract: A method for forming a trench having rounded corners in a semiconductor device comprises providing a substrate; forming a first pad oxide layer, a first silicon nitride layer, and a first oxide layer on the substrate sequentially; removing portions of the first oxide layer, the first silicon nitride layer, the first pad oxide layer, and the substrate to form at least one trench; and removing portions of the first oxide layer, the first silicon nitride layer, and the first pad oxide layer in the trench above an upper corner of the substrate in the trench. The substrate includes a lower corner at a bottom of the trench.