Abstract: A semiconductor device is formed with extended STI regions. Embodiments include implanting oxygen under STI trenches prior to filling the trenches with oxide and subsequently annealing. An embodiment includes forming a recess in a silicon substrate, implanting oxygen into the silicon substrate below the recess, filling the recess with an oxide, and annealing the oxygen implanted silicon. The annealed oxygen implanted silicon extends the STI region, thereby reducing leakage current between N+ diffusions and N-well and between P+ diffusions and P-well, without causing STI fill holes and other defects.

Abstract: A through silicon via (TSV) and a deep trench capacitor (DTCap) or a deep trench isolation (DTI) are simultaneously formed on the same substrate by a single mask and a single reactive ion etching (RIE). The TSV trench is wider and deeper that the DTCap or DTI trench. The TSV and DTCap or DTI are formed with different dielectric materials on the trench sidewalls. The TSV and DTCap or DTI are perfectly aligned.

Abstract: A semiconductor device includes a source, a drain, and a gate configured to selectively enable a current to pass between the source and the drain. The semiconductor device includes a drift zone between the source and the drain and a first field plate adjacent the drift zone. The semiconductor device includes a dielectric layer electrically isolating the first field plate from the drift zone and charges within the dielectric layer close to an interface of the dielectric layer adjacent the drift zone.

Abstract: A through silicon via (TSV) and a deep trench capacitor (DTCap) or a deep trench isolation (DTI) are simultaneously formed on the same substrate by a single mask and a single reactive ion etching (RIE). The TSV trench is wider and deeper that the DTCap or DTI trench. The TSV and DTCap or DTI are formed with different dielectric materials on the trench sidewalls. The TSV and DTCap or DTI are perfectly aligned.

Abstract: The present invention relates to aqueous two-component adhesion promoter compositions and also to their use in methods of adhesive bonding or sealing. Additionally it relates to packaging consisting of the two-component composition and also a pack having two chambers. The two-component adhesion promoter composition is composed of a first component K1 comprising at least one organoalkoxysilane S and at least one anhydrous surfactant T; and of a second component K2 comprising at least water and at least one acid, the acid being present in an amount such that, after components K1 and K2 have been mixed, the resulting mixture is acidic.

Abstract: Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 ?m into the substrate. The isolating structure prevents photons and electrons originating in peripheral circuitry from reaching the active area. Where the substrate has a heavily-doped lower layer and an upper layer on it, the trench can extend through the upper layer to the lower layer. A thermal oxide can be grown on the trench walls. A liner can also be deposited on the sidewalls of each trench. A fill material having a high-extinction coefficient is then deposited over the liner. The liner can also be light absorbent so that both the liner and fill material block photons.

Abstract: A CMOS image sensor includes a photosensitive device, a floating diffusion region, a transfer transistor, and a pocket photodiode formed in a semiconductor substrate of a first conductivity type. The floating diffusion region is of a second conductivity type. The transfer transistor has a channel region disposed between the photosensitive device and the floating diffusion region. The pocket photodiode is of the second conductivity type and is formed under a first portion of a bottom surface of the channel region such that a second portion of the bottom surface of the channel region abuts the semiconductor substrate.

Abstract: First, on a semiconductor region of a first conductivity type, a trapping film is formed which stores information by accumulating charges. Then, the trapping film is formed with a plurality of openings, and impurity ions of a second conductivity type are implanted into the semiconductor region from the formed openings, thereby forming a plurality of diffused layers of the second conductivity type in portions of the semiconductor region located below the openings, respectively. An insulating film is formed to cover edges of the trapping film located toward the openings, and then the semiconductor region is subjected to a thermal process in an atmosphere containing oxygen to oxidize upper portions of the diffused layers. Thereby, insulating oxide films are formed in the upper portions of the diffused layers, respectively. Subsequently, a conductive film is formed over the trapping film including the edges thereof to form an electrode.

Abstract: A method of forming a memory device includes forming first and second isolation structures on a semiconductor substrate, the first and second isolation structures defining an active region therebetween; and etching a portion of the semiconductor substrate provided within the active region to define a step profile, so that the active region includes a first vertical portion and an upper primary surface, the first vertical portion extending above the upper primary surface.

Abstract: A metal pattern of the present invention is a metal pattern (13?) formed on a surface of a substrate by etching, and a monomolecular film containing fluorinated alkyl chains (CF3(CF2)n—, where n represents an integer) is formed on a surface of a metal film composing the metal pattern (13?), and a masking film (18) is formed by penetration of a molecule having a mercapto group (—SH) or a disulfide (—SS—) group into interstices between molecules composing the monomolecular film.

Abstract: A method of forming at least one undercut structure in a semiconductor substrate. The method comprises providing a semiconductor substrate, forming at least one doped region in the semiconductor substrate, and removing the at least one doped region to form at least one undercut structure in the semiconductor substrate. The at least one undercut structure may include at least one substantially vertical shelf, at least one substantially horizontal shelf, and at least one faceted surface. The at least one doped region may be formed by implanting an impurity in the semiconductor substrate, which is, optionally, annealed. The at least one doped region may be removed selective to the undoped portion of the semiconductor substrate by at least one of wet etching or dry etching. An intermediate semiconductor structure that comprises a single crystalline silicon substrate and at least one undercut structure formed in the single crystalline silicon substrate is also disclosed.

Abstract: Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 ?m into the substrate. The isolating structure prevents photons and electrons originating in peripheral circuitry from reaching the active area. Where the substrate has a heavily-doped lower layer and an upper layer on it, the trench can extend through the upper layer to the lower layer. A thermal oxide can be grown on the trench walls. A liner can also be deposited on the sidewalls of each trench. A fill material having a high-extinction coefficient is then deposited over the liner. The liner can also be light absorbent so that both the liner and fill material block photons.

Abstract: A CMOS image sensor and a method for fabricating the same are disclosed, in which the boundary between an active region and a field region is not damaged by ion implantation. The method for fabricating a CMOS image sensor includes forming a trench in a first conductive type semiconductor substrate, forming a first conductive type heavily doped impurity ion region in the semiconductor substrate at both sides of the trench, forming a device isolation film by interposing an insulating film between the trench and the device isolation, sequentially forming a gate insulating film and a gate electrode on the semiconductor substrate, and forming a second conductive type impurity ion region for a photodiode in the semiconductor substrate between the gate electrode and the device isolation film.

Abstract: A process for forming isolation and active regions, wherein the patterning of an oxidation-barrier active stack is performed separately in the PMOS and NMOS regions. After the active stack is in place, two masking steps are used: one exposes the isolation areas on the NMOS side, for stack etch, channel-stop implant, and silicon recess etch (optional); the other masking step is exactly complementary, and performs the analogous operations on the PMOS side. After these two steps are performed (in either order), an additional nitride layer can optionally be deposited and etched to cover the sidewall of the active stack. Field oxide is then formed, and processing then proceeds in conventional fashion.

Abstract: A lateral trench in a semiconductor substrate is formed by the following steps. Form a lateral implant mask (LIM) over a top surface of the semiconductor substrate. Implant a heavy dopant concentration into the substrate through the LIM to form a lateral implant region (LIR) in the substrate. Strip the LIM exposing the top surface of the substrate. Form an epitaxial silicon layer over the top surface of the substrate burying the LIR. Form a trench mask over the epitaxial layer. Etch a trench reaching through the epitaxial layer and the LIR. Form oxidized trench sidewalls, an oxidized trench bottom and oxidized sidewalls of the LIR. Etch the oxidized sidewalls of the LIR until the LIR is exposed. Form laterally extending trenches by etching away the LIR.

Abstract: A method for fabricating dielectric isolated silicon islands or regions is described in this invention. A hard composite mask of pad oxide and silicon nitride is first patterned on a silicon substrate and trenches of required dimensions are etched into silicon. After forming an oxide liner on trench surfaces, boron ions are implanted in areas around the trenches such that heavily doped p+ regions are formed. The oxide liner is anisotropically etched with a reactive ion etching process such that only the silicon surface at trench bottom is exposed, leaving the oxide liner on trench walls. Epitaxial silicon is then deposited selectively on exposed single crystal silicon surface so as to fill the trenches. After removing the hard mask, trenches are masked with photo-resist pattern and the wafer is anodically etched in an aqueous bath of HF to form a buried porous silicon layer under and around the trenches. After removing the mask, the porous silicon is then oxidized.

Abstract: An electric field effect transistor of high breakdown voltage and a method of manufacturing the same are disclosed. A recessed portion is formed at the channel region and is filled by a protective oxide layer. Lightly doped source/drain regions are formed under the protective oxide layer. The protective oxide layer protects the lightly doped source/drain regions. Accordingly, the protective oxide layer prevents the electric field from being concentrated to a bottom corner portion of the gate structure. In addition, the effective channel length is elongated since an electric power source is connected to heavily doped source/drain regions from an outside source of the transistor, instead of being connected to lightly doped source/drain regions.

Abstract: Silica dielectric films, whether nanoporous foamed silica dielectrics or nonporous silica dielectrics are readily damaged by fabrication methods and reagents that reduce or remove hydrophobic properties from the dielectric surface. The invention provides for methods of imparting hydrophobic properties to such damaged silica dielectric films present on a substrate. The invention also provides plasma-based methods for imparting hydrophobicity to both new and damaged silica dielectric films. Semiconductor devices prepared by the inventive processes are also provided.

Abstract: A trench isolation having a sidewall and bottom implanted region located within a substrate of a first conductivity type is disclosed. The sidewall and bottom implanted region is formed by an angled implant, a 90 degree implant, or a combination of an angled implant and a 90 degree implant, of dopants of the first conductivity type. The sidewall and bottom implanted region located adjacent the trench isolation reduces surface leakage and dark current.

Abstract: A method for forming an isolation layer of a semiconductor device. The method includes: a) sequentially laminating a pad oxide layer and pad nitride layer on a semiconductor substrate; b) selectively removing the pad nitride layer, selectively removing the pad oxide layer and the substrate, thereby forming a trench in the substrate; c) implanting ions in a direction with a tilted angle into a side wall of the pad nitride layer located in an upper side of the trench; d) removing the side wall portion of the pad nitride layer in the trench, in which the ions are implanted, to form a sloped side wall of the pad nitride layer, wherein the sloped side wall is inclined in an inverse direction; e) filling a HDP oxid layer in an upper surface of an entire structure including the trench; f) planarizing the HDP oxide layer and the pad nitride layer; and g) removing a remaining pad nitride layer, thereby forming an isolation layer.

Abstract: A manufacturing method for an integrated circuit memory includes providing a semiconductor substrate and depositing a charge-trapping dielectric layer. First and second bitlines are implanted and a wordline layer is deposited. A hard mask layer is deposited over the wordline layer. A photoresist is deposited over the wordline layer and used to form a hard mask. The photoresist is removed. The wordline layer is processed using the hard mask to form a wordline and the hard mask is removed. A reduced hydrogen, ultra-violet block data retention liner covers the wordline and the charge-trapping dielectric layer. The reduced hydrogen levels reduce the charge loss compared to prior art. The surface of the liner is processed to block UV light before completing the integrated circuit.

Abstract: A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep implantation region. The deep implantation region is formed at various process stages according to embodiments. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.

Abstract: A method of fabricating a memory device. A plurality of isolation structures and a plurality of stacked gate structures are sequentially formed on a substrate. While defining the stacked gate structures, the isolation structures are over etched to form a plurality of trenches. A material layer is filled into the trenches. A patterned photoresist layer is formed on the substrate, while a part of the substrate predetermined for forming a drain region is exposed. An ion implantation step is performed to implant a dopant into the part of substrate predetermined for forming the drain region, such that a well is formed. As the trenches are filled with the material layer, the dopant cannot penetrate therethrough.

Abstract: A light receiving device includes a semiconductor substrate, a light absorbing layer provided on the semiconductor substrate, a window layer provided on the light absorbing layer, a wavelength filter provided on the window layer, and a diffusion region provided in the wavelength filter and the window layer. A forbidden bandwidth of the wavelength filter is smaller than a forbidden bandwidth of the window layer, and a forbidden bandwidth of the light absorbing layer is smaller than the forbidden bandwidth of the wavelength filter.

Abstract: A semiconductor flash memory device is formed with shallow trench isolation (STI) and a low-resistance source bus line (Vss Bus). Embodiments include forming core and peripheral field oxide regions, as by conventional STI techniques, bit lines by ion implantation, polysilicon floating gates above the channel regions and polysilicon word lines. The Vss Bus is then formed by etching away portions of the field oxide between corresponding source regions of adjacent bit lines to expose portions of the substrate, ion implanting impurities into the source regions and the exposed substrate, forming insulating spacers on the sides of the floating gates and word lines, and forming a metal silicide layer, such as titanium silicide, on the implanted source regions and exposed portions of the substrate to form a continuous conductor between the source regions.

Abstract: A structure and a process for manufacturing semiconductor devices with improved ESD protection for high voltage applications is described. A thick field gate oxide N channel field effect transistor (FET) device with a tunable threshold voltage (Vt) is developed at the input/output to the internal active circuits for the purpose of providing ESD protection for applications in the 9 volt and higher range. The FET threshold voltage determines the ESD protection characteristics. A N-field implant is used to provide a dopant region under the thick oxide gate element which has the effect of modifying the threshold voltage (Vt) of this device enabling the device turn-on to be “tuned” to more closely match the application requirements of the internal semiconductor circuits. The gate electrical contact is completed by using either a metal gate electrode or polysilicon gate element.

Abstract: A method of forming a semiconductor component having a conductive line (24) and a silicide region (140) that crosses a trench (72). The method involves forming nitride sidewalls (127) to protect the stack during the silicidation process.

Abstract: This is a method for forming a recessed LOCOS isolation region, which includes the steps of forming a first silicon nitride layer between the pad oxide layer and a polysilicon buffer layer and a second nitride layer over the polysilicon buffer layer. In addition, the method for forming LOCOS isolation regions can include the additional steps of forming a sidewall seal around the perimeter of the active moat regions prior to the field oxidation step. The resulting field oxide isolation regions have provided a low-profile recessed field oxide with reduced oxide encroachment into the active moat region.

Abstract: With the present invention, a filled isolation trench is fabricated as part of an integrated circuit on a semiconductor wafer using nitrogen implantation into at least one side wall of the isolation trench. An isolation trench is etched within a layer of semiconductor material. The isolation trench has at least one side wall comprised of the semiconductor material, and the isolation trench has a bottom wall. Nitrogen ions are implanted into the at least one side wall of the isolation trench. A layer of an insulator material is thermally grown from the at least one side wall and the bottom wall of the isolation trench. The isolation trench is then filled with the insulator material using a deposition process to form the filled isolation trench. With the present invention, the nitrogen ions implanted into the at least one side wall of the isolation trench reduce a radius of a bird's beak formed on the at least one side wall of the isolation trench.

Abstract: An integrated circuit memory device includes a semiconductor substrate having a memory cell area and a select transistor area. A first field insulation layer is included in the memory cell area, and a first channel stop impurity layer is included beneath the first field insulation layer. The first channel stop impurity layer is narrower than the first field insulation area. A second field insulation layer is included in the select transistor area, and a second channel stop impurity layer is included beneath the second field insulation layer. The second channel stop impurity layer is wider than the second field insulation layer. Integrated circuit memory devices are fabricated by defining a memory cell area and a select transistor area of a semiconductor substrate. The memory cell area includes a memory cell active area and a memory cell field area. The select transistor area includes a select transistor active area and a select transistor field area.

Abstract: A polysilicon film is deposited in a trench formed in a silicon element substrate. The polysilicon film in the trench and on the silicon element substrate is anisotropically etched, so that the film remains on the side wall of the trench. The polysilicon film on the side wall is oxidized to obtain an insulating film, which buries the trench. At the same time, an oxidized film is formed on the surface of the silicon element substrate to complete a trench-mold separation area.

Abstract: A method for forming a shallow trench isolation structure in a substrate includes the steps of forming a doped region around the future top corner regions of a trench. The concentration of dopants inside the doped region increases towards the substrate surface. Thereafter, a trench is formed in the substrate, and then a thermal oxidation operation is carried out. Utilizing the higher oxidizing rate for doped substrate relative to an undoped region, the upper corners of the trench become rounded corners. Subsequently, a liner oxide layer is formed over the substrate surface inside the trench using conventional methods. Finally, insulating material is deposited into the trench to form a trench isolation structure.

Abstract: The preferred embodiment of the present invention overcomes the disadvantages of the prior art by using hybrid resist to define a sidewall spacer region and form a new type of sidewall spacer. The preferred method allows for more controlled doping at the gate-source and gate-drain junctions by defining sidewall spacer troughs using hybrid resist. Implants can then be made through the troughs to precisely control the doping at the gate junctions. Additionally, sidewall spacers can then be formed in the sidewall spacer troughs. The dimensions of the sidewall spacers is determined by the hybrid resist and can thus be made smaller than traditional resist processes. Additionally, forming the sidewall spacers using hybrid resist allows for their width to be determined independent of the depth of the gate material.

Abstract: A method of fabricating a semiconductor device, including the steps of (a) forming a channel at a surface of a semiconductor substrate only in the center of a region X which physically and electrically isolates adjacent regions Y in each of which a device is to be fabricated, and (b) forming a silicon oxide layer over the region X for physically and electrically isolating the adjacent regions Y from each other. The method suppresses dimensional shift and occurrence of a stress, and further makes it difficult for the reverse narrow channel effect to occur only by adding the small number of additional steps thereto.

Abstract: A method of forming an isolation layer of a semiconductor device including active regions on a substrate and device isolation regions for isolating the active regions from one another includes the steps of forming a nitride layer on the active region of a semiconductor substrate, forming trenches of a predetermined depth in the semiconductor substrate at peripheral portions of the device isolation regions, and filling the trenches with a nitride material and performing a field oxidation process.

Abstract: A method for rapid thermally annealing a thin amorphous film on a transparent substrate with the use of a radiation absorption film is provided. Unlike a transmissive silicon thin film, or transparent substrate, the metal absorptive film has excellent radiation absorption characteristics. When a radiation absorption layer is added to the substrate it is possible to rapidly anneal an amorphous silicon film with convention IC process radiation lamps. The metal absorption film also acts to conduct the heat to the amorphous silicon. The control provided by the choice of metal material, metal thickness, the oxidation of the metal surface, and the heat and duration of the RTA process provide unique opportunities to control the crystallization process. Polysilicon made by the above-described method has the potential of high electron mobility and low production costs. A thin-film structure for use in a TFT, made through the above-described method, is also provided.

Abstract: A method for the fabrication of a semiconductor device is characterized by a series of steps comprising successively forming a trench in a field region of monosilicon substrate and forming an oxidation-preventive layer and a silicon layer in the trench, and oxidizing the silicon layer into a field oxide film to produce a channel stop region beneath the trench in the substrate. The method alternatively comprises forming a trench having a small pattern in a field region of a monosilicon substrate, sequentially forming an oxidation-preventive layer and a silicon layer on the surface of the trench, and oxidizing the silicon layer and the substrate of a field region having a large pattern size, at the same time, to produce a field oxide film and channel stop diffusion regions below both the trench and the field oxide film having a large pattern.

Abstract: A method for developing shallow trench isolation in a semiconductor device includes forming an ion diffusion area by implanting fluorine ions where a trench is to be formed in a semiconductor substrate before forming the trench, performing an annealing process or a tilt ion implantation process to diffuse the fluorine ions into both sides corresponding to the upper corners of the trench, wherein the fluorine implantation process increases the oxidation rate of the upper corners of the trench to be more than that of the semiconductor substrate when a light oxidation proceeds for preventing damage to the semiconductor substrate in forming the trench. Accordingly, the upper corner portions of the trench are formed to be rounded so as to distribute an electric field, thereby preventing a hump phenomenon when the completed semiconductor memory device is operated.

Abstract: A method is provided for forming an isolation structure at a semiconducting surface of a body, and the isolation structure formed thereby. A masking layer is formed over selected regions of the substrate surface; the masking layer preferably comprising a nitride layer overlying a pad oxide layer. The masking layer is patterned and etched to form openings exposing selected regions of the substrate surface. Recesses are formed into the substrate in the openings. Preferably a portion of the pad oxide layer is isotropically etched under the nitride layer forming an undercut region. An etch stop layer is formed over the substrate in the recesses filling in the undercut along the sidewalls. A second masking layer, preferably of nitride is formed over the etch stop layer and anisotropically etched to form nitride sidewalls in the openings. The etch stop layer may be etched away from the horizontal surfaces.

Abstract: Thermal dye sublimation transfer recording element for receiving sublimable basic dye-precursors, comprising a support having thereon a dye-developing layer containing a dye-developing copolymer having sulfonic acid side-groups that can react with the basic dye-precursor to produce a dye image, characterized in that said dye-developing vinyl copolymer comprises plasticizing comonomers, the weight percentage of plasticizing comonomers in the dye-developing vinyl copolymer being such that the glass transition temperature of the dye-developing vinyl copolymer is between 30.degree. C. and 90.degree. C.