Abstract: Apparatus, systems and methods relating to the reconstruction of semiconductor wafers for wafer-level processing are disclosed. Selected semiconductor dice having alignment cavities formed in a surface thereof are placed in contact with liquid, gel or other flowable alignment droplets in a similar pattern protruding from a substrate to position the dice through surface tension interaction. The alignment droplets are then solidified to maintain the positioning and an underfill is disposed between the dice and the fixture to strengthen and maintain the reconstructed wafer. A fixture plate may be used in combination with the underfill to add additional strength and simplify handling. The reconstructed wafer may be subjected to wafer-level processing, wafer-level testing and burn-in being particularly facilitated using the reconstructed wafer.

Abstract: InP epitaxial material is directly bonded onto a Silicon-On-Insulator (SOI) wafer having Vertical Outgassing Channels (VOCs) between the bonding surface and the insulator (buried oxide, or BOX) layer. H2O and other molecules near the bonding surface migrate to the closest VOC and are quenched in the buried oxide (BOX) layer quickly by combining with bridging oxygen ions and forming pairs of stable nonbridging hydroxyl groups (Si—OH). Various sizes and spacings of channels are envisioned for various devices.

Abstract: An electronic device comprises a substrate comprising a first surface and a second surface, a substrate carrier comprising a first surface and a second surface, and an inorganic material bonding the second surface of the substrate and the second surface of the substrate carrier.

Abstract: According to some embodiments, a conducting layer is formed on a first wafer. An insulating layer is formed on a second wafer. The insulating layer includes a cavity and a conducting area may be formed in the second wafer proximate to the cavity. The side of the conducting layer opposite the first wafer is bonded to the side of the insulating layer opposite the second wafer. At least some of the first wafer is then removed, without removing at least some of the conducting layer, to form a conducting diaphragm that is substantially parallel to the second wafer. In this way, an amount of capacitance between the diaphragm and the conducting area may be measured to determine an amount of pressure being applied to the diaphragm.

Abstract: A substrate gap adjusting device adjusts a gap between first and second substrates in a composite substrate. In the substrate gap adjusting device, the composite substrate includes the first substrate; the second substrate that is oppositely bonded to the first substrate through a sealant, the second substrate having a smaller area than the first substrate; and liquid crystal that is injected into a space surrounded by the first substrate, the second substrate, and the sealant.

Abstract: Techniques are disclosed for fabricating a relatively thin package for housing a micro component, such as an opto-electronic or MEMs device. The packages may be fabricated in a wafer-level batch process. The package may include hermetically sealed feed-through electrical connections coupling the micro component to electrical contacts on an exterior surface of the package.

Abstract: An electrical device includes an interconnect and a pair substrates at least one of which includes an integrated circuit, the pair of substrates being bonded together by a bond that includes a structure having multiple widths and a composition that is selected from the group consisting of a graded material and a first material upon a second material.

Abstract: A method and apparatus for underfilling a gap between a semiconductor die or device and a substrate, where the semiconductor die or device is electrically connected to the substrate so that an active surface of the semiconductor die is facing a top surface of the substrate with the gap therebetween. A silane layer is applied to the active surface of the semiconductor die, the upper surface of the substrate, and/or both to increase the surface tension thereon. The increased surface tension thereby allows the underfill material to fill the gap via capillary action in a lesser flow time more effectively, and therefore, is more efficient than conventional underfilling methods.

Abstract: A technique for manufacturing a micro-electro-mechanical (MEM) device includes a number of steps. Initially, a first wafer is provided. Next, a bonding layer is formed on a first surface of the first wafer. Then, a portion of the bonding layer is removed to provide a cavity including a plurality of spaced support pedestals within the cavity. Next, a second wafer is bonded to at least a portion of the bonding layer. A portion of the second wafer provides a diaphragm over the cavity and the support pedestals support the diaphragm during processing. The second wafer is then etched to release the diaphragm from the support pedestals.

Abstract: A wafer having a plurality of through holes is provided, and a glass wafer is disposed on the wafer. A plate having a plurality of concave cavities is disposed on the glass wafer, wherein the concave cavities corresponding to the through holes of the wafer so that a part of the plate corresponding to the through holes is not in contact with the glass wafer. A voltage source is provided, and two electrodes thereof respectively have electrical connections to the wafer and the plate. The wafer and the glass wafer are bonded to each other by the anodic bonding method so that a plurality of optical device caps are formed.

Abstract: The present invention provides a semiconductor structure that includes a high performance field effect transistor (FET) on a semiconductor-on-insulator (SOI) in which the insulator thereof is a stress-inducing material of a preselected geometry. Such a structure achieves performance enhancement from uniaxial stress, and the stress in the channel is not dependent on the layout design of the local contacts. In broad terms, the present invention relates to a semiconductor structure that comprises an upper semiconductor layer and a bottom semiconductor layer, wherein said upper semiconductor layer is separated from said bottom semiconductor layer in at least one region by a stress-inducing insulator having a preselected geometric shape, said stress-inducing insulator exerting a strain on the upper semiconductor layer.

Abstract: A stacked electronics module comprises a first layer including a first substrate having a front side and a backside, a first electrical interconnect layer disposed on the first substrate and a first electronic device disposed on the front side of the first substrate. In addition, the stacked electronics module comprises a second layer including a second substrate having a front side and a backside, a second electrical interconnect layer disposed on the second substrate and a second electronic device disposed on the front side of the second substrate.

Abstract: One embodiment of the present invention provides an integrated chip module and a corresponding method of manufacture that facilitates proximity communication. This module includes a base chip and a bridge chip, both of which include an active face, upon which active circuitry and signal pads reside, and a back face opposite the active face. The active face of the bridge chip is bonded to the active face of the base chip, and the back face of the bridge chip is thinned via planarization or polishing.

Abstract: A cap wafer with patterned film formed thereon is etched through areas not covered by the patterned film to form a plurality of openings. Then, the cap wafer is bonded to a transparent wafer, and the cap wafer around the pattern film is segmented to form a plurality of cap structures. A device wafer with a plurality of devices and a plurality of contact pads electrically connected to the devices is subsequently provided. The cap structures and the device wafer are hermetically sealed to form a plurality of hermetic windows on the devices.

Abstract: A structure and method for thermal management of integrated circuits. The structure for thermal management of integrated circuits includes first and second substrates bonded together, at least one of the first and second substrates including at least one circuit element, an entrance through-hole having a length extending through a thickness of at least one of the first substrate and the second substrate, an exit through-hole having a length extending through a thickness of at least one of the first substrate and the second substrate, a bonding element forming a seal between the first and second substrates and forming a space between the first and second substrate, and a coolant channel formed in the space between the first and second substrates such that a fluid entering the entrance through-hole transits the coolant channel and the exit through-hole to provide cooling to the circuit element.

Abstract: An electronic package for a photo-sensing device is provided. The package is formed to include a substrate of a material substantially transparent to light within a predetermined range of wavelengths. The package further formed to include at least one photo-sensing die having a photo-sensing area defined on a front side thereof. The photo-sensing die is mounted to the substrate by a plurality of interconnection joints disposed about the photo-sensing area, whereby the front side of the photo-sensing die is spaced by a gap from a front surface of the substrate. A sealing structure is formed to extend about the interconnection joints to fill portions of the gap thereabout, such that the sealing structure contiguously encloses an internal cavity in substantially sealed manner between the photo-sensing die and substrate. This internal cavity communicates with the photo-sensing area of the photo-sensing die.

Abstract: A method of manufacturing a device includes doping a low voltage threshold area and a high voltage threshold area. Gate structures are formed over the low voltage threshold and high voltage threshold areas while protecting the gate structure over the low voltage threshold area. A silicidation process is performed over the high voltage threshold area while the gate structure over the low voltage threshold area remains protected. Siliciding includes depositing metal on the gate of the high voltage threshold area and annealing the metal, the metal is deposited either by CVD or sputtering followed by anneal to fully suicide the gate structure of the high voltage threshold area. The metal, preferably cobalt or nickel is deposited to a thickness of approximately 500 ?, annealed for about 3 minutes at about 400° C.

Abstract: A method for reducing stress and warpage in flip chip packages comprising providing a flip chip package including an organic substrate, an integrated circuit chip, and a cap member, providing a temporary structure having a coefficient of thermal expansion that is substantially similar to a coefficient of thermal expansion of the integrated circuit chip, soldering a bottom side of the organic substrate to a top side of the temporary structure, bonding a bottom side of the integrated circuit chip to a top side of the organic substrate with controlled chip collapse columns, coupling the cap member to the top side of the organic substrate, applying force to the flip chip package in a first direction, and applying force to the temporary structure in a second direction opposite the first direction in order to shear the top side of the temporary structure from the bottom side of the organic substrate to remove the temporary structure from the flip chip package.

Abstract: A method of fabricating and separating semiconductor structures comprises the steps of: (a) partially forming a semiconductor structure attached to a support structure, the partially formed semiconductor structure comprising a plurality of partially formed devices, where the partially formed devices are attached to one another by at least one connective layer; (b) forming a partial mask layer over at least a part of the partially formed devices; (c) etching the connective layer to separate the devices; and (d) removing the partial mask layer. Advantages of the invention include higher yield than conventional techniques. In addition, less expensive equipment can be used to separate the devices. The result is a greater production of devices per unit of time and per dollar.

Abstract: A photoelectric device grinding process comprising the following steps is disclosed. A wafer comprising a plurality of chip units is provided. Each chip unit has at least a photoelectric device disposed on a surface layer. A dielectric substrate is attached to the wafer with glue having a plurality of spacers therein such that the photoelectric devices face the dielectric layer. The spacers maintain a gap between the dielectric substrate and the wafer. Thereafter, the dielectric substrate surface away from the wafer or the wafer surface away from the dielectric substrate or both is ground. The grinding process is particularly suitable for preventing any possible damage to the photoelectric devices on a wafer.

Abstract: Systems and methods for forming an electrostatic MEMS plate switch include forming a deformable plate on a first substrate, forming the electrical contacts on a second substrate, and coupling the two substrates using a hermetic seal. The deformable plate may have a flexible shunt bar which has one end coupled to the deformable plate, and the other end coupled to a contact on the second substrate. Upon activating the switch, the deformable plate urges the shunt bar against a second contact formed in the second substrate, thereby closing the switch. The hermetic seal may be a gold/indium alloy, formed by heating a layer of indium plated over a layer of gold. Electrical access to the electrostatic MEMS switch may be made by forming vias through the thickness of the second substrate.

Abstract: A MEMS (micro electro-mechanical system) semiconductor device and a method for producing such a device. A preferred embodiment of the present invention comprises the a wafer having a continuous BCS (bondline control structure) surrounding a MEMS active area that is affixed to an interposer layer, which is in turn affixed to a cover to form a sealed cavity over the surface of the MEMS. To fabricate this device, a wafer is populated with MEMS devices. The BCS is formed in the same process step as a device structure, for example a spacer layer. The BCS remains, however, even if all or a portion of this spacer layer is removed. In this way when the reflecting surface of the MEMS device has been formed, an interposer layer may be mounted to the BCS using a filler-less adhesive, and a cover can likewise be affixed to the interposer layer.

Abstract: The present invention provides a solar cell pre-laminate assembly comprising one or more solar cells laminated between two compositionally distinct encapsulant layers, and the method of preparing a solar cell module from such an assembly.

Abstract: A method for forming a device wafer with a recyclable support by providing a wafer having first and second surfaces, with at least the first surface of the wafer comprising a semiconductor material that is suitable for receiving or forming electronic devices thereon, providing a supporting substrate having upper and lower surfaces, and providing the second surface of the wafer or the upper surface of the supporting substrate with void features in an amount sufficient to enable a connecting bond therebetween to form a construct wherein the bond is formed at an interface between the wafer and the substrate and is suitable to maintain the wafer and supporting substrate in association while forming or applying electronic devices to the first surface of the wafer, but which connecting bond is severable at the interface due to the void features to separate the substrate from the wafer so that the substrate can be reused.

Abstract: A method of fabricating thin films of semiconductor materials by implanting ions in a substrate composed of at least two different elements at least one of which can form a gaseous phase on bonding with itself and/or with impurities includes the following steps: (1) bombarding one face of the substrate with ions of a non-gaseous heavy species in order to implant those ions in a concentration sufficient to create in the substrate a layer of microcavities containing a gaseous phase formed by the element of the substrate; (2) bringing this face of the substrate into intimate contact with a stiffener; and (3) obtaining cleavage at the level of the microcavity layer by the application of heat treatment and/or a splitting stress.

Abstract: A system and method for manufacturing micro cavities at the wafer level using a unique, innovative MEMS (MicroElectroMechanical Systems) process, wherein micro cavities are formed, with epoxy bonded single-crystalline silicon membrane as cap and deposited and/or electroplated metal as sidewall, on substrate wafers. The epoxy is also the sacrificial layer. It is removed from within the cavity through small etch access holes etched in the silicon cap before the etch access holes are sealed under vacuum. The micro cavities manufactured therein can be used as pressure sensors or for packaging MEMS devices under vacuum or inert environment. In addition, the silicon membrane manufactured therein can be used to manufacture RF switches.

Abstract: A cell suitable for use with an atomic clock and a method for making the same, the cell including: a silicon wafer having a recess formed therein; at least one amorphous silicate member having an ion mobility and temperature expansion coefficient approximately that of silicon sealing the recess; and, an alkali metal containing component and buffer gas contained in the recess. The method includes: providing a silicon wafer; forming a cavity through the silicon wafer; introducing an alkali metal containing component and buffer gas into the cavity; and, anodically bonding at least one amorphous silicate member having an ion mobility and temperature expansion coefficient approximately that of silicon to the wafer to close the cavity.

Abstract: A method which is intended to facilitate and/or simplify the process of fabricating interlayer vias by selective modification of the FEOL film stack on a transfer wafer is provided. Specifically, the present invention provides a method in which two dimensional devices are prepared for subsequent integration in a third dimension at the transition between normal FEOL processes by using an existing interlayer contact mask to define regions in which layers of undesirable dielectrics and metal are selectively removed and refilled with a middle-of-the-line (MOL) compatible dielectric film. As presented, the inventive method is compatible with standard FEOL/MOL integration schemes, and it guarantees a homogeneous dielectric film stack specifically in areas where interlayer contacts are to be formed, thus allowing the option of a straightforward integration path, if desired.

Abstract: A process for fabricating a micro-electro-mechanical system (MEMS) composed of fixed components fixedly supported on a lower substrate and movable components movably supported on the lower substrate. The process utilizes an upper substrate separate from the lower substrate. The upper substrate is selectively etched in its top layer to form therein a plurality of posts which project commonly from a bottom layer of the upper substrate. The posts include the fixed components to be fixed to the lower substrate and the movable components which are resiliently supported only to one or more of the fixed components to be movable relative to the fixed components. The lower substrate is formed in its top surface with at least one recess. The upper substrate is then bonded to the top of the lower substrate upside down in such a manner as to place the fixed components directly on the lower substrate and to place the movable components upwardly of the recess.

Abstract: A method of singulating electronic devices, including aligning a saw blade over a lid street disposed on a lid substrate that is disposed over a device substrate. An electronic device that includes a bond pad is disposed on the device substrate, wherein the lid street is disposed over the bond pad. In addition, the method also includes sawing partially through the lid street to form a trench in the lid street. The trench includes a trench bottom in the lid substrate.

Abstract: A method of fabricating protective caps for protecting devices on wafer surface includes: (a) providing a non-metal cap substrate and forming a metal layer on the non-metal cap substrate; (b) forming a plurality of cavities on a surface of the metal layer, wherein the location of each cavity corresponds to each of the devices on the wafer surface; and (c) forming a protective cap in each cavity and forming a plurality of bonding media around the cavities.

Abstract: A method of creating a predefined internal pressure within a cavity of a semiconductor device, the method including providing the semiconductor device, the semiconductor device including a semiconductor oxide area which is continuously arranged between the cavity of the semiconductor device and an external surface of the semiconductor device, exposing the semiconductor device to an ambient atmosphere with a noble gas at a first temperature for a predetermined time period, and setting a second temperature, which is different from the first, after the predetermined time period has expired, the semiconductor oxide area exhibiting a higher permeability for the noble gas at the first temperature than at the second temperature.

Abstract: A micromachined sensor and a process for fabrication and vertical integration of a sensor and circuitry at wafer-level. The process entails processing a first wafer to incompletely define a sensing structure in a first surface thereof, processing a second wafer to define circuitry on a surface thereof, bonding the first and second wafers together, and then etching the first wafer to complete the sensing structure, including the release of a member relative to the second wafer. The first wafer is preferably a silicon-on-insulator (SOI) wafer, and the sensing structure preferably includes a member containing conductive and insulator layers of the SOI wafer. Sets of capacitively coupled elements are preferably formed from a first of the conductive layers to define a symmetric capacitive full-bridge structure.

Abstract: A MEMS mass spectrometer having metal walls connected between a lid and base, with the walls defining a plurality of interior chambers including sample gas input chambers, an ionizer chamber, a plurality of ion optics chambers and a ion separation chamber. A detector array at the end of the ion separation chamber includes a plurality of V-shaped detector elements positioned along two parallel lines and arranged to intercept all of the ionized beams produced in the mass spectrometer.

Abstract: A method of manufacturing a coaxial trace (100) within a surrounding material (190) includes: providing a first substrate (191, 410) and a second substrate (192, 1010) composed of the surrounding material; forming a first portion (101, 601) of the coaxial trace in the first substrate; forming a second portion (102, 1001) of the coaxial trace in the second substrate; aligning the first portion of the coaxial trace with the second portion of the coaxial trace; and bonding the first portion of the coaxial trace to the second portion of the coaxial trace.

Abstract: A method for manufacturing a micro-electro-mechanical device, which has supporting parts and operative parts, includes providing a first semiconductor wafer, having a first layer of semiconductor material and a second layer of semiconductor material arranged on top of the first layer, forming first supporting parts and first operative parts of the device in the second layer, forming temporary anchors in the first layer, and bonding the first wafer to a second wafer, with the second layer facing the second wafer. After bonding the first wafer and the second wafer together, second supporting parts and second operative parts of said device are formed in the first layer. The temporary anchors are removed from the first layer to free the operative parts formed therein.

Abstract: A deformable spacer for wafer bonding applications is disclosed. The spacer may be used to keep wafers separated until desired conditions are achieved.

Abstract: A method of producing a device with a movable portion spaced apart from a support wafer comprises a step of providing the support wafer having a structured surface and a further step of providing a device wafer with a backing layer and a device layer disposed thereon. Further, the method comprises the step of generating a first planarization layer from a first starting material on the support wafer with a first method to fill in the structures of the structured surface of the support wafer, whereby a surface with a first degree of planarization is obtained. Further, the method comprises a step of generating a second planarization layer from a second starting material on the planarized surface of the support wafer with a second method to obtain a surface with a second degree of planarization, which is higher than the first degree of planarization, wherein the first and second planarization layers can be removed together.

Abstract: Methods of fabricating comb drive devices utilizing one or more sacrificial etch-buffers are disclosed. An illustrative fabrication method may include the steps of etching a pattern onto a wafer substrate defining one or more comb drive elements and sacrificial etch-buffers, liberating and removing one or more sacrificial etch-buffers prior to wafer bonding, bonding the etched wafer substrate to an underlying support substrate, and etching away the wafer substrate. In some embodiments, the sacrificial etch-buffers are removed after bonding the wafer to the support substrate. The sacrificial etch-buffers can be provided at one or more selective regions to provide greater uniformity in etch rate during etching. A comb drive device in accordance with an illustrative embodiment can include a number of interdigitated comb fingers each having a more uniform profile along their length and/or at their ends, producing less harmonic distortion during operation.

Abstract: A process for joining substrates having electrical, semiconducting, mechanical and/or optical components, and to a composite element is provided. The process is to be suitable for substrates that are to be joined substantially irrespective of material and for sensitive substrates. According to the process, a raised frame, in particular formed from anodically bondable glass, is applied by evaporation coating to one of the two substrates in order to serve as a joining element.

Abstract: A Multiple Internal Seal Ring (MISR) Micro-Electro-Mechanical System (MEMS) vacuum packaging method that hermetically seals MEMS devices using MISR. The method bonds a capping plate having metal seal rings to a base plate having metal seal rings by wafer bonding the capping plate wafer to the base plate wafer. Bulk electrodes may be used to provide conductive paths between the seal rings on the base plate and the capping plate. All seals are made using only metal-to-metal seal rings deposited on the polished surfaces of the base plate and capping plate wafers. However, multiple electrical feed-through metal traces are provided by fabricating via holes through the capping plate for electrical connection from the outside of the package through the via-holes to the inside of the package. Each metal seal ring serves the dual purposes of hermetic sealing and providing the electrical feed-through metal trace.

Abstract: A method of manufacturing an external force detection sensor in which a sensor element is formed by through-hole dry etching of an element substrate, and an electrically conductive material is used as an etching stop layer during the dry etching.

Abstract: Semiconductor devices (300, 400, and 500) including an integrated circuit (IC) device (100) coupled to a micro-electro-mechanical systems (MEMS) device (200) and a method (600) for producing same are disclosed. The IC device includes a die seal ring (130) and the MEMS device includes a MEMS seal ring (230), and the IC device is coupled to the MEMS device via the die seal ring and the MEMS seal ring. The MEMS device may include one or more passive devices (450, 475) coupled to it. Moreover, a substrate (510) including an aperture (550) may be coupled to the passive device, wherein the aperture enables the passive device to be trimmed after being disposed on the MEMS device. The semiconductor devices include an RF signal path (486) and at least one other signal path (482 and 484), wherein the other signal path(s) may be an analog and/or a digital signal path.

Abstract: A process for producing a tube suitable for microfluidic devices. The process uses first and second wafers, each having a substantially uniform doping level. The first wafer has a first portion into which a channel is etched partially therethrough between second and third portions of the first wafer. The first wafer is then bonded to the second wafer so that a first portion of the second wafer overlies the first portion of the first wafer and encloses the channel to define a passage. The second wafer is then thinned so that the first portion thereof defines a thinned wall of the passage. Second and third portions of the second wafer and part of the second and third portions of the first wafer are then removed, and the thinned wall defined by the second wafer is bonded to a substrate such that the passage projects over a recess in the substrate surface. The second and third portions of the first wafer are then removed to define a tube with a freestanding portion.

Abstract: The invention is directed to a wafer bonding method for bonding a first wafer with a second wafer, wherein the first wafer has a first top surface and the second wafer has a second top surface formed thereon and the first wafer bonds with the second wafer in a manner that the first top surface of the first wafer is opposite the second top surface of the second wafer. The wafer bonding method comprises steps of adding a hydroxyl-ion-containing solution between the first top surface and the second top surface and then applying an external pressure on the first wafer and the second wafer. An annealing process is performed.

Abstract: Embodiments of a micro electro mechanical system are disclosed.

Abstract: Disclosed are embodiments of a method for forming a seal ring on a substrate that is anchored to the substrate by a number of vias. Also disclosed are embodiments of an assembly including such an anchored seal ring. In some embodiments, a seal ring may extend around the periphery of a MEMS device and may, in combination with a lid, provide a hermitic cavity enclosing the MEMS device. Other embodiments are described and claimed.

Abstract: A process for producing a tube suitable for microfluidic devices. The process uses a uniformly-doped first material having a first portion into which a channel is etched partially through the first material between second and third portions of the first material. The first material is then bonded to a second material so that a first portion of the second material overlies the first portion of the first material and encloses the channel to define a passage. The second and third portions of the second material and part of the second and third portions of the first material are then removed, and the first portion of the second material is bonded to a substrate such that the passage projects over a recess in the substrate surface. The second and third portions of the first material are then removed to define a tube with a freestanding portion.

Abstract: As disclosed herein, structures and methods are provided for forming capped chips. As provided by the disclosed method, a metal base pattern is formed on a chip insulated from wiring of the chip, and a cap is formed including a metal. The cap is joined to the metal base pattern on the chip to form the capped chip. In one embodiment, a front surface of the chip is exposed which extends from a contact of the chip to an edge of the chip. In another embodiment, a conductive connection is formed to the contact, the conductive connection extending from the contact to a terminal at an exposed plane above the front surface of the chip.

Abstract: A process manufactures a wafer using semiconductor processing techniques. A bonding layer is formed on a top surface of a first wafer; a deep trench is dug in a substrate of semiconductor material belonging to a second wafer. A top layer of semiconductor material is formed on top of the substrate so as to close the deep trench at the top and form at least one buried cavity. The top layer of the second wafer is bonded to the first wafer through the bonding layer. The two wafers are subjected to a thermal treatment that causes bonding of at least one portion of the top layer to the first wafer and widening of the buried cavity. In this way, the portion of the top layer bonded to the first wafer is separated from the rest of the second wafer, to form a composite wafer.